Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	585298	1			T2	1		T4	49		T5	501
auto[1]	10891998	1			T1	71872		T2	2		T3	2482
auto[2]	486770	1			T4	48		T5	254		T6	6973
auto[3]	10800337	1			T1	72552		T2	9		T3	2452

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14126196	1			T1	120287		T2	8		T3	4096
auto[1]	2239590	1			T1	11493		T2	1		T3	414
auto[2]	2261484	1			T1	11573		T2	3		T3	385
auto[3]	4137133	1			T1	1071		T3	39		T4	239

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8585660

1

T1

35

T2

12

T3

4928

auto[1]

14178743

1

T1

144389

T3

6

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	273883	1			T2	1		T5	423		T6	6336
auto[0]	auto[0]	auto[1]	28864	1			T4	2		T5	37		T6	640
auto[0]	auto[0]	auto[2]	28525	1			T4	1		T5	38		T6	658
auto[0]	auto[0]	auto[3]	9334	1			T4	46		T5	3		T6	66
auto[0]	auto[1]	auto[0]	3256065	1			T1	16		T2	2		T3	2062
auto[0]	auto[1]	auto[1]	341144	1			T3	213		T5	611		T6	693
auto[0]	auto[1]	auto[2]	330350	1			T1	2		T3	187		T4	4
auto[0]	auto[1]	auto[3]	70766	1			T3	18		T4	50		T5	62
auto[0]	auto[2]	auto[0]	232749	1			T6	5867		T9	1		T19	13
auto[0]	auto[2]	auto[1]	24230	1			T4	2		T6	585		T20	1
auto[0]	auto[2]	auto[2]	27413	1			T5	236		T6	466		T41	31
auto[0]	auto[2]	auto[3]	7535	1			T4	46		T5	18		T6	45
auto[0]	auto[3]	auto[0]	3216890	1			T1	15		T2	5		T3	2030
auto[0]	auto[3]	auto[1]	326598	1			T1	1		T2	1		T3	199
auto[0]	auto[3]	auto[2]	340175	1			T1	1		T2	3		T3	198
auto[0]	auto[3]	auto[3]	71139	1			T3	21		T4	96		T5	84
auto[1]	auto[0]	auto[0]	8159	1			T6	4		T42	344		T150	4
auto[1]	auto[0]	auto[1]	36030	1			T6	1		T42	1479		T150	1
auto[1]	auto[0]	auto[2]	36210	1			T6	1		T42	1453		T114	550
auto[1]	auto[0]	auto[3]	164293	1			T42	6862		T114	2595		T99	1
auto[1]	auto[1]	auto[0]	3567814	1			T1	60014		T3	1		T5	4
auto[1]	auto[1]	auto[1]	737260	1			T1	5304		T3	1		T10	4
auto[1]	auto[1]	auto[2]	736376	1			T1	6002		T10	4		T42	976
auto[1]	auto[1]	auto[3]	1852223	1			T1	534		T10	2		T42	7954
auto[1]	auto[2]	auto[0]	5306	1			T6	7		T42	196		T150	2
auto[1]	auto[2]	auto[1]	23012	1			T42	903		T150	1		T68	2863
auto[1]	auto[2]	auto[2]	30299	1			T6	3		T42	1721		T114	541
auto[1]	auto[2]	auto[3]	136226	1			T42	7394		T114	2408		T68	11508
auto[1]	auto[3]	auto[0]	3565330	1			T1	60242		T3	3		T5	1
auto[1]	auto[3]	auto[1]	722452	1			T1	6188		T3	1		T5	1
auto[1]	auto[3]	auto[2]	732136	1			T1	5568		T5	1		T9	1
auto[1]	auto[3]	auto[3]	1825617	1			T1	537		T4	1		T5	1