Module Definition
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Module : sram_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sram_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 311933018 164239 0 0
ctrl_regwen_rd_A 311933018 3187 0 0
exec_rd_A 311933018 2839 0 0
exec_regwen_rd_A 311933018 3081 0 0
readback_rd_A 311933018 1868 0 0
readback_regwen_rd_A 311933018 1757 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 311933018 164239 0 0
T21 61299 3855 0 0
T22 57298 1418 0 0
T23 0 3466 0 0
T45 0 8128 0 0
T46 0 6890 0 0
T47 0 6735 0 0
T51 17981 0 0 0
T59 0 5326 0 0
T61 0 1677 0 0
T76 0 4138 0 0
T77 0 10856 0 0
T78 385124 0 0 0
T79 92642 0 0 0
T80 436952 0 0 0
T81 1045 0 0 0
T82 14597 0 0 0
T83 304224 0 0 0
T84 103700 0 0 0

ctrl_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 311933018 3187 0 0
T22 57298 82 0 0
T47 0 455 0 0
T53 65097 0 0 0
T59 0 435 0 0
T81 1045 0 0 0
T82 14597 0 0 0
T83 304224 0 0 0
T84 103700 0 0 0
T118 0 72 0 0
T119 0 168 0 0
T120 0 151 0 0
T121 0 87 0 0
T122 0 316 0 0
T123 0 41 0 0
T124 0 152 0 0
T125 4384 0 0 0
T126 6923 0 0 0
T127 51311 0 0 0
T128 88553 0 0 0

exec_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 311933018 2839 0 0
T22 57298 46 0 0
T47 0 341 0 0
T53 65097 0 0 0
T59 0 275 0 0
T81 1045 0 0 0
T82 14597 0 0 0
T83 304224 0 0 0
T84 103700 0 0 0
T118 0 58 0 0
T119 0 188 0 0
T120 0 103 0 0
T121 0 70 0 0
T122 0 190 0 0
T123 0 75 0 0
T124 0 217 0 0
T125 4384 0 0 0
T126 6923 0 0 0
T127 51311 0 0 0
T128 88553 0 0 0

exec_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 311933018 3081 0 0
T22 57298 109 0 0
T47 0 466 0 0
T53 65097 0 0 0
T59 0 340 0 0
T81 1045 0 0 0
T82 14597 0 0 0
T83 304224 0 0 0
T84 103700 0 0 0
T118 0 43 0 0
T119 0 178 0 0
T120 0 144 0 0
T121 0 78 0 0
T122 0 297 0 0
T123 0 82 0 0
T124 0 170 0 0
T125 4384 0 0 0
T126 6923 0 0 0
T127 51311 0 0 0
T128 88553 0 0 0

readback_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 311933018 1868 0 0
T22 57298 48 0 0
T47 0 394 0 0
T53 65097 0 0 0
T59 0 362 0 0
T81 1045 0 0 0
T82 14597 0 0 0
T83 304224 0 0 0
T84 103700 0 0 0
T118 0 62 0 0
T119 0 111 0 0
T120 0 146 0 0
T121 0 90 0 0
T122 0 268 0 0
T123 0 54 0 0
T124 0 206 0 0
T125 4384 0 0 0
T126 6923 0 0 0
T127 51311 0 0 0
T128 88553 0 0 0

readback_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 311933018 1757 0 0
T22 57298 56 0 0
T47 0 401 0 0
T53 65097 0 0 0
T59 0 450 0 0
T81 1045 0 0 0
T82 14597 0 0 0
T83 304224 0 0 0
T84 103700 0 0 0
T118 0 59 0 0
T119 0 95 0 0
T120 0 93 0 0
T121 0 140 0 0
T122 0 202 0 0
T123 0 41 0 0
T124 0 143 0 0
T125 4384 0 0 0
T126 6923 0 0 0
T127 51311 0 0 0
T128 88553 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%