Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145616338	1			T1	9578		T2	1972		T4	358064
instr_valid_dis	112838883	1			T1	9578		T2	1972		T4	358064
instr_en	22846344	1			T25	11554		T27	253196		T26	384

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10619457	1			T27	123152		T31	38248		T21	143564
sram_ifetch_valid_disable	113511026	1			T1	9578		T2	1972		T4	358064
sram_ifetch_enable	21485855	1			T25	24582		T27	197546		T26	384

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145616338	1			T1	9578		T2	1972		T4	358064
hw_debug_en_valid_off	112671118	1			T1	9578		T2	1972		T4	358064
hw_debug_en_on	22169842	1			T25	30508		T27	116594		T31	26264

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113511026	1			T1	9578		T2	1972		T4	358064
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100275791	1			T1	9578		T2	1972		T4	358064
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9089902	1			T25	5926		T27	77250		T21	157660
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4620965	1			T27	38730		T31	20000		T21	78730
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2344812	1			T21	40888		T50	51562		T143	32122
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1418875	1			T27	38730		T21	37842		T132	8206
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4067850	1			T27	36448		T21	52160		T143	13422
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1384618	1			T27	36448		T21	926		T143	13422
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2005522	1			T21	51234		T132	103970		T124	41770
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9755298	1			T25	5926		T27	49110		T31	26264
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3998266	1			T27	49110		T21	450970		T50	92444
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3980358	1			T25	5926		T21	132712		T50	35514

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9494359	1			T25	5628		T27	98486		T26	384
lc_exec_en	8346694	1			T25	24582		T27	31036		T21	48274
valid_exec_dis	106942854	1			T1	9578		T2	1972		T4	358064
invalid_exec_dis	32105312	1			T25	24582		T27	320698		T26	384