Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1024
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.41 67.41 94.66 94.66 65.05 65.05 39.91 39.91 66.67 66.67 83.57 83.57 94.40 94.40 27.61 27.61 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3903042878
86.68 19.28 96.53 1.86 82.70 17.65 93.55 53.64 71.43 4.76 88.65 5.07 95.87 1.47 78.06 50.46 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.606040141
90.14 3.45 97.54 1.02 83.18 0.47 93.55 0.00 90.48 19.05 90.82 2.17 95.87 0.00 79.52 1.46 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2755848073
93.13 3.00 98.73 1.19 85.31 2.13 93.90 0.35 100.00 9.52 93.48 2.66 95.87 0.00 84.64 5.12 /workspace/coverage/default/15.sram_ctrl_stress_all.3730879866
94.26 1.12 98.73 0.00 87.44 2.13 95.56 1.66 100.00 0.00 94.69 1.21 96.17 0.29 87.20 2.56 /workspace/coverage/default/49.sram_ctrl_multiple_keys.1789632570
95.21 0.95 98.90 0.17 88.27 0.83 95.77 0.21 100.00 0.00 95.41 0.72 96.17 0.00 91.96 4.75 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.103452299
95.97 0.76 99.07 0.17 90.28 2.01 96.53 0.76 100.00 0.00 96.14 0.72 96.90 0.74 92.87 0.91 /workspace/coverage/default/0.sram_ctrl_sec_cm.49319489
96.26 0.29 99.07 0.00 90.28 0.00 97.68 1.14 100.00 0.00 96.14 0.00 96.90 0.00 93.78 0.91 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.726294958
96.52 0.25 99.07 0.00 90.52 0.24 98.30 0.62 100.00 0.00 96.14 0.00 96.90 0.00 94.70 0.91 /workspace/coverage/default/29.sram_ctrl_stress_all.2329613310
96.76 0.24 99.07 0.00 90.52 0.00 98.37 0.07 100.00 0.00 96.14 0.00 98.53 1.62 94.70 0.00 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1353489304
96.90 0.14 99.15 0.08 90.52 0.00 99.27 0.90 100.00 0.00 96.14 0.00 98.53 0.00 94.70 0.00 /workspace/coverage/default/24.sram_ctrl_ram_cfg.462123112
97.03 0.13 99.15 0.00 90.52 0.00 99.27 0.00 100.00 0.00 96.14 0.00 98.53 0.00 95.61 0.91 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.671469411
97.14 0.10 99.15 0.00 90.52 0.00 99.31 0.03 100.00 0.00 96.14 0.00 98.67 0.15 96.16 0.55 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.884589300
97.21 0.08 99.15 0.00 90.52 0.00 99.31 0.00 100.00 0.00 96.14 0.00 98.67 0.00 96.71 0.55 /workspace/coverage/default/39.sram_ctrl_stress_all.2713612716
97.28 0.07 99.15 0.00 90.88 0.36 99.45 0.14 100.00 0.00 96.14 0.00 98.67 0.00 96.71 0.00 /workspace/coverage/default/41.sram_ctrl_alert_test.3051968201
97.34 0.06 99.15 0.00 90.88 0.00 99.55 0.10 100.00 0.00 96.14 0.00 98.97 0.29 96.71 0.00 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2512189579
97.39 0.05 99.15 0.00 90.88 0.00 99.55 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.37 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1790318723
97.43 0.04 99.15 0.00 91.00 0.12 99.69 0.14 100.00 0.00 96.14 0.00 98.97 0.00 97.07 0.00 /workspace/coverage/default/17.sram_ctrl_stress_all.1528110681
97.46 0.03 99.15 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.509100012
97.48 0.03 99.15 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.14 0.00 98.97 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.517624269
97.50 0.02 99.15 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.14 0.00 99.12 0.15 97.44 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.145856936
97.51 0.01 99.15 0.00 91.00 0.00 99.72 0.03 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.00 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2436116606

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.131932917
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1780482451
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.78026988
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.658156676
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3816688152
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3414567275
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1645360837
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1869595841
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2770328998
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.366936709
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.496521347
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3804325157
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4236052914
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3811343497
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2935636027
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1157398949
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.384272770
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.934883215
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2483927626
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.40985363
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4173581033
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2417887756
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3327627310
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.575390335
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2876828949
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2105229651
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3061514559
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3188659923
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1478900955
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2302079005
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1911565416
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.607470002
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4140360172
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2393068654
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2307771594
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1061668021
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4150603278
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2954649166
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.181054464
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1734209387
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2726826768
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.494154142
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2235708385
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1763192947
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3054474919
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.570103975
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1810498937
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1193860926
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.615180131
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1622117049
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.907984444
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3129655172
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1138983897
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2107165591
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4114500015
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2029640078
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2574810154
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.92136287
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2194345037
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1885513563
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1216043046
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.210800037
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3347349132
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2077726124
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3819582180
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.803354277
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.74958608
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2967948665
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1462143648
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3914074752
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1254902014
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2589726969
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2313575927
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3150877537
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2461115030
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2177218579
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2105868307
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1694447796
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2598279656
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1229195591
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2235251708
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2787614878
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.863261455
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2891865374
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1671437955
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3488821592
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2882695429
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3701261598
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.432131752
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2926388228
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1213975179
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2025155222
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3030899965
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.509389379
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2986594215
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2759619493
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1899970822
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3576285862
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2541209565
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4219530117
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1073683460
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.981884949
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3079747517
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4012621121
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2939490703
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3638740300
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2517830311
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.256346799
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2370402274
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1695315662
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.334512456
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1742140666
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.948227401
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3033315440
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3372884188
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1955235373
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3920950670
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3886681481
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2698748929
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1559171642
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3372737011
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4169196785
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.226940285
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4060189195
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1062273504
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.197170216
/workspace/coverage/default/0.sram_ctrl_alert_test.2050965708
/workspace/coverage/default/0.sram_ctrl_bijection.1116177637
/workspace/coverage/default/0.sram_ctrl_executable.798906783
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2676436800
/workspace/coverage/default/0.sram_ctrl_max_throughput.3795501967
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3193777355
/workspace/coverage/default/0.sram_ctrl_mem_walk.627807644
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2257697183
/workspace/coverage/default/0.sram_ctrl_partial_access.2478699569
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1622282710
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2080028790
/workspace/coverage/default/0.sram_ctrl_regwen.602509211
/workspace/coverage/default/0.sram_ctrl_smoke.4214648959
/workspace/coverage/default/0.sram_ctrl_stress_all.3297274127
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.431896671
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4228232408
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.270901368
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4179388473
/workspace/coverage/default/1.sram_ctrl_alert_test.3220227894
/workspace/coverage/default/1.sram_ctrl_bijection.106047790
/workspace/coverage/default/1.sram_ctrl_executable.3590981804
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2263599679
/workspace/coverage/default/1.sram_ctrl_max_throughput.3978721234
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3331916131
/workspace/coverage/default/1.sram_ctrl_mem_walk.2480219859
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1804245663
/workspace/coverage/default/1.sram_ctrl_partial_access.2256609164
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.436727428
/workspace/coverage/default/1.sram_ctrl_ram_cfg.759650457
/workspace/coverage/default/1.sram_ctrl_regwen.1181440082
/workspace/coverage/default/1.sram_ctrl_sec_cm.641941293
/workspace/coverage/default/1.sram_ctrl_smoke.2208661728
/workspace/coverage/default/1.sram_ctrl_stress_all.2237658986
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1491268503
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.496517626
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3882542784
/workspace/coverage/default/10.sram_ctrl_alert_test.3025968483
/workspace/coverage/default/10.sram_ctrl_bijection.1997277115
/workspace/coverage/default/10.sram_ctrl_executable.24506313
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1416905248
/workspace/coverage/default/10.sram_ctrl_max_throughput.341569346
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1221907648
/workspace/coverage/default/10.sram_ctrl_mem_walk.4203760517
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2276532723
/workspace/coverage/default/10.sram_ctrl_partial_access.2952560545
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1175157492
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1007078181
/workspace/coverage/default/10.sram_ctrl_regwen.2315544879
/workspace/coverage/default/10.sram_ctrl_smoke.75547451
/workspace/coverage/default/10.sram_ctrl_stress_all.161428
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2264596209
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3441271294
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.19980923
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.192926503
/workspace/coverage/default/11.sram_ctrl_alert_test.4070165857
/workspace/coverage/default/11.sram_ctrl_bijection.3615681477
/workspace/coverage/default/11.sram_ctrl_executable.477205328
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2371384380
/workspace/coverage/default/11.sram_ctrl_max_throughput.99702668
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2172354828
/workspace/coverage/default/11.sram_ctrl_mem_walk.336389882
/workspace/coverage/default/11.sram_ctrl_multiple_keys.248057605
/workspace/coverage/default/11.sram_ctrl_partial_access.2854423650
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2033236510
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2521054373
/workspace/coverage/default/11.sram_ctrl_regwen.3830528038
/workspace/coverage/default/11.sram_ctrl_smoke.4088793280
/workspace/coverage/default/11.sram_ctrl_stress_all.2362162373
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1876575385
/workspace/coverage/default/12.sram_ctrl_alert_test.172335781
/workspace/coverage/default/12.sram_ctrl_bijection.3998585855
/workspace/coverage/default/12.sram_ctrl_executable.1536265762
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3590498344
/workspace/coverage/default/12.sram_ctrl_max_throughput.2419772025
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/workspace/coverage/default/43.sram_ctrl_lc_escalation.4287118101
/workspace/coverage/default/43.sram_ctrl_max_throughput.2212690735
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1557741874
/workspace/coverage/default/43.sram_ctrl_mem_walk.3093539216
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3983109435
/workspace/coverage/default/43.sram_ctrl_partial_access.2360861992
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2780220015
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1234902908
/workspace/coverage/default/43.sram_ctrl_regwen.2142519415
/workspace/coverage/default/43.sram_ctrl_smoke.1934128089
/workspace/coverage/default/43.sram_ctrl_stress_all.1169695120
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.43649824
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.370717948
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.373027919
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.847002902
/workspace/coverage/default/44.sram_ctrl_alert_test.3758430302
/workspace/coverage/default/44.sram_ctrl_bijection.1689211990
/workspace/coverage/default/44.sram_ctrl_executable.3441538590
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1752635235
/workspace/coverage/default/44.sram_ctrl_max_throughput.722842587
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.370322771
/workspace/coverage/default/44.sram_ctrl_mem_walk.1672524625
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2029112014
/workspace/coverage/default/44.sram_ctrl_partial_access.951145919
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3837574739
/workspace/coverage/default/44.sram_ctrl_ram_cfg.432935151
/workspace/coverage/default/44.sram_ctrl_regwen.1152929441
/workspace/coverage/default/44.sram_ctrl_smoke.2998542068
/workspace/coverage/default/44.sram_ctrl_stress_all.71067923
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1062126244
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3817386091
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.266869908
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.343346864
/workspace/coverage/default/45.sram_ctrl_alert_test.2903894271
/workspace/coverage/default/45.sram_ctrl_bijection.2506653830
/workspace/coverage/default/45.sram_ctrl_executable.3794013995
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2182634433
/workspace/coverage/default/45.sram_ctrl_max_throughput.3603544590
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1415137776
/workspace/coverage/default/45.sram_ctrl_mem_walk.3815718658
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1624701548
/workspace/coverage/default/45.sram_ctrl_partial_access.477476174
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.210279128
/workspace/coverage/default/45.sram_ctrl_ram_cfg.873360962
/workspace/coverage/default/45.sram_ctrl_regwen.3038319077
/workspace/coverage/default/45.sram_ctrl_smoke.1585634813
/workspace/coverage/default/45.sram_ctrl_stress_all.2639713913
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1122124257
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.632720476
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1266831258
/workspace/coverage/default/46.sram_ctrl_alert_test.119874633
/workspace/coverage/default/46.sram_ctrl_bijection.3650861907
/workspace/coverage/default/46.sram_ctrl_executable.1385392006
/workspace/coverage/default/46.sram_ctrl_lc_escalation.4038116735
/workspace/coverage/default/46.sram_ctrl_max_throughput.3461214535
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4271736755
/workspace/coverage/default/46.sram_ctrl_mem_walk.882470648
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3262427826
/workspace/coverage/default/46.sram_ctrl_partial_access.3422252807
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.170759883
/workspace/coverage/default/46.sram_ctrl_ram_cfg.251655526
/workspace/coverage/default/46.sram_ctrl_regwen.2629614776
/workspace/coverage/default/46.sram_ctrl_smoke.2323112204
/workspace/coverage/default/46.sram_ctrl_stress_all.887051870
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.160056051
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3315138342
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2765025946
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.383716465
/workspace/coverage/default/47.sram_ctrl_alert_test.3364809882
/workspace/coverage/default/47.sram_ctrl_bijection.2786900852
/workspace/coverage/default/47.sram_ctrl_executable.939636934
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4248449630
/workspace/coverage/default/47.sram_ctrl_max_throughput.171925055
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.168875215
/workspace/coverage/default/47.sram_ctrl_mem_walk.2118998901
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3238102197
/workspace/coverage/default/47.sram_ctrl_partial_access.3404512226
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2244984866
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3881935892
/workspace/coverage/default/47.sram_ctrl_regwen.2051597736
/workspace/coverage/default/47.sram_ctrl_smoke.2198599068
/workspace/coverage/default/47.sram_ctrl_stress_all.3398127442
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1371856345
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2655949004
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1862255609
/workspace/coverage/default/48.sram_ctrl_alert_test.4001430635
/workspace/coverage/default/48.sram_ctrl_bijection.419162802
/workspace/coverage/default/48.sram_ctrl_executable.3666947050
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2061932029
/workspace/coverage/default/48.sram_ctrl_max_throughput.3732495684
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1000050441
/workspace/coverage/default/48.sram_ctrl_mem_walk.1581207771
/workspace/coverage/default/48.sram_ctrl_multiple_keys.434202221
/workspace/coverage/default/48.sram_ctrl_partial_access.1070811403
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2497449316
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4274889149
/workspace/coverage/default/48.sram_ctrl_regwen.3786182033
/workspace/coverage/default/48.sram_ctrl_smoke.3833128372
/workspace/coverage/default/48.sram_ctrl_stress_all.2677114042
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3713919856
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1148396473
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2456505778
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.4142805464
/workspace/coverage/default/49.sram_ctrl_alert_test.2010073157
/workspace/coverage/default/49.sram_ctrl_bijection.3720102120
/workspace/coverage/default/49.sram_ctrl_executable.319079555
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2507737913
/workspace/coverage/default/49.sram_ctrl_max_throughput.257872111
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.190338035
/workspace/coverage/default/49.sram_ctrl_mem_walk.694428445
/workspace/coverage/default/49.sram_ctrl_partial_access.611584568
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.928058315
/workspace/coverage/default/49.sram_ctrl_ram_cfg.301165041
/workspace/coverage/default/49.sram_ctrl_regwen.3369803422
/workspace/coverage/default/49.sram_ctrl_smoke.3849364490
/workspace/coverage/default/49.sram_ctrl_stress_all.194824190
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2047371946
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1261795680
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1742530843
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3687700601
/workspace/coverage/default/5.sram_ctrl_alert_test.847354436
/workspace/coverage/default/5.sram_ctrl_bijection.1997833025
/workspace/coverage/default/5.sram_ctrl_executable.3077622325
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2715018007
/workspace/coverage/default/5.sram_ctrl_max_throughput.2679207406
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3468619782
/workspace/coverage/default/5.sram_ctrl_mem_walk.3548049690
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2808069664
/workspace/coverage/default/5.sram_ctrl_partial_access.3928224449
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1150444567
/workspace/coverage/default/5.sram_ctrl_ram_cfg.4229252041
/workspace/coverage/default/5.sram_ctrl_regwen.1997100625
/workspace/coverage/default/5.sram_ctrl_smoke.3398211481
/workspace/coverage/default/5.sram_ctrl_stress_all.2831909290
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.708394487
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4246568468
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3830442541
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3239472945
/workspace/coverage/default/6.sram_ctrl_alert_test.595670768
/workspace/coverage/default/6.sram_ctrl_bijection.1904622083
/workspace/coverage/default/6.sram_ctrl_executable.3428139549
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4093050143
/workspace/coverage/default/6.sram_ctrl_max_throughput.2495031671
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1093486075
/workspace/coverage/default/6.sram_ctrl_mem_walk.1565202035
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2740732606
/workspace/coverage/default/6.sram_ctrl_partial_access.2622012523
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3653800801
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1803182764
/workspace/coverage/default/6.sram_ctrl_regwen.2579231157
/workspace/coverage/default/6.sram_ctrl_smoke.1620736040
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1933250110
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1271799927
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4105881752
/workspace/coverage/default/7.sram_ctrl_alert_test.26745115
/workspace/coverage/default/7.sram_ctrl_bijection.2566543806
/workspace/coverage/default/7.sram_ctrl_executable.1313283532
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3638096241
/workspace/coverage/default/7.sram_ctrl_max_throughput.1298199651
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3525053300
/workspace/coverage/default/7.sram_ctrl_mem_walk.1363367998
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1537020247
/workspace/coverage/default/7.sram_ctrl_partial_access.3215325175
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.326562977
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3307251594
/workspace/coverage/default/7.sram_ctrl_regwen.3788451759
/workspace/coverage/default/7.sram_ctrl_smoke.1480665173
/workspace/coverage/default/7.sram_ctrl_stress_all.2670987417
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.444782838
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2160040224
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3669650054
/workspace/coverage/default/8.sram_ctrl_alert_test.3454095018
/workspace/coverage/default/8.sram_ctrl_bijection.2799921492
/workspace/coverage/default/8.sram_ctrl_executable.3812730882
/workspace/coverage/default/8.sram_ctrl_lc_escalation.96242264
/workspace/coverage/default/8.sram_ctrl_max_throughput.2172310776
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3652345622
/workspace/coverage/default/8.sram_ctrl_mem_walk.1121684347
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3058830580
/workspace/coverage/default/8.sram_ctrl_partial_access.1804983874
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.881940028
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2612049000
/workspace/coverage/default/8.sram_ctrl_regwen.3137870940
/workspace/coverage/default/8.sram_ctrl_smoke.1303971988
/workspace/coverage/default/8.sram_ctrl_stress_all.2357867605
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.884148830
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2596649463
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3906590590
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.410611177
/workspace/coverage/default/9.sram_ctrl_alert_test.1597836541
/workspace/coverage/default/9.sram_ctrl_bijection.2785981338
/workspace/coverage/default/9.sram_ctrl_executable.2907005894
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2323404855
/workspace/coverage/default/9.sram_ctrl_max_throughput.4112419603
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1790024016
/workspace/coverage/default/9.sram_ctrl_mem_walk.3677870350
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3765818659
/workspace/coverage/default/9.sram_ctrl_partial_access.2527508272
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3911343480
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1343078919
/workspace/coverage/default/9.sram_ctrl_regwen.3822268289
/workspace/coverage/default/9.sram_ctrl_smoke.1460734955
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.664955796
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1952413423
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1205715787



Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2765025946 Jul 11 05:18:02 PM PDT 24 Jul 11 05:18:28 PM PDT 24 358948617 ps
T2 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3903042878 Jul 11 05:14:44 PM PDT 24 Jul 11 05:14:49 PM PDT 24 383905901 ps
T3 /workspace/coverage/default/0.sram_ctrl_alert_test.2050965708 Jul 11 04:58:57 PM PDT 24 Jul 11 04:58:58 PM PDT 24 11333287 ps
T4 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2887211273 Jul 11 05:16:58 PM PDT 24 Jul 11 05:20:34 PM PDT 24 4381681957 ps
T5 /workspace/coverage/default/37.sram_ctrl_max_throughput.3677764764 Jul 11 05:17:19 PM PDT 24 Jul 11 05:17:22 PM PDT 24 186895185 ps
T9 /workspace/coverage/default/41.sram_ctrl_smoke.3501811828 Jul 11 05:17:14 PM PDT 24 Jul 11 05:17:29 PM PDT 24 421913237 ps
T10 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1491268503 Jul 11 04:59:07 PM PDT 24 Jul 11 05:05:33 PM PDT 24 4000160547 ps
T11 /workspace/coverage/default/15.sram_ctrl_smoke.146493294 Jul 11 05:13:57 PM PDT 24 Jul 11 05:16:09 PM PDT 24 2189339812 ps
T12 /workspace/coverage/default/17.sram_ctrl_smoke.1370563492 Jul 11 05:14:09 PM PDT 24 Jul 11 05:14:19 PM PDT 24 317875799 ps
T13 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2203635128 Jul 11 05:17:13 PM PDT 24 Jul 11 05:17:16 PM PDT 24 698770287 ps
T25 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.606040141 Jul 11 05:13:43 PM PDT 24 Jul 11 05:20:35 PM PDT 24 2475539274 ps
T32 /workspace/coverage/default/6.sram_ctrl_ram_cfg.1803182764 Jul 11 05:13:06 PM PDT 24 Jul 11 05:13:08 PM PDT 24 48398746 ps
T46 /workspace/coverage/default/1.sram_ctrl_partial_access.2256609164 Jul 11 04:59:07 PM PDT 24 Jul 11 04:59:22 PM PDT 24 1051897877 ps
T47 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2902492566 Jul 11 05:17:48 PM PDT 24 Jul 11 05:29:00 PM PDT 24 1833260526 ps
T44 /workspace/coverage/default/49.sram_ctrl_multiple_keys.1789632570 Jul 11 05:18:12 PM PDT 24 Jul 11 05:32:04 PM PDT 24 17358360708 ps
T28 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.726294958 Jul 11 05:14:58 PM PDT 24 Jul 11 05:15:04 PM PDT 24 157416672 ps
T29 /workspace/coverage/default/29.sram_ctrl_smoke.3587113386 Jul 11 05:15:58 PM PDT 24 Jul 11 05:16:04 PM PDT 24 195402312 ps
T70 /workspace/coverage/default/5.sram_ctrl_smoke.3398211481 Jul 11 05:12:34 PM PDT 24 Jul 11 05:12:42 PM PDT 24 126801200 ps
T19 /workspace/coverage/default/46.sram_ctrl_bijection.3650861907 Jul 11 05:17:41 PM PDT 24 Jul 11 05:18:16 PM PDT 24 549171535 ps
T71 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.590648211 Jul 11 05:14:44 PM PDT 24 Jul 11 05:19:48 PM PDT 24 11952569362 ps
T33 /workspace/coverage/default/21.sram_ctrl_ram_cfg.4180848942 Jul 11 05:14:44 PM PDT 24 Jul 11 05:14:46 PM PDT 24 53281374 ps
T45 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3770110833 Jul 11 05:14:39 PM PDT 24 Jul 11 05:17:26 PM PDT 24 13240702315 ps
T157 /workspace/coverage/default/16.sram_ctrl_partial_access.2872598612 Jul 11 05:14:10 PM PDT 24 Jul 11 05:14:18 PM PDT 24 1031481938 ps
T6 /workspace/coverage/default/30.sram_ctrl_lc_escalation.979735749 Jul 11 05:16:28 PM PDT 24 Jul 11 05:16:36 PM PDT 24 815332985 ps
T48 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2510985051 Jul 11 05:14:02 PM PDT 24 Jul 11 05:25:03 PM PDT 24 2714944404 ps
T51 /workspace/coverage/default/25.sram_ctrl_mem_walk.4060429422 Jul 11 05:15:06 PM PDT 24 Jul 11 05:15:18 PM PDT 24 362028629 ps
T64 /workspace/coverage/default/24.sram_ctrl_mem_walk.330547782 Jul 11 05:15:01 PM PDT 24 Jul 11 05:15:07 PM PDT 24 1253051775 ps
T65 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.884589300 Jul 11 05:13:28 PM PDT 24 Jul 11 05:16:08 PM PDT 24 6556284445 ps
T34 /workspace/coverage/default/13.sram_ctrl_ram_cfg.754769449 Jul 11 05:13:42 PM PDT 24 Jul 11 05:13:44 PM PDT 24 125522334 ps
T20 /workspace/coverage/default/25.sram_ctrl_bijection.4254852990 Jul 11 05:15:05 PM PDT 24 Jul 11 05:15:48 PM PDT 24 2300894475 ps
T49 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.847002902 Jul 11 05:17:44 PM PDT 24 Jul 11 05:49:07 PM PDT 24 5395574812 ps
T27 /workspace/coverage/default/1.sram_ctrl_executable.3590981804 Jul 11 04:58:45 PM PDT 24 Jul 11 05:23:23 PM PDT 24 4433776510 ps
T78 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3067623417 Jul 11 05:14:28 PM PDT 24 Jul 11 05:20:46 PM PDT 24 3927936895 ps
T26 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3288209151 Jul 11 05:14:55 PM PDT 24 Jul 11 05:22:32 PM PDT 24 2583803390 ps
T147 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3924113113 Jul 11 05:13:57 PM PDT 24 Jul 11 05:21:42 PM PDT 24 6529326471 ps
T93 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3615344563 Jul 11 05:17:12 PM PDT 24 Jul 11 05:17:18 PM PDT 24 153043866 ps
T148 /workspace/coverage/default/11.sram_ctrl_multiple_keys.248057605 Jul 11 05:13:30 PM PDT 24 Jul 11 05:33:09 PM PDT 24 20602693998 ps
T160 /workspace/coverage/default/11.sram_ctrl_bijection.3615681477 Jul 11 05:13:25 PM PDT 24 Jul 11 05:14:22 PM PDT 24 3074779535 ps
T94 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3669650054 Jul 11 05:13:17 PM PDT 24 Jul 11 05:22:09 PM PDT 24 5054807961 ps
T163 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3831002351 Jul 11 05:17:29 PM PDT 24 Jul 11 05:19:56 PM PDT 24 2942266823 ps
T164 /workspace/coverage/default/3.sram_ctrl_multiple_keys.1274273906 Jul 11 04:58:51 PM PDT 24 Jul 11 05:11:32 PM PDT 24 6734183302 ps
T31 /workspace/coverage/default/6.sram_ctrl_regwen.2579231157 Jul 11 05:12:54 PM PDT 24 Jul 11 05:25:14 PM PDT 24 3779021772 ps
T14 /workspace/coverage/default/38.sram_ctrl_alert_test.171525663 Jul 11 05:17:39 PM PDT 24 Jul 11 05:17:41 PM PDT 24 20745832 ps
T165 /workspace/coverage/default/24.sram_ctrl_ram_cfg.462123112 Jul 11 05:15:05 PM PDT 24 Jul 11 05:15:09 PM PDT 24 90345605 ps
T150 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2304393367 Jul 11 05:14:59 PM PDT 24 Jul 11 05:15:01 PM PDT 24 37808182 ps
T162 /workspace/coverage/default/39.sram_ctrl_ram_cfg.1994318511 Jul 11 05:17:08 PM PDT 24 Jul 11 05:17:10 PM PDT 24 27798803 ps
T156 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.266869908 Jul 11 05:17:44 PM PDT 24 Jul 11 05:19:20 PM PDT 24 132648128 ps
T111 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1371856345 Jul 11 05:17:51 PM PDT 24 Jul 11 05:21:26 PM PDT 24 4401780966 ps
T153 /workspace/coverage/default/7.sram_ctrl_max_throughput.1298199651 Jul 11 05:13:06 PM PDT 24 Jul 11 05:14:12 PM PDT 24 108374104 ps
T149 /workspace/coverage/default/14.sram_ctrl_multiple_keys.483710698 Jul 11 05:13:53 PM PDT 24 Jul 11 05:35:19 PM PDT 24 20584951359 ps
T166 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3906590590 Jul 11 05:13:18 PM PDT 24 Jul 11 05:13:42 PM PDT 24 111447496 ps
T21 /workspace/coverage/default/29.sram_ctrl_stress_all.2329613310 Jul 11 05:16:09 PM PDT 24 Jul 11 06:32:35 PM PDT 24 91563914932 ps
T15 /workspace/coverage/default/37.sram_ctrl_alert_test.4183064462 Jul 11 05:17:19 PM PDT 24 Jul 11 05:17:21 PM PDT 24 33630139 ps
T167 /workspace/coverage/default/3.sram_ctrl_partial_access.3026946460 Jul 11 04:59:09 PM PDT 24 Jul 11 05:00:02 PM PDT 24 1104445062 ps
T168 /workspace/coverage/default/36.sram_ctrl_multiple_keys.2549994737 Jul 11 05:16:52 PM PDT 24 Jul 11 05:28:41 PM PDT 24 2100230728 ps
T169 /workspace/coverage/default/31.sram_ctrl_smoke.508030892 Jul 11 05:16:39 PM PDT 24 Jul 11 05:16:51 PM PDT 24 667015440 ps
T54 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.168875215 Jul 11 05:17:54 PM PDT 24 Jul 11 05:18:03 PM PDT 24 203665926 ps
T151 /workspace/coverage/default/41.sram_ctrl_alert_test.3051968201 Jul 11 05:17:17 PM PDT 24 Jul 11 05:17:18 PM PDT 24 31164084 ps
T112 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2592120243 Jul 11 05:16:45 PM PDT 24 Jul 11 05:20:54 PM PDT 24 8483843154 ps
T170 /workspace/coverage/default/40.sram_ctrl_partial_access.3439232781 Jul 11 05:17:51 PM PDT 24 Jul 11 05:19:05 PM PDT 24 183609158 ps
T50 /workspace/coverage/default/31.sram_ctrl_executable.2601833674 Jul 11 05:16:29 PM PDT 24 Jul 11 05:37:58 PM PDT 24 32143226152 ps
T171 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3058830580 Jul 11 05:13:16 PM PDT 24 Jul 11 05:19:37 PM PDT 24 1252061720 ps
T7 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3655383585 Jul 11 05:14:28 PM PDT 24 Jul 11 05:14:31 PM PDT 24 270836283 ps
T113 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1506538036 Jul 11 05:14:12 PM PDT 24 Jul 11 05:19:10 PM PDT 24 7787302004 ps
T172 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2436116606 Jul 11 05:13:28 PM PDT 24 Jul 11 05:13:33 PM PDT 24 153837390 ps
T114 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2776964294 Jul 11 05:14:03 PM PDT 24 Jul 11 05:19:11 PM PDT 24 3268505285 ps
T8 /workspace/coverage/default/17.sram_ctrl_stress_all.1528110681 Jul 11 05:14:23 PM PDT 24 Jul 11 05:57:13 PM PDT 24 37408965077 ps
T55 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3652345622 Jul 11 05:13:20 PM PDT 24 Jul 11 05:13:24 PM PDT 24 406669954 ps
T173 /workspace/coverage/default/22.sram_ctrl_ram_cfg.1614106233 Jul 11 05:14:58 PM PDT 24 Jul 11 05:14:59 PM PDT 24 26477227 ps
T69 /workspace/coverage/default/25.sram_ctrl_regwen.1959766818 Jul 11 05:15:06 PM PDT 24 Jul 11 05:15:48 PM PDT 24 1631264786 ps
T174 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3876961970 Jul 11 05:13:52 PM PDT 24 Jul 11 05:18:26 PM PDT 24 11051565761 ps
T95 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3615500659 Jul 11 05:14:33 PM PDT 24 Jul 11 05:19:00 PM PDT 24 4867406748 ps
T155 /workspace/coverage/default/0.sram_ctrl_max_throughput.3795501967 Jul 11 04:58:43 PM PDT 24 Jul 11 04:58:48 PM PDT 24 212643092 ps
T175 /workspace/coverage/default/18.sram_ctrl_smoke.3138045091 Jul 11 05:14:17 PM PDT 24 Jul 11 05:14:38 PM PDT 24 2041925578 ps
T143 /workspace/coverage/default/20.sram_ctrl_executable.3056271439 Jul 11 05:14:39 PM PDT 24 Jul 11 05:20:44 PM PDT 24 16951728551 ps
T176 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3441271294 Jul 11 05:13:25 PM PDT 24 Jul 11 05:18:09 PM PDT 24 11845970355 ps
T161 /workspace/coverage/default/24.sram_ctrl_multiple_keys.667644865 Jul 11 05:14:55 PM PDT 24 Jul 11 05:17:28 PM PDT 24 746992118 ps
T177 /workspace/coverage/default/46.sram_ctrl_multiple_keys.3262427826 Jul 11 05:17:43 PM PDT 24 Jul 11 05:39:00 PM PDT 24 19081390398 ps
T56 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2260658895 Jul 11 05:17:09 PM PDT 24 Jul 11 05:17:16 PM PDT 24 183440148 ps
T154 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1807212002 Jul 11 05:17:20 PM PDT 24 Jul 11 05:28:08 PM PDT 24 2576674262 ps
T178 /workspace/coverage/default/16.sram_ctrl_max_throughput.1363073619 Jul 11 05:14:10 PM PDT 24 Jul 11 05:14:13 PM PDT 24 103289270 ps
T179 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2581878440 Jul 11 05:14:41 PM PDT 24 Jul 11 05:14:47 PM PDT 24 151325101 ps
T180 /workspace/coverage/default/16.sram_ctrl_smoke.3357566936 Jul 11 05:13:56 PM PDT 24 Jul 11 05:14:00 PM PDT 24 93611523 ps
T181 /workspace/coverage/default/26.sram_ctrl_max_throughput.3126391957 Jul 11 05:15:12 PM PDT 24 Jul 11 05:16:30 PM PDT 24 546661749 ps
T182 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.148223026 Jul 11 05:17:14 PM PDT 24 Jul 11 05:41:49 PM PDT 24 20792352092 ps
T158 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.299464250 Jul 11 05:15:51 PM PDT 24 Jul 11 05:19:34 PM PDT 24 11327071343 ps
T57 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1093486075 Jul 11 05:12:42 PM PDT 24 Jul 11 05:12:46 PM PDT 24 60642820 ps
T183 /workspace/coverage/default/41.sram_ctrl_max_throughput.2283165639 Jul 11 05:17:17 PM PDT 24 Jul 11 05:17:22 PM PDT 24 95393766 ps
T159 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1905971282 Jul 11 05:15:57 PM PDT 24 Jul 11 05:22:11 PM PDT 24 7864725010 ps
T16 /workspace/coverage/default/0.sram_ctrl_sec_cm.49319489 Jul 11 04:58:45 PM PDT 24 Jul 11 04:58:50 PM PDT 24 461007203 ps
T37 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3247448144 Jul 11 05:14:24 PM PDT 24 Jul 11 05:18:03 PM PDT 24 11728591570 ps
T38 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.373027919 Jul 11 05:17:27 PM PDT 24 Jul 11 05:17:32 PM PDT 24 50638977 ps
T39 /workspace/coverage/default/12.sram_ctrl_bijection.3998585855 Jul 11 05:13:38 PM PDT 24 Jul 11 05:13:55 PM PDT 24 1867003366 ps
T40 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2521054373 Jul 11 05:13:31 PM PDT 24 Jul 11 05:13:34 PM PDT 24 84986224 ps
T22 /workspace/coverage/default/44.sram_ctrl_regwen.1152929441 Jul 11 05:17:46 PM PDT 24 Jul 11 05:33:19 PM PDT 24 12175189511 ps
T24 /workspace/coverage/default/26.sram_ctrl_lc_escalation.4236838688 Jul 11 05:15:09 PM PDT 24 Jul 11 05:15:20 PM PDT 24 3427481423 ps
T41 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1130620219 Jul 11 05:13:37 PM PDT 24 Jul 11 05:19:51 PM PDT 24 13996979809 ps
T42 /workspace/coverage/default/22.sram_ctrl_alert_test.11151350 Jul 11 05:15:05 PM PDT 24 Jul 11 05:15:09 PM PDT 24 12613800 ps
T43 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3895213984 Jul 11 05:17:09 PM PDT 24 Jul 11 05:17:20 PM PDT 24 1186366576 ps
T152 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4163434366 Jul 11 04:58:54 PM PDT 24 Jul 11 04:59:53 PM PDT 24 275648903 ps
T184 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2979463412 Jul 11 05:16:58 PM PDT 24 Jul 11 05:22:42 PM PDT 24 15098222468 ps
T185 /workspace/coverage/default/27.sram_ctrl_ram_cfg.385865995 Jul 11 05:15:52 PM PDT 24 Jul 11 05:15:55 PM PDT 24 271880277 ps
T186 /workspace/coverage/default/10.sram_ctrl_smoke.75547451 Jul 11 05:13:14 PM PDT 24 Jul 11 05:13:56 PM PDT 24 3374546700 ps
T23 /workspace/coverage/default/34.sram_ctrl_regwen.2501409749 Jul 11 05:28:37 PM PDT 24 Jul 11 05:31:34 PM PDT 24 51197880592 ps
T187 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4062281701 Jul 11 05:15:11 PM PDT 24 Jul 11 05:16:07 PM PDT 24 113332882 ps
T188 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.967885275 Jul 11 05:14:59 PM PDT 24 Jul 11 05:18:37 PM PDT 24 2305675744 ps
T30 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2755848073 Jul 11 05:16:10 PM PDT 24 Jul 11 05:21:18 PM PDT 24 2063505227 ps
T189 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2506963677 Jul 11 04:58:49 PM PDT 24 Jul 11 05:00:15 PM PDT 24 1575606323 ps
T190 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1742858776 Jul 11 05:15:19 PM PDT 24 Jul 11 05:18:21 PM PDT 24 7344024576 ps
T191 /workspace/coverage/default/16.sram_ctrl_alert_test.3090544876 Jul 11 05:14:13 PM PDT 24 Jul 11 05:14:15 PM PDT 24 23002231 ps
T192 /workspace/coverage/default/25.sram_ctrl_smoke.1910287106 Jul 11 05:15:01 PM PDT 24 Jul 11 05:15:16 PM PDT 24 1484909026 ps
T144 /workspace/coverage/default/3.sram_ctrl_executable.1250685379 Jul 11 04:58:54 PM PDT 24 Jul 11 05:05:26 PM PDT 24 5398743983 ps
T193 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3464245541 Jul 11 05:13:28 PM PDT 24 Jul 11 05:15:45 PM PDT 24 1428144070 ps
T132 /workspace/coverage/default/39.sram_ctrl_stress_all.2713612716 Jul 11 05:17:09 PM PDT 24 Jul 11 05:52:53 PM PDT 24 648923547579 ps
T58 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3885243915 Jul 11 05:12:34 PM PDT 24 Jul 11 05:15:14 PM PDT 24 2071510267 ps
T123 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2596649463 Jul 11 05:12:58 PM PDT 24 Jul 11 05:17:41 PM PDT 24 2954856947 ps
T124 /workspace/coverage/default/15.sram_ctrl_stress_all.3730879866 Jul 11 05:13:59 PM PDT 24 Jul 11 05:54:39 PM PDT 24 13152800781 ps
T125 /workspace/coverage/default/25.sram_ctrl_multiple_keys.2542345013 Jul 11 05:15:08 PM PDT 24 Jul 11 05:27:54 PM PDT 24 28852657738 ps
T126 /workspace/coverage/default/7.sram_ctrl_alert_test.26745115 Jul 11 05:13:13 PM PDT 24 Jul 11 05:13:14 PM PDT 24 55414573 ps
T127 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.423478236 Jul 11 05:15:52 PM PDT 24 Jul 11 05:21:14 PM PDT 24 71181979411 ps
T128 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1205715787 Jul 11 05:13:12 PM PDT 24 Jul 11 05:13:32 PM PDT 24 92486251 ps
T129 /workspace/coverage/default/10.sram_ctrl_alert_test.3025968483 Jul 11 05:13:30 PM PDT 24 Jul 11 05:13:33 PM PDT 24 15183810 ps
T130 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.221682632 Jul 11 05:14:04 PM PDT 24 Jul 11 05:15:46 PM PDT 24 527405941 ps
T59 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3963032335 Jul 11 05:14:10 PM PDT 24 Jul 11 05:14:15 PM PDT 24 68164547 ps
T194 /workspace/coverage/default/44.sram_ctrl_ram_cfg.432935151 Jul 11 05:17:44 PM PDT 24 Jul 11 05:17:46 PM PDT 24 43830299 ps
T195 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.116042346 Jul 11 05:16:29 PM PDT 24 Jul 11 05:16:33 PM PDT 24 43959523 ps
T60 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3074915456 Jul 11 05:16:54 PM PDT 24 Jul 11 05:16:58 PM PDT 24 260873528 ps
T196 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2207711198 Jul 11 05:16:18 PM PDT 24 Jul 11 05:22:29 PM PDT 24 55279027053 ps
T197 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3239472945 Jul 11 05:12:57 PM PDT 24 Jul 11 05:31:20 PM PDT 24 3348951614 ps
T198 /workspace/coverage/default/13.sram_ctrl_mem_walk.2365851546 Jul 11 05:13:53 PM PDT 24 Jul 11 05:14:01 PM PDT 24 106190089 ps
T199 /workspace/coverage/default/31.sram_ctrl_mem_walk.1992715359 Jul 11 05:16:28 PM PDT 24 Jul 11 05:16:36 PM PDT 24 309926059 ps
T200 /workspace/coverage/default/34.sram_ctrl_alert_test.2245010974 Jul 11 05:17:10 PM PDT 24 Jul 11 05:17:12 PM PDT 24 14521245 ps
T201 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.632720476 Jul 11 05:17:43 PM PDT 24 Jul 11 05:18:13 PM PDT 24 100152908 ps
T202 /workspace/coverage/default/10.sram_ctrl_max_throughput.341569346 Jul 11 05:13:17 PM PDT 24 Jul 11 05:15:27 PM PDT 24 556528345 ps
T203 /workspace/coverage/default/42.sram_ctrl_smoke.816460008 Jul 11 05:17:17 PM PDT 24 Jul 11 05:17:29 PM PDT 24 1834341959 ps
T204 /workspace/coverage/default/36.sram_ctrl_mem_walk.2044515145 Jul 11 05:17:26 PM PDT 24 Jul 11 05:17:39 PM PDT 24 2171660631 ps
T205 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1349348296 Jul 11 04:58:55 PM PDT 24 Jul 11 05:04:24 PM PDT 24 53032650048 ps
T206 /workspace/coverage/default/44.sram_ctrl_stress_all.71067923 Jul 11 05:17:31 PM PDT 24 Jul 11 05:42:31 PM PDT 24 82475946820 ps
T207 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3509045523 Jul 11 05:17:23 PM PDT 24 Jul 11 05:21:36 PM PDT 24 44528040703 ps
T208 /workspace/coverage/default/47.sram_ctrl_smoke.2198599068 Jul 11 05:18:01 PM PDT 24 Jul 11 05:18:19 PM PDT 24 331587382 ps
T209 /workspace/coverage/default/18.sram_ctrl_ram_cfg.889401109 Jul 11 05:14:35 PM PDT 24 Jul 11 05:14:37 PM PDT 24 29816976 ps
T210 /workspace/coverage/default/13.sram_ctrl_max_throughput.702039897 Jul 11 05:13:55 PM PDT 24 Jul 11 05:14:53 PM PDT 24 209166794 ps
T211 /workspace/coverage/default/11.sram_ctrl_executable.477205328 Jul 11 05:13:26 PM PDT 24 Jul 11 05:16:52 PM PDT 24 3465628755 ps
T212 /workspace/coverage/default/29.sram_ctrl_partial_access.2865985128 Jul 11 05:15:59 PM PDT 24 Jul 11 05:16:05 PM PDT 24 1161238335 ps
T213 /workspace/coverage/default/7.sram_ctrl_partial_access.3215325175 Jul 11 05:12:55 PM PDT 24 Jul 11 05:12:58 PM PDT 24 71095402 ps
T72 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1076160935 Jul 11 05:16:28 PM PDT 24 Jul 11 05:22:23 PM PDT 24 10634699531 ps
T214 /workspace/coverage/default/20.sram_ctrl_lc_escalation.691025198 Jul 11 05:14:40 PM PDT 24 Jul 11 05:14:44 PM PDT 24 385195841 ps
T146 /workspace/coverage/default/24.sram_ctrl_regwen.850180988 Jul 11 05:15:01 PM PDT 24 Jul 11 05:34:03 PM PDT 24 12491637484 ps
T215 /workspace/coverage/default/30.sram_ctrl_mem_walk.546661270 Jul 11 05:16:39 PM PDT 24 Jul 11 05:16:52 PM PDT 24 2617361631 ps
T216 /workspace/coverage/default/8.sram_ctrl_stress_all.2357867605 Jul 11 05:13:00 PM PDT 24 Jul 11 07:08:12 PM PDT 24 579695930274 ps
T217 /workspace/coverage/default/5.sram_ctrl_executable.3077622325 Jul 11 05:12:46 PM PDT 24 Jul 11 05:25:50 PM PDT 24 7491933433 ps
T218 /workspace/coverage/default/36.sram_ctrl_ram_cfg.1026427616 Jul 11 05:17:29 PM PDT 24 Jul 11 05:17:32 PM PDT 24 28099343 ps
T219 /workspace/coverage/default/23.sram_ctrl_ram_cfg.4269095681 Jul 11 05:14:50 PM PDT 24 Jul 11 05:14:52 PM PDT 24 81526754 ps
T96 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.4279370505 Jul 11 05:14:49 PM PDT 24 Jul 11 05:14:53 PM PDT 24 461285191 ps
T220 /workspace/coverage/default/5.sram_ctrl_lc_escalation.2715018007 Jul 11 05:12:45 PM PDT 24 Jul 11 05:12:55 PM PDT 24 3917259740 ps
T221 /workspace/coverage/default/0.sram_ctrl_ram_cfg.2080028790 Jul 11 04:58:41 PM PDT 24 Jul 11 04:58:44 PM PDT 24 44900311 ps
T222 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1862255609 Jul 11 05:17:55 PM PDT 24 Jul 11 05:30:59 PM PDT 24 15316967714 ps
T223 /workspace/coverage/default/23.sram_ctrl_mem_walk.3037941914 Jul 11 05:14:50 PM PDT 24 Jul 11 05:14:56 PM PDT 24 71705416 ps
T224 /workspace/coverage/default/13.sram_ctrl_bijection.2008249621 Jul 11 05:13:55 PM PDT 24 Jul 11 05:14:50 PM PDT 24 2459159957 ps
T225 /workspace/coverage/default/16.sram_ctrl_lc_escalation.3706271216 Jul 11 05:14:11 PM PDT 24 Jul 11 05:14:18 PM PDT 24 541527986 ps
T226 /workspace/coverage/default/33.sram_ctrl_smoke.2723173690 Jul 11 05:16:37 PM PDT 24 Jul 11 05:16:45 PM PDT 24 227968461 ps
T73 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.884148830 Jul 11 05:13:14 PM PDT 24 Jul 11 05:17:06 PM PDT 24 590155209 ps
T227 /workspace/coverage/default/38.sram_ctrl_multiple_keys.1573997212 Jul 11 05:17:39 PM PDT 24 Jul 11 05:24:24 PM PDT 24 51230233232 ps
T228 /workspace/coverage/default/47.sram_ctrl_alert_test.3364809882 Jul 11 05:18:15 PM PDT 24 Jul 11 05:18:18 PM PDT 24 17932415 ps
T229 /workspace/coverage/default/24.sram_ctrl_bijection.1770481731 Jul 11 05:14:54 PM PDT 24 Jul 11 05:15:21 PM PDT 24 1584626557 ps
T230 /workspace/coverage/default/7.sram_ctrl_mem_walk.1363367998 Jul 11 05:13:09 PM PDT 24 Jul 11 05:13:16 PM PDT 24 606877537 ps
T231 /workspace/coverage/default/47.sram_ctrl_executable.939636934 Jul 11 05:18:15 PM PDT 24 Jul 11 05:32:32 PM PDT 24 5909120730 ps
T232 /workspace/coverage/default/0.sram_ctrl_partial_access.2478699569 Jul 11 04:58:57 PM PDT 24 Jul 11 04:59:49 PM PDT 24 301223480 ps
T233 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2456505778 Jul 11 05:18:15 PM PDT 24 Jul 11 05:18:35 PM PDT 24 164073721 ps
T234 /workspace/coverage/default/28.sram_ctrl_alert_test.710110151 Jul 11 05:16:02 PM PDT 24 Jul 11 05:16:03 PM PDT 24 15293531 ps
T235 /workspace/coverage/default/42.sram_ctrl_bijection.2754529024 Jul 11 05:17:44 PM PDT 24 Jul 11 05:18:25 PM PDT 24 1508845454 ps
T236 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2061932029 Jul 11 05:18:15 PM PDT 24 Jul 11 05:18:25 PM PDT 24 686191239 ps
T237 /workspace/coverage/default/17.sram_ctrl_partial_access.2924925770 Jul 11 05:14:13 PM PDT 24 Jul 11 05:14:29 PM PDT 24 2611695988 ps
T238 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3817386091 Jul 11 05:17:31 PM PDT 24 Jul 11 05:22:49 PM PDT 24 3475575518 ps
T239 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3825644797 Jul 11 05:15:06 PM PDT 24 Jul 11 05:18:13 PM PDT 24 1978824072 ps
T240 /workspace/coverage/default/39.sram_ctrl_executable.830300079 Jul 11 05:17:11 PM PDT 24 Jul 11 05:31:31 PM PDT 24 6767218504 ps
T241 /workspace/coverage/default/28.sram_ctrl_stress_all.474983969 Jul 11 05:16:03 PM PDT 24 Jul 11 05:48:25 PM PDT 24 84088838775 ps
T242 /workspace/coverage/default/2.sram_ctrl_smoke.1572298415 Jul 11 04:59:00 PM PDT 24 Jul 11 04:59:53 PM PDT 24 521341742 ps
T243 /workspace/coverage/default/13.sram_ctrl_partial_access.3890966365 Jul 11 05:13:53 PM PDT 24 Jul 11 05:13:58 PM PDT 24 102103359 ps
T244 /workspace/coverage/default/5.sram_ctrl_alert_test.847354436 Jul 11 05:12:51 PM PDT 24 Jul 11 05:12:53 PM PDT 24 13361551 ps
T245 /workspace/coverage/default/35.sram_ctrl_mem_walk.4183976487 Jul 11 05:17:07 PM PDT 24 Jul 11 05:17:13 PM PDT 24 459008093 ps
T246 /workspace/coverage/default/17.sram_ctrl_mem_walk.4081625187 Jul 11 05:14:19 PM PDT 24 Jul 11 05:14:27 PM PDT 24 229094255 ps
T247 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3863418226 Jul 11 05:16:36 PM PDT 24 Jul 11 05:22:16 PM PDT 24 82265926276 ps
T248 /workspace/coverage/default/35.sram_ctrl_ram_cfg.1837373164 Jul 11 05:16:59 PM PDT 24 Jul 11 05:17:01 PM PDT 24 29412184 ps
T249 /workspace/coverage/default/42.sram_ctrl_alert_test.1548295983 Jul 11 05:17:20 PM PDT 24 Jul 11 05:17:22 PM PDT 24 80093484 ps
T250 /workspace/coverage/default/27.sram_ctrl_stress_all.3591158515 Jul 11 05:15:57 PM PDT 24 Jul 11 05:52:05 PM PDT 24 7668516677 ps
T251 /workspace/coverage/default/18.sram_ctrl_max_throughput.821224143 Jul 11 05:14:26 PM PDT 24 Jul 11 05:14:29 PM PDT 24 68295393 ps
T252 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1271799927 Jul 11 05:12:54 PM PDT 24 Jul 11 05:14:23 PM PDT 24 269984866 ps
T253 /workspace/coverage/default/18.sram_ctrl_partial_access.494380286 Jul 11 05:14:31 PM PDT 24 Jul 11 05:15:24 PM PDT 24 525510876 ps
T254 /workspace/coverage/default/27.sram_ctrl_mem_walk.4085264980 Jul 11 05:15:51 PM PDT 24 Jul 11 05:16:04 PM PDT 24 718200654 ps
T255 /workspace/coverage/default/40.sram_ctrl_bijection.1176776090 Jul 11 05:17:51 PM PDT 24 Jul 11 05:18:39 PM PDT 24 8695408073 ps
T256 /workspace/coverage/default/13.sram_ctrl_alert_test.1761348172 Jul 11 05:13:59 PM PDT 24 Jul 11 05:14:01 PM PDT 24 20700173 ps
T257 /workspace/coverage/default/6.sram_ctrl_multiple_keys.2740732606 Jul 11 05:12:39 PM PDT 24 Jul 11 05:34:41 PM PDT 24 57611024492 ps
T258 /workspace/coverage/default/4.sram_ctrl_bijection.1846672595 Jul 11 04:59:05 PM PDT 24 Jul 11 05:00:04 PM PDT 24 7004636685 ps
T259 /workspace/coverage/default/34.sram_ctrl_lc_escalation.2413787925 Jul 11 05:16:59 PM PDT 24 Jul 11 05:17:07 PM PDT 24 500639104 ps
T74 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2174256141 Jul 11 05:16:35 PM PDT 24 Jul 11 05:17:08 PM PDT 24 1787709641 ps
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T262 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3190428770 Jul 11 05:15:11 PM PDT 24 Jul 11 05:15:14 PM PDT 24 167442404 ps
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T273 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.68163203 Jul 11 04:59:02 PM PDT 24 Jul 11 05:01:16 PM PDT 24 1381719969 ps
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T278 /workspace/coverage/default/46.sram_ctrl_alert_test.119874633 Jul 11 05:17:52 PM PDT 24 Jul 11 05:17:55 PM PDT 24 21127520 ps
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T298 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1343112889 Jul 11 05:14:01 PM PDT 24 Jul 11 05:14:06 PM PDT 24 263891103 ps
T299 /workspace/coverage/default/15.sram_ctrl_partial_access.2156525318 Jul 11 05:14:10 PM PDT 24 Jul 11 05:14:55 PM PDT 24 632313108 ps
T300 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2676436800 Jul 11 04:58:53 PM PDT 24 Jul 11 04:59:02 PM PDT 24 614464360 ps
T301 /workspace/coverage/default/42.sram_ctrl_lc_escalation.1008285948 Jul 11 05:17:48 PM PDT 24 Jul 11 05:17:54 PM PDT 24 1978729160 ps
T302 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1965752065 Jul 11 05:12:21 PM PDT 24 Jul 11 05:12:25 PM PDT 24 59049476 ps
T303 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2264827993 Jul 11 05:16:25 PM PDT 24 Jul 11 05:24:30 PM PDT 24 4361725037 ps
T304 /workspace/coverage/default/4.sram_ctrl_partial_access.1352921152 Jul 11 05:12:13 PM PDT 24 Jul 11 05:12:32 PM PDT 24 3616995598 ps
T305 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.358265732 Jul 11 05:14:43 PM PDT 24 Jul 11 05:15:06 PM PDT 24 335421666 ps
T306 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.4105881752 Jul 11 05:13:07 PM PDT 24 Jul 11 05:21:02 PM PDT 24 7531953031 ps
T307 /workspace/coverage/default/17.sram_ctrl_ram_cfg.3643933814 Jul 11 05:14:25 PM PDT 24 Jul 11 05:14:28 PM PDT 24 31618957 ps
T308 /workspace/coverage/default/47.sram_ctrl_max_throughput.171925055 Jul 11 05:17:51 PM PDT 24 Jul 11 05:19:25 PM PDT 24 495786230 ps
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