Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43537715	1			T1	3939		T2	54		T4	162683
triple_byte_access	2515129	1			T1	177		T2	108		T4	3276
halfword_access	3770033	1			T1	251		T2	246		T4	4834
byte_access	5042672	1			T1	353		T2	382		T4	6606
zero_access	1269222	1			T1	69		T2	196		T4	1633

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28021578

1

T1

2415

T2

364

T4

89837

auto[1]

28113193

1

T1

2374

T2

622

T4

89195

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21722942	1			T1	2010		T2	2		T4	81693
auto[0]	triple_byte_access	1255216	1			T1	86		T2	11		T4	1661
auto[0]	halfword_access	1882170	1			T1	111		T2	60		T4	2410
auto[0]	byte_access	2522791	1			T1	172		T2	142		T4	3259
auto[0]	zero_access	638459	1			T1	36		T2	149		T4	814
auto[1]	word_access	21814773	1			T1	1929		T2	52		T4	80990
auto[1]	triple_byte_access	1259913	1			T1	91		T2	97		T4	1615
auto[1]	halfword_access	1887863	1			T1	140		T2	186		T4	2424
auto[1]	byte_access	2519881	1			T1	181		T2	240		T4	3347
auto[1]	zero_access	630763	1			T1	33		T2	47		T4	819