Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148312800	1			T1	695700		T2	6142		T3	105633
instr_valid_dis	114322884	1			T1	695700		T2	6142		T3	529062
instr_en	24947349	1			T3	435284		T24	203438		T5	195950

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11127374	1			T3	199882		T8	214386		T24	119408
sram_ifetch_valid_disable	113879582	1			T1	695700		T2	6142		T3	618024
sram_ifetch_enable	23305844	1			T3	238430		T8	535106		T21	19704

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148312800	1			T1	695700		T2	6142		T3	105633
hw_debug_en_valid_off	114977316	1			T1	695700		T2	6142		T3	686256
hw_debug_en_on	21558198	1			T3	193028		T8	543488		T24	214142

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113879582	1			T1	695700		T2	6142		T3	618024
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100210644	1			T1	695700		T2	6142		T3	400202
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9716085	1			T3	151546		T24	40618		T5	38118
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4682412	1			T3	149054		T8	57086		T24	31290
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1776444	1			T3	63590		T8	57086		T24	12922
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1990278	1			T3	73372		T24	18368		T143	56022
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4207816	1			T3	21156		T8	139778		T24	76044
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1630280	1			T8	139778		T18	7978		T144	42878
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2010350	1			T3	21156		T24	76044		T5	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9356996	1			T3	108650		T8	248674		T24	40618
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3664681	1			T3	17452		T8	248674		T62	19326
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4019553	1			T3	24922		T24	20618		T62	20000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10418278	1			T3	189210		T24	68408		T5	86380
lc_exec_en	7993386	1			T3	63222		T8	155036		T24	97480
valid_exec_dis	109881200	1			T1	695700		T2	6142		T3	518812
invalid_exec_dis	34433218	1			T3	438312		T8	749492		T21	19704