Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44360377	1			T1	317363		T2	3071		T3	279517
triple_byte_access	2486574	1			T1	5809		T3	5432		T4	23
halfword_access	3728914	1			T1	8714		T3	8415		T4	30
byte_access	4980801	1			T1	11589		T3	11061		T4	54
zero_access	1255465	1			T1	2867		T3	2870		T4	18

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28348570

1

T1

173258

T2

1024

T3

153496

auto[1]

28463561

1

T1

173084

T2

2047

T3

153799

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22127294	1			T1	158648		T2	1024		T3	139569
auto[0]	triple_byte_access	1239979	1			T1	2924		T3	2712		T4	11
auto[0]	halfword_access	1860678	1			T1	4374		T3	4248		T4	13
auto[0]	byte_access	2489432	1			T1	5856		T3	5540		T4	21
auto[0]	zero_access	631187	1			T1	1456		T3	1427		T4	5
auto[1]	word_access	22233083	1			T1	158715		T2	2047		T3	139948
auto[1]	triple_byte_access	1246595	1			T1	2885		T3	2720		T4	12
auto[1]	halfword_access	1868236	1			T1	4340		T3	4167		T4	17
auto[1]	byte_access	2491369	1			T1	5733		T3	5521		T4	33
auto[1]	zero_access	624278	1			T1	1411		T3	1443		T4	13