Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147218834	1			T1	198088		T3	335368		T4	242578
instr_valid_dis	111996491	1			T1	198088		T3	335368		T4	194200
instr_en	24789404	1			T4	48378		T20	607984		T22	566936

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11604444	1			T4	78430		T20	71560		T21	156142
sram_ifetch_valid_disable	113784504	1			T1	198088		T3	335368		T4	142180
sram_ifetch_enable	21829886	1			T4	21968		T20	363728		T21	363006

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147218834	1			T1	198088		T3	335368		T4	242578
hw_debug_en_valid_off	111868996	1			T1	198088		T3	335368		T4	149748
hw_debug_en_on	23424334	1			T4	78430		T20	223196		T21	379350

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113784504	1			T1	198088		T3	335368		T4	142180
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99708001	1			T1	198088		T3	335368		T4	142180
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9477480	1			T20	172774		T22	325004		T61	20042
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4535776	1			T20	30750		T21	36684		T22	16014
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1752092	1			T61	39826		T135	17768		T138	13776
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1889272	1			T20	30750		T42	4784		T135	39978
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4401556	1			T4	78430		T21	23352		T22	68148
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1676842	1			T4	37620		T22	1424		T61	117280
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1977230	1			T4	40810		T22	66724		T135	94364
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9199748	1			T20	88134		T21	40564		T22	209178
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3628510	1			T22	69244		T42	15976		T61	10780
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3896544	1			T20	88134		T22	120392		T135	80744

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9981188	1			T4	7568		T20	363650		T22	175208
lc_exec_en	9823030	1			T20	135062		T21	315434		T22	126822
valid_exec_dis	107347006	1			T1	198088		T3	335368		T4	156580
invalid_exec_dis	33434330	1			T4	100398		T20	435288		T21	519148