Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43866081	1			T1	89982		T3	30500		T4	54504
triple_byte_access	2488806	1			T1	1806		T3	27423		T4	527
halfword_access	3734806	1			T1	2762		T3	41322		T4	829
byte_access	4990854	1			T1	3611		T3	54782		T4	1083
zero_access	1256465	1			T1	883		T3	13657		T4	271

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28114329

1

T1

49738

T3

84056

T4

28303

auto[1]

28222683

1

T1

49306

T3

83628

T4

28911

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21885166	1			T1	45278		T3	15203		T4	26939
auto[0]	triple_byte_access	1241555	1			T1	883		T3	13611		T4	266
auto[0]	halfword_access	1863460	1			T1	1344		T3	20841		T4	420
auto[0]	byte_access	2492909	1			T1	1806		T3	27514		T4	532
auto[0]	zero_access	631239	1			T1	427		T3	6887		T4	146
auto[1]	word_access	21980915	1			T1	44704		T3	15297		T4	27565
auto[1]	triple_byte_access	1247251	1			T1	923		T3	13812		T4	261
auto[1]	halfword_access	1871346	1			T1	1418		T3	20481		T4	409
auto[1]	byte_access	2497945	1			T1	1805		T3	27268		T4	551
auto[1]	zero_access	625226	1			T1	456		T3	6770		T4	125