Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147602608	1			T1	6142		T2	9768		T3	357738
instr_valid_dis	113003744	1			T1	6142		T2	9768		T3	352556
instr_en	23972105	1			T3	5182		T13	449054		T26	222426

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11382603	1			T3	72924		T13	65400		T26	195634
sram_ifetch_valid_disable	111289726	1			T1	6142		T2	9768		T3	147670
sram_ifetch_enable	24930279	1			T3	137144		T13	191732		T26	131276

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147602608	1			T1	6142		T2	9768		T3	357738
hw_debug_en_valid_off	111794655	1			T1	6142		T2	9768		T3	183614
hw_debug_en_on	25016941	1			T3	77280		T13	196858		T26	82758

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111289726	1			T1	6142		T2	9768		T3	147670
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97849315	1			T1	6142		T2	9768		T3	147590
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9002536	1			T3	80		T13	191922		T26	53520
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4503188	1			T3	27288		T13	65400		T26	49518
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1798832	1			T3	27288		T26	28514		T66	2488
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2083722	1			T13	65400		T5	15016		T7	43398
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4590548	1			T3	40534		T26	19670		T5	1218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1901972	1			T3	40534		T26	19670		T5	1218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1558012	1			T24	1996		T7	18848		T163	3456
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9310149	1			T3	17520		T13	71798		T26	12934
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4160162	1			T3	17440		T26	12934		T5	52364
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3529781	1			T3	80		T13	71798		T5	17930

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10095961	1			T13	191732		T26	81058		T5	39732
lc_exec_en	11116244	1			T3	19226		T13	125060		T26	50154
valid_exec_dis	108296938	1			T1	6142		T2	9768		T3	219436
invalid_exec_dis	36312882	1			T3	210068		T13	257132		T26	326910