Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43630044	1			T1	3071		T2	4046		T3	65136
triple_byte_access	2524810	1			T2	155		T3	1308		T8	32
halfword_access	3792806	1			T2	255		T3	1958		T8	48
byte_access	5061163	1			T2	337		T3	2625		T8	76
zero_access	1273370	1			T2	91		T3	678		T8	20

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28080130

1

T1

1024

T2

2405

T3

35574

auto[1]

28202063

1

T1

2047

T2

2479

T3

36131

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21759032	1			T1	1024		T2	1985		T3	32340
auto[0]	triple_byte_access	1258457	1			T2	76		T3	639		T8	18
auto[0]	halfword_access	1893868	1			T2	124		T3	968		T8	30
auto[0]	byte_access	2528121	1			T2	171		T3	1296		T8	40
auto[0]	zero_access	640652	1			T2	49		T3	331		T8	11
auto[1]	word_access	21871012	1			T1	2047		T2	2061		T3	32796
auto[1]	triple_byte_access	1266353	1			T2	79		T3	669		T8	14
auto[1]	halfword_access	1898938	1			T2	131		T3	990		T8	18
auto[1]	byte_access	2533042	1			T2	166		T3	1329		T8	36
auto[1]	zero_access	632718	1			T2	42		T3	347		T8	9