Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	150328492	1			T1	316866		T2	296426		T3	2634
instr_valid_dis	122001400	1			T2	296426		T3	2634		T7	87732
instr_en	22253091	1			T1	316866		T10	269252		T19	105080

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10575123	1			T1	81156		T10	157276		T19	69420
sram_ifetch_valid_disable	117543305	1			T1	73090		T2	296426		T3	2634
sram_ifetch_enable	22210064	1			T1	162620		T10	138468		T19	235094

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	150328492	1			T1	316866		T2	296426		T3	2634
hw_debug_en_valid_off	116360986	1			T1	105642		T2	296426		T3	2634
hw_debug_en_on	22976268	1			T1	78654		T10	205488		T19	324490

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117543305	1			T1	73090		T2	296426		T3	2634
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	105895114	1			T2	296426		T3	2634		T7	87732
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9016438	1			T1	73090		T10	142950		T19	35122
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4386328	1			T1	31076		T10	51662		T19	20102
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2087018	1			T10	51662		T19	20000		T6	14978
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1809134	1			T1	31076		T19	102		T6	40000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4249831	1			T1	50080		T10	88990		T6	83780
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1888481	1			T6	78136		T72	20622		T21	9416
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1849044	1			T1	50080		T10	88990		T6	1874
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9826878	1			T1	22616		T10	45642		T19	206314
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4544520	1			T10	20000		T19	192098		T6	42274
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4211792	1			T1	22616		T10	25642		T6	12920

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8795075	1			T1	162620		T10	37312		T19	34056
lc_exec_en	8899559	1			T1	5958		T10	70856		T19	118176
valid_exec_dis	114206742	1			T2	296426		T3	2634		T7	87732
invalid_exec_dis	32785187	1			T1	243776		T10	295744		T19	304514