Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.98 99.16 94.27 99.72 100.00 95.95 99.12 97.62


Total tests in report: 1030
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.21 68.21 91.10 91.10 67.30 67.30 75.76 75.76 23.81 23.81 80.19 80.19 93.22 93.22 46.07 46.07 /workspace/coverage/default/24.sram_ctrl_executable.4154373
82.43 14.22 95.59 4.49 80.92 13.63 78.57 2.81 61.90 38.10 87.92 7.73 95.28 2.06 76.78 30.71 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1392600837
87.27 4.85 97.03 1.44 86.02 5.09 87.90 9.33 71.43 9.52 90.82 2.90 95.43 0.15 82.27 5.48 /workspace/coverage/default/18.sram_ctrl_stress_all.1038846716
91.92 4.65 98.56 1.53 86.02 0.00 87.93 0.03 100.00 28.57 93.24 2.42 95.43 0.00 82.27 0.00 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2868662401
93.81 1.89 98.64 0.08 87.09 1.07 94.38 6.45 100.00 0.00 93.72 0.48 96.17 0.74 86.65 4.39 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2077212326
94.79 0.98 98.81 0.17 87.91 0.83 94.59 0.21 100.00 0.00 94.44 0.72 96.17 0.00 91.59 4.94 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1322284118
95.39 0.60 98.81 0.00 88.03 0.12 97.40 2.81 100.00 0.00 94.44 0.00 97.05 0.88 91.96 0.37 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.860264995
95.96 0.58 98.98 0.17 89.81 1.78 97.82 0.42 100.00 0.00 95.17 0.72 97.64 0.59 92.32 0.37 /workspace/coverage/default/0.sram_ctrl_sec_cm.507957586
96.38 0.42 98.98 0.00 90.17 0.36 97.82 0.00 100.00 0.00 95.41 0.24 97.79 0.15 94.52 2.19 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3630494770
96.59 0.20 98.98 0.00 90.52 0.36 98.34 0.52 100.00 0.00 95.41 0.00 97.79 0.00 95.06 0.55 /workspace/coverage/default/30.sram_ctrl_alert_test.105825033
96.79 0.20 98.98 0.00 90.52 0.00 98.40 0.07 100.00 0.00 95.41 0.00 99.12 1.33 95.06 0.00 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1382401906
96.94 0.15 98.98 0.00 90.76 0.24 98.86 0.45 100.00 0.00 95.41 0.00 99.12 0.00 95.43 0.37 /workspace/coverage/default/48.sram_ctrl_stress_all.2544439226
97.07 0.14 99.07 0.08 90.76 0.00 99.72 0.87 100.00 0.00 95.41 0.00 99.12 0.00 95.43 0.00 /workspace/coverage/default/47.sram_ctrl_ram_cfg.2392510280
97.20 0.13 99.07 0.00 90.76 0.00 99.72 0.00 100.00 0.00 95.41 0.00 99.12 0.00 96.34 0.91 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3750418872
97.29 0.09 99.07 0.00 90.88 0.12 99.72 0.00 100.00 0.00 95.89 0.48 99.12 0.00 96.34 0.00 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4056816605
97.35 0.06 99.15 0.08 91.00 0.12 99.72 0.00 100.00 0.00 96.14 0.24 99.12 0.00 96.34 0.00 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3617785041
97.40 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.71 0.37 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2950073051
97.46 0.05 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.07 0.37 /workspace/coverage/default/28.sram_ctrl_stress_all.1565683462
97.48 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2396864344
97.51 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3822960809
97.53 0.03 99.15 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.62 0.18 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1707820827

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3500808401
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.428879522
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3425661198
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3546625443
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2964505581
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1087193111
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3866114591
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3352443173
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.14859189
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3949978592
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1280493506
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2861659181
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3601262505
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3581224743
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.98335631
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3952531145
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3688321723
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1054210567
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3081619109
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3836746028
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.488765326
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.599037770
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1857020958
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3426514220
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1276840927
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3400910329
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3539468506
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4121369197
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1223297895
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1839205795
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3215606544
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1651584094
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.484528971
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2177899316
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4067619445
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.753010000
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.928981708
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3863032747
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.406524333
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4068888381
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4081868374
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4197628141
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3155720691
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2234561305
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1848012989
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2918851500
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2185976319
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3195553650
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.590637057
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.6072683
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.248256551
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3820713142
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2506201457
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.909632663
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4153896482
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2117924626
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2960436792
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1525172055
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4110744568
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2192855696
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2578328473
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.308175213
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3728813543
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1508733420
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3409231114
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2996761117
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3215506192
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.706314006
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3731799406
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1600489286
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3387301689
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2480419724
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3965449003
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.104952734
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3536865754
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1928271083
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3805597574
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1295212530
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2822285540
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.169888500
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1820451248
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3843971941
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1761528085
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3046483036
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.662137392
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3798774885
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2426751481
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2958209961
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3735196192
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2395753556
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.379191106
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3544011656
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2698215522
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2772696910
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3835578382
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3567432445
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1894962396
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3732493454
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3073392968
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3494759659
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3000355951
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4190339351
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.702601590
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2426641775
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1655194251
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.35368160
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3254266472
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.877692528
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.690568402
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2349674665
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3081326895
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3595275769
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2301383681
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.659383619
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2595082830
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.452680330
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2394140261
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2334545790
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4152104813
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2810218157
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2576353255
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2257926082
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3319360950
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3249286373
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1621109767
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1442501770
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.845328235
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1982773837
/workspace/coverage/default/0.sram_ctrl_alert_test.694266576
/workspace/coverage/default/0.sram_ctrl_bijection.3060342258
/workspace/coverage/default/0.sram_ctrl_executable.1615585294
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2978892938
/workspace/coverage/default/0.sram_ctrl_max_throughput.2303499088
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2785245270
/workspace/coverage/default/0.sram_ctrl_mem_walk.1552099468
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3085188582
/workspace/coverage/default/0.sram_ctrl_partial_access.3353321041
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2180949789
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3834693750
/workspace/coverage/default/0.sram_ctrl_regwen.373672739
/workspace/coverage/default/0.sram_ctrl_smoke.399795503
/workspace/coverage/default/0.sram_ctrl_stress_all.1616030479
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.31487660
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4062179191
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1853575785
/workspace/coverage/default/1.sram_ctrl_alert_test.3487572215
/workspace/coverage/default/1.sram_ctrl_bijection.3641820542
/workspace/coverage/default/1.sram_ctrl_executable.375164003
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1363026281
/workspace/coverage/default/1.sram_ctrl_max_throughput.2096292456
/workspace/coverage/default/1.sram_ctrl_mem_walk.167239194
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3385246361
/workspace/coverage/default/1.sram_ctrl_partial_access.3412222042
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2340923855
/workspace/coverage/default/1.sram_ctrl_ram_cfg.242401645
/workspace/coverage/default/1.sram_ctrl_regwen.2585233061
/workspace/coverage/default/1.sram_ctrl_sec_cm.3917654411
/workspace/coverage/default/1.sram_ctrl_smoke.3149443664
/workspace/coverage/default/1.sram_ctrl_stress_all.1663379849
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3608246952
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.739543919
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.958314619
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1250492954
/workspace/coverage/default/10.sram_ctrl_alert_test.2028045513
/workspace/coverage/default/10.sram_ctrl_bijection.967989110
/workspace/coverage/default/10.sram_ctrl_executable.1316505210
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3803578598
/workspace/coverage/default/10.sram_ctrl_max_throughput.2221468744
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2343854134
/workspace/coverage/default/10.sram_ctrl_mem_walk.1682466303
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2295657765
/workspace/coverage/default/10.sram_ctrl_partial_access.355587163
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1671147065
/workspace/coverage/default/10.sram_ctrl_ram_cfg.241661006
/workspace/coverage/default/10.sram_ctrl_regwen.2744385781
/workspace/coverage/default/10.sram_ctrl_smoke.2812119166
/workspace/coverage/default/10.sram_ctrl_stress_all.495028750
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.904657030
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3043623949
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2121494310
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.383766744
/workspace/coverage/default/11.sram_ctrl_alert_test.3392171580
/workspace/coverage/default/11.sram_ctrl_bijection.175287926
/workspace/coverage/default/11.sram_ctrl_executable.4097385250
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1873308783
/workspace/coverage/default/11.sram_ctrl_max_throughput.2578449304
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3715739438
/workspace/coverage/default/11.sram_ctrl_mem_walk.1856179547
/workspace/coverage/default/11.sram_ctrl_multiple_keys.661425390
/workspace/coverage/default/11.sram_ctrl_partial_access.1896413589
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1398012170
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2813063105
/workspace/coverage/default/11.sram_ctrl_regwen.1937087036
/workspace/coverage/default/11.sram_ctrl_smoke.2564843371
/workspace/coverage/default/11.sram_ctrl_stress_all.4278260610
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1349845215
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.686846371
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3463504560
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3264864082
/workspace/coverage/default/12.sram_ctrl_alert_test.3063414343
/workspace/coverage/default/12.sram_ctrl_bijection.1289703789
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/workspace/coverage/default/43.sram_ctrl_alert_test.591280881
/workspace/coverage/default/43.sram_ctrl_bijection.134793046
/workspace/coverage/default/43.sram_ctrl_executable.1652355837
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2935621655
/workspace/coverage/default/43.sram_ctrl_max_throughput.2164206625
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1553099015
/workspace/coverage/default/43.sram_ctrl_mem_walk.1398281385
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3972350444
/workspace/coverage/default/43.sram_ctrl_partial_access.3036853027
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3896266730
/workspace/coverage/default/43.sram_ctrl_ram_cfg.9945249
/workspace/coverage/default/43.sram_ctrl_regwen.1925815609
/workspace/coverage/default/43.sram_ctrl_smoke.37385545
/workspace/coverage/default/43.sram_ctrl_stress_all.1798292206
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2051918436
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2797551605
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.565711427
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3289876404
/workspace/coverage/default/44.sram_ctrl_alert_test.2478122116
/workspace/coverage/default/44.sram_ctrl_bijection.424966330
/workspace/coverage/default/44.sram_ctrl_executable.2142879
/workspace/coverage/default/44.sram_ctrl_lc_escalation.4260891582
/workspace/coverage/default/44.sram_ctrl_max_throughput.2400631762
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2869556205
/workspace/coverage/default/44.sram_ctrl_mem_walk.1968779941
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2790966593
/workspace/coverage/default/44.sram_ctrl_partial_access.2747994856
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2263615190
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3027769677
/workspace/coverage/default/44.sram_ctrl_regwen.3439102986
/workspace/coverage/default/44.sram_ctrl_smoke.3961042341
/workspace/coverage/default/44.sram_ctrl_stress_all.2531107289
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2978442916
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3821404903
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4165954282
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.302452983
/workspace/coverage/default/45.sram_ctrl_alert_test.1032574983
/workspace/coverage/default/45.sram_ctrl_bijection.385538710
/workspace/coverage/default/45.sram_ctrl_executable.3494187070
/workspace/coverage/default/45.sram_ctrl_lc_escalation.4205583260
/workspace/coverage/default/45.sram_ctrl_max_throughput.3361898650
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2306091292
/workspace/coverage/default/45.sram_ctrl_mem_walk.303589943
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1935834639
/workspace/coverage/default/45.sram_ctrl_partial_access.1400043288
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3225161871
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2238017913
/workspace/coverage/default/45.sram_ctrl_regwen.2603676591
/workspace/coverage/default/45.sram_ctrl_smoke.1283685307
/workspace/coverage/default/45.sram_ctrl_stress_all.1784718433
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4085448714
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4101484816
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1439526105
/workspace/coverage/default/46.sram_ctrl_alert_test.2643282949
/workspace/coverage/default/46.sram_ctrl_bijection.528978761
/workspace/coverage/default/46.sram_ctrl_executable.1616623190
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1248937807
/workspace/coverage/default/46.sram_ctrl_max_throughput.2070778852
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2506989558
/workspace/coverage/default/46.sram_ctrl_mem_walk.1095869239
/workspace/coverage/default/46.sram_ctrl_multiple_keys.958724717
/workspace/coverage/default/46.sram_ctrl_partial_access.565813605
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2742720284
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2189663064
/workspace/coverage/default/46.sram_ctrl_regwen.586754592
/workspace/coverage/default/46.sram_ctrl_smoke.3882352747
/workspace/coverage/default/46.sram_ctrl_stress_all.1935416768
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1621678691
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3338615983
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3273389390
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2076192639
/workspace/coverage/default/47.sram_ctrl_alert_test.2428748535
/workspace/coverage/default/47.sram_ctrl_bijection.2359744044
/workspace/coverage/default/47.sram_ctrl_executable.1408246383
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1607885834
/workspace/coverage/default/47.sram_ctrl_max_throughput.713185053
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.840854038
/workspace/coverage/default/47.sram_ctrl_mem_walk.3321577889
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1492524345
/workspace/coverage/default/47.sram_ctrl_partial_access.1462179161
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3415992255
/workspace/coverage/default/47.sram_ctrl_regwen.1373153157
/workspace/coverage/default/47.sram_ctrl_smoke.458975676
/workspace/coverage/default/47.sram_ctrl_stress_all.3261031428
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1635961778
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3594890251
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1276586492
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2485563891
/workspace/coverage/default/48.sram_ctrl_alert_test.2430384046
/workspace/coverage/default/48.sram_ctrl_bijection.3731579709
/workspace/coverage/default/48.sram_ctrl_executable.2252058315
/workspace/coverage/default/48.sram_ctrl_lc_escalation.4184334935
/workspace/coverage/default/48.sram_ctrl_max_throughput.3788537536
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2196356797
/workspace/coverage/default/48.sram_ctrl_mem_walk.2869759967
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3409525973
/workspace/coverage/default/48.sram_ctrl_partial_access.1340340731
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2308223764
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1431680085
/workspace/coverage/default/48.sram_ctrl_regwen.3559555513
/workspace/coverage/default/48.sram_ctrl_smoke.1473340801
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1849163124
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1921344942
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2980993812
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.198626322
/workspace/coverage/default/49.sram_ctrl_alert_test.648300399
/workspace/coverage/default/49.sram_ctrl_bijection.153574890
/workspace/coverage/default/49.sram_ctrl_executable.4004300006
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3774227591
/workspace/coverage/default/49.sram_ctrl_max_throughput.1585535375
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2440020067
/workspace/coverage/default/49.sram_ctrl_mem_walk.3822389016
/workspace/coverage/default/49.sram_ctrl_multiple_keys.475020689
/workspace/coverage/default/49.sram_ctrl_partial_access.1581710681
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.207628772
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4058029018
/workspace/coverage/default/49.sram_ctrl_regwen.765341530
/workspace/coverage/default/49.sram_ctrl_smoke.3977876953
/workspace/coverage/default/49.sram_ctrl_stress_all.972566536
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2898267885
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1774720197
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3244359997
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3981054471
/workspace/coverage/default/5.sram_ctrl_alert_test.479673895
/workspace/coverage/default/5.sram_ctrl_bijection.2600455119
/workspace/coverage/default/5.sram_ctrl_executable.4031807932
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1625231284
/workspace/coverage/default/5.sram_ctrl_max_throughput.149163517
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2457607237
/workspace/coverage/default/5.sram_ctrl_mem_walk.3763012266
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1603032028
/workspace/coverage/default/5.sram_ctrl_partial_access.160935456
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3953847191
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3374852109
/workspace/coverage/default/5.sram_ctrl_regwen.2509503248
/workspace/coverage/default/5.sram_ctrl_smoke.3406264919
/workspace/coverage/default/5.sram_ctrl_stress_all.2889030457
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.286373380
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3962630317
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1349551502
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1181999490
/workspace/coverage/default/6.sram_ctrl_alert_test.3498045978
/workspace/coverage/default/6.sram_ctrl_bijection.3800392001
/workspace/coverage/default/6.sram_ctrl_executable.3835710821
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1224489756
/workspace/coverage/default/6.sram_ctrl_max_throughput.1639260446
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3622835667
/workspace/coverage/default/6.sram_ctrl_mem_walk.3874043415
/workspace/coverage/default/6.sram_ctrl_multiple_keys.865039827
/workspace/coverage/default/6.sram_ctrl_partial_access.2650797271
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3366668112
/workspace/coverage/default/6.sram_ctrl_ram_cfg.4147199459
/workspace/coverage/default/6.sram_ctrl_regwen.1223739555
/workspace/coverage/default/6.sram_ctrl_smoke.84498097
/workspace/coverage/default/6.sram_ctrl_stress_all.761591689
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2038323113
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3743697464
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.908091640
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4033845366
/workspace/coverage/default/7.sram_ctrl_alert_test.3659985805
/workspace/coverage/default/7.sram_ctrl_bijection.3349236550
/workspace/coverage/default/7.sram_ctrl_executable.1185757921
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3805853549
/workspace/coverage/default/7.sram_ctrl_max_throughput.3162898191
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3475127296
/workspace/coverage/default/7.sram_ctrl_mem_walk.2008467022
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3951737052
/workspace/coverage/default/7.sram_ctrl_partial_access.3593518880
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.918981175
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2809331408
/workspace/coverage/default/7.sram_ctrl_regwen.1637687792
/workspace/coverage/default/7.sram_ctrl_smoke.187045671
/workspace/coverage/default/7.sram_ctrl_stress_all.3633182491
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4075577073
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3088734764
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3602122894
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1640633595
/workspace/coverage/default/8.sram_ctrl_alert_test.1571824055
/workspace/coverage/default/8.sram_ctrl_bijection.2746313065
/workspace/coverage/default/8.sram_ctrl_executable.3584156760
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4039304542
/workspace/coverage/default/8.sram_ctrl_max_throughput.4247406663
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.62367502
/workspace/coverage/default/8.sram_ctrl_mem_walk.2568250933
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2584496962
/workspace/coverage/default/8.sram_ctrl_partial_access.374140845
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3229549768
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2580839965
/workspace/coverage/default/8.sram_ctrl_regwen.2450596004
/workspace/coverage/default/8.sram_ctrl_smoke.2663676359
/workspace/coverage/default/8.sram_ctrl_stress_all.1613989455
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.998224049
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1938291864
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2231785869
/workspace/coverage/default/9.sram_ctrl_alert_test.468588111
/workspace/coverage/default/9.sram_ctrl_bijection.3156074834
/workspace/coverage/default/9.sram_ctrl_executable.1326766488
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2099131466
/workspace/coverage/default/9.sram_ctrl_max_throughput.1858321724
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2165786562
/workspace/coverage/default/9.sram_ctrl_mem_walk.3386204108
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3402871516
/workspace/coverage/default/9.sram_ctrl_partial_access.2066997928
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2292012053
/workspace/coverage/default/9.sram_ctrl_ram_cfg.811183838
/workspace/coverage/default/9.sram_ctrl_regwen.1974599472
/workspace/coverage/default/9.sram_ctrl_smoke.649855795
/workspace/coverage/default/9.sram_ctrl_stress_all.672719536
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3900424352
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3272188445
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3457892927



Total test records in report: 1030
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.sram_ctrl_regwen.2509503248 Jul 16 07:41:20 PM PDT 24 Jul 16 07:59:27 PM PDT 24 18330503071 ps
T2 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1898176444 Jul 16 07:43:07 PM PDT 24 Jul 16 07:46:14 PM PDT 24 25612855062 ps
T3 /workspace/coverage/default/21.sram_ctrl_partial_access.2825380855 Jul 16 07:42:23 PM PDT 24 Jul 16 07:42:35 PM PDT 24 131365563 ps
T7 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3796001544 Jul 16 07:43:36 PM PDT 24 Jul 16 07:46:53 PM PDT 24 3618293499 ps
T8 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.860264995 Jul 16 07:42:23 PM PDT 24 Jul 16 08:02:49 PM PDT 24 16227537318 ps
T9 /workspace/coverage/default/4.sram_ctrl_bijection.3475517487 Jul 16 07:41:19 PM PDT 24 Jul 16 07:42:51 PM PDT 24 34219782278 ps
T10 /workspace/coverage/default/24.sram_ctrl_executable.4154373 Jul 16 07:42:41 PM PDT 24 Jul 16 07:59:36 PM PDT 24 17097568897 ps
T11 /workspace/coverage/default/47.sram_ctrl_ram_cfg.2392510280 Jul 16 07:45:36 PM PDT 24 Jul 16 07:45:39 PM PDT 24 46436736 ps
T4 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3774227591 Jul 16 07:46:18 PM PDT 24 Jul 16 07:46:21 PM PDT 24 60615077 ps
T12 /workspace/coverage/default/48.sram_ctrl_alert_test.2430384046 Jul 16 07:46:19 PM PDT 24 Jul 16 07:46:21 PM PDT 24 17863149 ps
T40 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1980591881 Jul 16 07:42:28 PM PDT 24 Jul 16 07:45:42 PM PDT 24 2599023806 ps
T41 /workspace/coverage/default/7.sram_ctrl_smoke.187045671 Jul 16 07:41:24 PM PDT 24 Jul 16 07:41:47 PM PDT 24 55342870 ps
T5 /workspace/coverage/default/0.sram_ctrl_lc_escalation.2978892938 Jul 16 07:41:11 PM PDT 24 Jul 16 07:41:29 PM PDT 24 692701279 ps
T119 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2980993812 Jul 16 07:46:17 PM PDT 24 Jul 16 07:48:52 PM PDT 24 161457911 ps
T19 /workspace/coverage/default/43.sram_ctrl_stress_all.1798292206 Jul 16 07:44:56 PM PDT 24 Jul 16 08:24:09 PM PDT 24 52546056318 ps
T42 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3630494770 Jul 16 07:42:19 PM PDT 24 Jul 16 07:46:39 PM PDT 24 121948785249 ps
T73 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2121494310 Jul 16 07:41:28 PM PDT 24 Jul 16 07:41:59 PM PDT 24 535576251 ps
T6 /workspace/coverage/default/18.sram_ctrl_stress_all.1038846716 Jul 16 07:42:20 PM PDT 24 Jul 16 08:57:56 PM PDT 24 21595239881 ps
T90 /workspace/coverage/default/48.sram_ctrl_executable.2252058315 Jul 16 07:46:20 PM PDT 24 Jul 16 08:06:41 PM PDT 24 65363661103 ps
T72 /workspace/coverage/default/28.sram_ctrl_stress_all.1565683462 Jul 16 07:43:04 PM PDT 24 Jul 16 09:23:37 PM PDT 24 14956513992 ps
T115 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2263615190 Jul 16 07:45:00 PM PDT 24 Jul 16 07:47:51 PM PDT 24 36313372435 ps
T139 /workspace/coverage/default/10.sram_ctrl_bijection.967989110 Jul 16 07:41:25 PM PDT 24 Jul 16 07:42:41 PM PDT 24 897345920 ps
T137 /workspace/coverage/default/28.sram_ctrl_executable.2472344610 Jul 16 07:43:04 PM PDT 24 Jul 16 07:49:48 PM PDT 24 24035048198 ps
T44 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.3290719948 Jul 16 07:42:51 PM PDT 24 Jul 16 07:42:58 PM PDT 24 274136666 ps
T60 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.739543919 Jul 16 07:41:10 PM PDT 24 Jul 16 07:46:07 PM PDT 24 3056205921 ps
T25 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2077212326 Jul 16 07:41:07 PM PDT 24 Jul 16 07:41:26 PM PDT 24 930984715 ps
T61 /workspace/coverage/default/25.sram_ctrl_partial_access.3185568889 Jul 16 07:42:54 PM PDT 24 Jul 16 07:43:17 PM PDT 24 2540018317 ps
T45 /workspace/coverage/default/14.sram_ctrl_mem_walk.855885581 Jul 16 07:41:57 PM PDT 24 Jul 16 07:42:19 PM PDT 24 2592111555 ps
T27 /workspace/coverage/default/36.sram_ctrl_ram_cfg.957289280 Jul 16 07:43:51 PM PDT 24 Jul 16 07:43:53 PM PDT 24 50534461 ps
T62 /workspace/coverage/default/46.sram_ctrl_executable.1616623190 Jul 16 07:45:33 PM PDT 24 Jul 16 08:02:53 PM PDT 24 17019434720 ps
T63 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.565711427 Jul 16 07:44:58 PM PDT 24 Jul 16 07:45:35 PM PDT 24 121341316 ps
T64 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1533163204 Jul 16 07:42:02 PM PDT 24 Jul 16 07:44:11 PM PDT 24 311943096 ps
T65 /workspace/coverage/default/10.sram_ctrl_smoke.2812119166 Jul 16 07:41:28 PM PDT 24 Jul 16 07:41:53 PM PDT 24 167212717 ps
T46 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3740874113 Jul 16 07:42:50 PM PDT 24 Jul 16 07:42:56 PM PDT 24 342277559 ps
T78 /workspace/coverage/default/42.sram_ctrl_stress_all.2990890431 Jul 16 07:44:40 PM PDT 24 Jul 16 08:05:04 PM PDT 24 125259080501 ps
T28 /workspace/coverage/default/16.sram_ctrl_ram_cfg.658693074 Jul 16 07:42:07 PM PDT 24 Jul 16 07:42:15 PM PDT 24 44160648 ps
T21 /workspace/coverage/default/20.sram_ctrl_regwen.2782199339 Jul 16 07:42:27 PM PDT 24 Jul 16 07:49:54 PM PDT 24 45492397920 ps
T140 /workspace/coverage/default/7.sram_ctrl_max_throughput.3162898191 Jul 16 07:41:28 PM PDT 24 Jul 16 07:42:24 PM PDT 24 198650909 ps
T141 /workspace/coverage/default/6.sram_ctrl_ram_cfg.4147199459 Jul 16 07:41:24 PM PDT 24 Jul 16 07:41:46 PM PDT 24 25540773 ps
T142 /workspace/coverage/default/16.sram_ctrl_multiple_keys.1707820827 Jul 16 07:42:06 PM PDT 24 Jul 16 08:00:26 PM PDT 24 45730086362 ps
T96 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3475127296 Jul 16 07:41:25 PM PDT 24 Jul 16 07:41:49 PM PDT 24 322808263 ps
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T143 /workspace/coverage/default/18.sram_ctrl_max_throughput.835754664 Jul 16 07:42:22 PM PDT 24 Jul 16 07:44:08 PM PDT 24 265443152 ps
T22 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1392600837 Jul 16 07:44:40 PM PDT 24 Jul 16 07:55:19 PM PDT 24 10271573562 ps
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T20 /workspace/coverage/default/46.sram_ctrl_stress_all.1935416768 Jul 16 07:45:34 PM PDT 24 Jul 16 08:57:05 PM PDT 24 49610305883 ps
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T97 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1023267244 Jul 16 07:41:57 PM PDT 24 Jul 16 07:42:10 PM PDT 24 44775432 ps
T52 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3617785041 Jul 16 07:41:07 PM PDT 24 Jul 16 07:41:23 PM PDT 24 1993034321 ps
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T145 /workspace/coverage/default/2.sram_ctrl_executable.4197104 Jul 16 07:41:06 PM PDT 24 Jul 16 07:53:29 PM PDT 24 11384215450 ps
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T53 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3508756050 Jul 16 07:44:40 PM PDT 24 Jul 16 07:44:48 PM PDT 24 1418730744 ps
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T26 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.904657030 Jul 16 07:41:51 PM PDT 24 Jul 16 07:43:50 PM PDT 24 4557411878 ps
T57 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3900424352 Jul 16 07:41:22 PM PDT 24 Jul 16 07:43:36 PM PDT 24 5897153719 ps
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T150 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2939626761 Jul 16 07:41:11 PM PDT 24 Jul 16 08:04:06 PM PDT 24 3297002651 ps
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T23 /workspace/coverage/default/48.sram_ctrl_stress_all.2544439226 Jul 16 07:46:11 PM PDT 24 Jul 16 08:19:29 PM PDT 24 33713832265 ps
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T154 /workspace/coverage/default/43.sram_ctrl_partial_access.3036853027 Jul 16 07:44:41 PM PDT 24 Jul 16 07:44:58 PM PDT 24 420065336 ps
T155 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4035332387 Jul 16 07:43:54 PM PDT 24 Jul 16 07:45:03 PM PDT 24 134223830 ps
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T157 /workspace/coverage/default/16.sram_ctrl_partial_access.3164328349 Jul 16 07:42:04 PM PDT 24 Jul 16 07:43:33 PM PDT 24 218609079 ps
T158 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1530265137 Jul 16 07:43:35 PM PDT 24 Jul 16 07:44:20 PM PDT 24 213729785 ps
T159 /workspace/coverage/default/37.sram_ctrl_executable.3545678062 Jul 16 07:43:54 PM PDT 24 Jul 16 08:01:59 PM PDT 24 66659577053 ps
T58 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.323396066 Jul 16 07:43:22 PM PDT 24 Jul 16 07:43:29 PM PDT 24 388624272 ps
T160 /workspace/coverage/default/25.sram_ctrl_multiple_keys.3740518969 Jul 16 07:42:53 PM PDT 24 Jul 16 07:53:50 PM PDT 24 31105976542 ps
T14 /workspace/coverage/default/30.sram_ctrl_alert_test.105825033 Jul 16 07:43:19 PM PDT 24 Jul 16 07:43:22 PM PDT 24 31105960 ps
T161 /workspace/coverage/default/44.sram_ctrl_max_throughput.2400631762 Jul 16 07:44:57 PM PDT 24 Jul 16 07:45:28 PM PDT 24 90270364 ps
T162 /workspace/coverage/default/30.sram_ctrl_smoke.657737810 Jul 16 07:43:04 PM PDT 24 Jul 16 07:44:38 PM PDT 24 127940550 ps
T116 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3594890251 Jul 16 07:45:33 PM PDT 24 Jul 16 07:49:47 PM PDT 24 2777873918 ps
T163 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1363026281 Jul 16 07:41:12 PM PDT 24 Jul 16 07:41:34 PM PDT 24 5313909916 ps
T98 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.4021932311 Jul 16 07:41:19 PM PDT 24 Jul 16 07:41:43 PM PDT 24 86308298 ps
T164 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3085188582 Jul 16 07:41:08 PM PDT 24 Jul 16 07:46:05 PM PDT 24 9076887361 ps
T43 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2293825005 Jul 16 07:43:58 PM PDT 24 Jul 16 08:01:04 PM PDT 24 20632958150 ps
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T59 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.413926085 Jul 16 07:42:23 PM PDT 24 Jul 16 07:51:17 PM PDT 24 2317519307 ps
T167 /workspace/coverage/default/13.sram_ctrl_mem_walk.3971817274 Jul 16 07:41:36 PM PDT 24 Jul 16 07:42:04 PM PDT 24 348081594 ps
T168 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.500876529 Jul 16 07:43:43 PM PDT 24 Jul 16 07:44:08 PM PDT 24 353087982 ps
T76 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3883319973 Jul 16 07:42:51 PM PDT 24 Jul 16 07:43:24 PM PDT 24 3469533868 ps
T66 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.840854038 Jul 16 07:45:34 PM PDT 24 Jul 16 07:45:41 PM PDT 24 197483826 ps
T169 /workspace/coverage/default/30.sram_ctrl_partial_access.4152814898 Jul 16 07:43:07 PM PDT 24 Jul 16 07:45:29 PM PDT 24 647815290 ps
T24 /workspace/coverage/default/22.sram_ctrl_lc_escalation.2567114369 Jul 16 07:42:20 PM PDT 24 Jul 16 07:42:37 PM PDT 24 3684718302 ps
T170 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1181999490 Jul 16 07:41:28 PM PDT 24 Jul 16 07:49:51 PM PDT 24 4360467011 ps
T171 /workspace/coverage/default/8.sram_ctrl_ram_cfg.2580839965 Jul 16 07:41:30 PM PDT 24 Jul 16 07:41:52 PM PDT 24 41554200 ps
T172 /workspace/coverage/default/12.sram_ctrl_ram_cfg.3969343282 Jul 16 07:41:55 PM PDT 24 Jul 16 07:42:06 PM PDT 24 84920540 ps
T173 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.31487660 Jul 16 07:41:05 PM PDT 24 Jul 16 07:44:58 PM PDT 24 10620401827 ps
T174 /workspace/coverage/default/32.sram_ctrl_stress_all.3401157999 Jul 16 07:43:37 PM PDT 24 Jul 16 08:19:48 PM PDT 24 37952465870 ps
T175 /workspace/coverage/default/33.sram_ctrl_multiple_keys.775653496 Jul 16 07:43:35 PM PDT 24 Jul 16 07:54:32 PM PDT 24 3844425681 ps
T67 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1562723665 Jul 16 07:41:57 PM PDT 24 Jul 16 07:42:49 PM PDT 24 537373197 ps
T176 /workspace/coverage/default/44.sram_ctrl_smoke.3961042341 Jul 16 07:44:57 PM PDT 24 Jul 16 07:45:11 PM PDT 24 515483391 ps
T177 /workspace/coverage/default/13.sram_ctrl_ram_cfg.932013598 Jul 16 07:41:52 PM PDT 24 Jul 16 07:42:05 PM PDT 24 30452332 ps
T178 /workspace/coverage/default/42.sram_ctrl_executable.1481275736 Jul 16 07:44:40 PM PDT 24 Jul 16 07:53:42 PM PDT 24 5911638042 ps
T125 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2366255141 Jul 16 07:41:56 PM PDT 24 Jul 16 07:42:15 PM PDT 24 2944367071 ps
T179 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.460035410 Jul 16 07:41:23 PM PDT 24 Jul 16 07:54:09 PM PDT 24 3167537491 ps
T180 /workspace/coverage/default/32.sram_ctrl_smoke.1105750252 Jul 16 07:43:22 PM PDT 24 Jul 16 07:43:35 PM PDT 24 1740237756 ps
T138 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2742720284 Jul 16 07:45:35 PM PDT 24 Jul 16 07:48:11 PM PDT 24 6392330540 ps
T181 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2098755263 Jul 16 07:42:21 PM PDT 24 Jul 16 07:42:34 PM PDT 24 63492798 ps
T182 /workspace/coverage/default/10.sram_ctrl_executable.1316505210 Jul 16 07:41:51 PM PDT 24 Jul 16 07:42:16 PM PDT 24 1088153404 ps
T183 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.4032605454 Jul 16 07:44:11 PM PDT 24 Jul 16 07:44:15 PM PDT 24 46547589 ps
T184 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2684180565 Jul 16 07:43:42 PM PDT 24 Jul 16 07:43:46 PM PDT 24 69671686 ps
T185 /workspace/coverage/default/48.sram_ctrl_partial_access.1340340731 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:27 PM PDT 24 408982382 ps
T186 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3893644578 Jul 16 07:43:56 PM PDT 24 Jul 16 07:48:24 PM PDT 24 5738885624 ps
T187 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1671147065 Jul 16 07:41:27 PM PDT 24 Jul 16 07:48:40 PM PDT 24 56925214815 ps
T188 /workspace/coverage/default/37.sram_ctrl_bijection.1365821378 Jul 16 07:43:52 PM PDT 24 Jul 16 07:44:18 PM PDT 24 2982876326 ps
T189 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.976726539 Jul 16 07:43:08 PM PDT 24 Jul 16 07:48:08 PM PDT 24 68393240853 ps
T190 /workspace/coverage/default/16.sram_ctrl_regwen.548161269 Jul 16 07:42:06 PM PDT 24 Jul 16 08:14:55 PM PDT 24 19232594069 ps
T191 /workspace/coverage/default/45.sram_ctrl_max_throughput.3361898650 Jul 16 07:45:01 PM PDT 24 Jul 16 07:45:10 PM PDT 24 95959073 ps
T68 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2966192771 Jul 16 07:41:58 PM PDT 24 Jul 16 07:46:02 PM PDT 24 7612209652 ps
T56 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3885489990 Jul 16 07:42:08 PM PDT 24 Jul 16 07:42:40 PM PDT 24 3061502640 ps
T192 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1611849185 Jul 16 07:41:19 PM PDT 24 Jul 16 07:42:44 PM PDT 24 505349456 ps
T193 /workspace/coverage/default/10.sram_ctrl_max_throughput.2221468744 Jul 16 07:41:27 PM PDT 24 Jul 16 07:43:52 PM PDT 24 145046950 ps
T194 /workspace/coverage/default/31.sram_ctrl_mem_walk.822451169 Jul 16 07:43:22 PM PDT 24 Jul 16 07:43:36 PM PDT 24 463504048 ps
T195 /workspace/coverage/default/11.sram_ctrl_regwen.1937087036 Jul 16 07:41:51 PM PDT 24 Jul 16 07:59:36 PM PDT 24 6896809456 ps
T196 /workspace/coverage/default/25.sram_ctrl_alert_test.1550023660 Jul 16 07:42:53 PM PDT 24 Jul 16 07:42:58 PM PDT 24 87869052 ps
T197 /workspace/coverage/default/17.sram_ctrl_bijection.2570416612 Jul 16 07:42:08 PM PDT 24 Jul 16 07:43:10 PM PDT 24 2531903304 ps
T77 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4087525186 Jul 16 07:41:21 PM PDT 24 Jul 16 07:53:20 PM PDT 24 5478499725 ps
T198 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3831006849 Jul 16 07:42:07 PM PDT 24 Jul 16 07:46:48 PM PDT 24 2779253146 ps
T136 /workspace/coverage/default/10.sram_ctrl_stress_all.495028750 Jul 16 07:41:52 PM PDT 24 Jul 16 08:49:32 PM PDT 24 15226263884 ps
T199 /workspace/coverage/default/26.sram_ctrl_executable.822421286 Jul 16 07:42:53 PM PDT 24 Jul 16 08:02:20 PM PDT 24 4089870331 ps
T200 /workspace/coverage/default/11.sram_ctrl_ram_cfg.2813063105 Jul 16 07:41:49 PM PDT 24 Jul 16 07:42:04 PM PDT 24 134444191 ps
T201 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2771139804 Jul 16 07:41:57 PM PDT 24 Jul 16 07:44:57 PM PDT 24 9032043783 ps
T120 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.644226279 Jul 16 07:44:13 PM PDT 24 Jul 16 07:44:25 PM PDT 24 318653838 ps
T202 /workspace/coverage/default/14.sram_ctrl_stress_all.259715289 Jul 16 07:41:56 PM PDT 24 Jul 16 08:03:36 PM PDT 24 189276210940 ps
T54 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2868662401 Jul 16 07:44:24 PM PDT 24 Jul 16 07:44:33 PM PDT 24 2263122812 ps
T203 /workspace/coverage/default/23.sram_ctrl_smoke.1204963154 Jul 16 07:42:42 PM PDT 24 Jul 16 07:43:08 PM PDT 24 593657495 ps
T204 /workspace/coverage/default/38.sram_ctrl_regwen.3430554017 Jul 16 07:44:11 PM PDT 24 Jul 16 08:04:12 PM PDT 24 23470520703 ps
T205 /workspace/coverage/default/43.sram_ctrl_executable.1652355837 Jul 16 07:44:56 PM PDT 24 Jul 16 08:03:50 PM PDT 24 6338579171 ps
T55 /workspace/coverage/default/0.sram_ctrl_mem_walk.1552099468 Jul 16 07:41:09 PM PDT 24 Jul 16 07:41:32 PM PDT 24 1471989802 ps
T206 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3077998314 Jul 16 07:42:36 PM PDT 24 Jul 16 07:47:29 PM PDT 24 2903221343 ps
T207 /workspace/coverage/default/46.sram_ctrl_max_throughput.2070778852 Jul 16 07:45:35 PM PDT 24 Jul 16 07:47:34 PM PDT 24 519456596 ps
T208 /workspace/coverage/default/9.sram_ctrl_smoke.649855795 Jul 16 07:41:30 PM PDT 24 Jul 16 07:42:46 PM PDT 24 557346943 ps
T209 /workspace/coverage/default/8.sram_ctrl_executable.3584156760 Jul 16 07:41:29 PM PDT 24 Jul 16 08:02:38 PM PDT 24 67777329697 ps
T210 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1794011255 Jul 16 07:41:14 PM PDT 24 Jul 16 07:46:17 PM PDT 24 3052477541 ps
T211 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2536957480 Jul 16 07:43:23 PM PDT 24 Jul 16 07:47:25 PM PDT 24 30450014002 ps
T121 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1349845215 Jul 16 07:41:51 PM PDT 24 Jul 16 07:44:23 PM PDT 24 6772231030 ps
T212 /workspace/coverage/default/13.sram_ctrl_executable.4151690692 Jul 16 07:41:52 PM PDT 24 Jul 16 07:50:14 PM PDT 24 10394495609 ps
T213 /workspace/coverage/default/41.sram_ctrl_max_throughput.1474327076 Jul 16 07:44:25 PM PDT 24 Jul 16 07:45:14 PM PDT 24 103138483 ps
T214 /workspace/coverage/default/34.sram_ctrl_partial_access.3334430249 Jul 16 07:43:37 PM PDT 24 Jul 16 07:43:55 PM PDT 24 248742712 ps
T215 /workspace/coverage/default/6.sram_ctrl_executable.3835710821 Jul 16 07:41:23 PM PDT 24 Jul 16 07:48:21 PM PDT 24 9137496919 ps
T216 /workspace/coverage/default/6.sram_ctrl_stress_all.761591689 Jul 16 07:41:29 PM PDT 24 Jul 16 08:02:17 PM PDT 24 76254733081 ps
T217 /workspace/coverage/default/24.sram_ctrl_ram_cfg.3518367180 Jul 16 07:42:39 PM PDT 24 Jul 16 07:42:45 PM PDT 24 72182200 ps
T218 /workspace/coverage/default/31.sram_ctrl_executable.3008717527 Jul 16 07:43:19 PM PDT 24 Jul 16 07:45:03 PM PDT 24 754509983 ps
T219 /workspace/coverage/default/17.sram_ctrl_partial_access.3029102241 Jul 16 07:42:07 PM PDT 24 Jul 16 07:42:16 PM PDT 24 39053338 ps
T220 /workspace/coverage/default/34.sram_ctrl_multiple_keys.4002276535 Jul 16 07:43:35 PM PDT 24 Jul 16 08:05:47 PM PDT 24 7690896117 ps
T221 /workspace/coverage/default/44.sram_ctrl_alert_test.2478122116 Jul 16 07:45:00 PM PDT 24 Jul 16 07:45:02 PM PDT 24 30875903 ps
T222 /workspace/coverage/default/48.sram_ctrl_bijection.3731579709 Jul 16 07:46:19 PM PDT 24 Jul 16 07:47:43 PM PDT 24 4462634487 ps
T223 /workspace/coverage/default/49.sram_ctrl_mem_walk.3822389016 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:32 PM PDT 24 104858485 ps
T224 /workspace/coverage/default/42.sram_ctrl_partial_access.278799504 Jul 16 07:44:38 PM PDT 24 Jul 16 07:44:52 PM PDT 24 270780049 ps
T225 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.790752779 Jul 16 07:41:22 PM PDT 24 Jul 16 07:46:03 PM PDT 24 5674794066 ps
T226 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.54028188 Jul 16 07:42:54 PM PDT 24 Jul 16 07:46:34 PM PDT 24 9686162856 ps
T227 /workspace/coverage/default/45.sram_ctrl_ram_cfg.2238017913 Jul 16 07:45:33 PM PDT 24 Jul 16 07:45:35 PM PDT 24 31298407 ps
T228 /workspace/coverage/default/15.sram_ctrl_regwen.4109130152 Jul 16 07:41:58 PM PDT 24 Jul 16 07:51:26 PM PDT 24 10005192553 ps
T229 /workspace/coverage/default/12.sram_ctrl_stress_all.1702247624 Jul 16 07:41:47 PM PDT 24 Jul 16 07:45:28 PM PDT 24 26874482733 ps
T230 /workspace/coverage/default/29.sram_ctrl_bijection.2572017304 Jul 16 07:43:06 PM PDT 24 Jul 16 07:43:40 PM PDT 24 1959889670 ps
T231 /workspace/coverage/default/47.sram_ctrl_lc_escalation.1607885834 Jul 16 07:45:34 PM PDT 24 Jul 16 07:45:39 PM PDT 24 325847572 ps
T122 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.582420215 Jul 16 07:42:08 PM PDT 24 Jul 16 07:42:22 PM PDT 24 1363557299 ps
T232 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2481957410 Jul 16 07:42:38 PM PDT 24 Jul 16 07:42:47 PM PDT 24 47941887 ps
T233 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3272188445 Jul 16 07:41:28 PM PDT 24 Jul 16 07:46:51 PM PDT 24 18883564910 ps
T234 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1174087994 Jul 16 07:44:16 PM PDT 24 Jul 16 08:01:19 PM PDT 24 4938871269 ps
T235 /workspace/coverage/default/12.sram_ctrl_mem_walk.595886017 Jul 16 07:41:54 PM PDT 24 Jul 16 07:42:11 PM PDT 24 240333673 ps
T236 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3415915846 Jul 16 07:42:41 PM PDT 24 Jul 16 07:46:30 PM PDT 24 15379504880 ps
T237 /workspace/coverage/default/5.sram_ctrl_stress_all.2889030457 Jul 16 07:41:21 PM PDT 24 Jul 16 08:19:39 PM PDT 24 50837282864 ps
T238 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2516956501 Jul 16 07:44:16 PM PDT 24 Jul 16 08:03:08 PM PDT 24 15701436887 ps
T239 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2195019027 Jul 16 07:41:08 PM PDT 24 Jul 16 07:47:00 PM PDT 24 57077007852 ps
T240 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2051918436 Jul 16 07:45:00 PM PDT 24 Jul 16 07:51:34 PM PDT 24 751299687 ps
T241 /workspace/coverage/default/42.sram_ctrl_multiple_keys.2614980087 Jul 16 07:44:38 PM PDT 24 Jul 16 08:00:28 PM PDT 24 46280364447 ps
T242 /workspace/coverage/default/3.sram_ctrl_bijection.727721314 Jul 16 07:41:06 PM PDT 24 Jul 16 07:42:12 PM PDT 24 3524979050 ps
T243 /workspace/coverage/default/11.sram_ctrl_stress_all.4278260610 Jul 16 07:41:47 PM PDT 24 Jul 16 08:28:13 PM PDT 24 11435194184 ps
T244 /workspace/coverage/default/0.sram_ctrl_executable.1615585294 Jul 16 07:41:12 PM PDT 24 Jul 16 07:53:31 PM PDT 24 30004328831 ps
T245 /workspace/coverage/default/31.sram_ctrl_lc_escalation.3654108939 Jul 16 07:43:20 PM PDT 24 Jul 16 07:43:35 PM PDT 24 3428993368 ps
T246 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.686846371 Jul 16 07:41:54 PM PDT 24 Jul 16 07:46:27 PM PDT 24 2597331458 ps
T247 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3743697464 Jul 16 07:41:27 PM PDT 24 Jul 16 07:46:48 PM PDT 24 12750476021 ps
T248 /workspace/coverage/default/3.sram_ctrl_stress_all.3303105476 Jul 16 07:41:21 PM PDT 24 Jul 16 08:11:51 PM PDT 24 160419959186 ps
T249 /workspace/coverage/default/18.sram_ctrl_lc_escalation.934435280 Jul 16 07:42:20 PM PDT 24 Jul 16 07:42:34 PM PDT 24 489159812 ps
T250 /workspace/coverage/default/10.sram_ctrl_mem_walk.1682466303 Jul 16 07:41:55 PM PDT 24 Jul 16 07:42:18 PM PDT 24 761091977 ps
T251 /workspace/coverage/default/10.sram_ctrl_ram_cfg.241661006 Jul 16 07:41:56 PM PDT 24 Jul 16 07:42:07 PM PDT 24 191107419 ps
T252 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3819220924 Jul 16 07:42:26 PM PDT 24 Jul 16 07:45:34 PM PDT 24 5569136291 ps
T253 /workspace/coverage/default/35.sram_ctrl_bijection.1021183117 Jul 16 07:43:42 PM PDT 24 Jul 16 07:44:24 PM PDT 24 9060208204 ps
T254 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2545989218 Jul 16 07:42:54 PM PDT 24 Jul 16 07:43:00 PM PDT 24 71085191 ps
T255 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4171284523 Jul 16 07:43:08 PM PDT 24 Jul 16 07:43:15 PM PDT 24 429777742 ps
T256 /workspace/coverage/default/33.sram_ctrl_max_throughput.2826371049 Jul 16 07:43:43 PM PDT 24 Jul 16 07:45:46 PM PDT 24 185493734 ps
T257 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.853111381 Jul 16 07:41:57 PM PDT 24 Jul 16 07:48:43 PM PDT 24 17559789341 ps
T258 /workspace/coverage/default/4.sram_ctrl_executable.199331383 Jul 16 07:41:19 PM PDT 24 Jul 16 07:57:55 PM PDT 24 11742328613 ps
T259 /workspace/coverage/default/7.sram_ctrl_bijection.3349236550 Jul 16 07:41:29 PM PDT 24 Jul 16 07:42:51 PM PDT 24 1806303468 ps
T260 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.166172324 Jul 16 07:42:23 PM PDT 24 Jul 16 07:42:34 PM PDT 24 2041518978 ps
T261 /workspace/coverage/default/22.sram_ctrl_bijection.1590414634 Jul 16 07:42:23 PM PDT 24 Jul 16 07:43:55 PM PDT 24 10914898094 ps
T262 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2855353641 Jul 16 07:41:58 PM PDT 24 Jul 16 07:48:35 PM PDT 24 21239763304 ps
T263 /workspace/coverage/default/29.sram_ctrl_alert_test.2033656345 Jul 16 07:43:06 PM PDT 24 Jul 16 07:43:10 PM PDT 24 12449924 ps
T264 /workspace/coverage/default/24.sram_ctrl_partial_access.2779331824 Jul 16 07:42:52 PM PDT 24 Jul 16 07:43:11 PM PDT 24 704892824 ps
T265 /workspace/coverage/default/3.sram_ctrl_alert_test.3413457942 Jul 16 07:41:20 PM PDT 24 Jul 16 07:41:42 PM PDT 24 13907685 ps
T266 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2389587382 Jul 16 07:41:56 PM PDT 24 Jul 16 07:48:17 PM PDT 24 27841693329 ps
T267 /workspace/coverage/default/29.sram_ctrl_max_throughput.1365509024 Jul 16 07:43:05 PM PDT 24 Jul 16 07:43:10 PM PDT 24 127337278 ps
T268 /workspace/coverage/default/18.sram_ctrl_bijection.2198639835 Jul 16 07:42:08 PM PDT 24 Jul 16 07:42:56 PM PDT 24 874296466 ps
T269 /workspace/coverage/default/23.sram_ctrl_partial_access.1017629493 Jul 16 07:42:36 PM PDT 24 Jul 16 07:45:09 PM PDT 24 621949561 ps
T47 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4075577073 Jul 16 07:41:26 PM PDT 24 Jul 16 07:45:23 PM PDT 24 16348745976 ps
T270 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3497798045 Jul 16 07:42:28 PM PDT 24 Jul 16 07:47:01 PM PDT 24 1741312860 ps
T271 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4132502387 Jul 16 07:42:50 PM PDT 24 Jul 16 07:48:08 PM PDT 24 12442601821 ps
T272 /workspace/coverage/default/33.sram_ctrl_ram_cfg.530636967 Jul 16 07:43:35 PM PDT 24 Jul 16 07:43:37 PM PDT 24 33238732 ps
T273 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1875579494 Jul 16 07:42:20 PM PDT 24 Jul 16 07:42:54 PM PDT 24 195324692 ps
T274 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1921344942 Jul 16 07:46:23 PM PDT 24 Jul 16 07:51:20 PM PDT 24 11466417747 ps
T275 /workspace/coverage/default/36.sram_ctrl_partial_access.128159513 Jul 16 07:43:51 PM PDT 24 Jul 16 07:44:08 PM PDT 24 925298972 ps
T276 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3518384998 Jul 16 07:44:40 PM PDT 24 Jul 16 07:44:48 PM PDT 24 972342395 ps
T277 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.869795526 Jul 16 07:43:19 PM PDT 24 Jul 16 08:03:10 PM PDT 24 3707886950 ps
T278 /workspace/coverage/default/49.sram_ctrl_alert_test.648300399 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:25 PM PDT 24 25405157 ps
T279 /workspace/coverage/default/8.sram_ctrl_regwen.2450596004 Jul 16 07:41:30 PM PDT 24 Jul 16 07:52:22 PM PDT 24 17092537267 ps
T280 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.284179551 Jul 16 07:44:25 PM PDT 24 Jul 16 07:48:30 PM PDT 24 9564237077 ps
T281 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.4033845366 Jul 16 07:41:28 PM PDT 24 Jul 16 07:50:03 PM PDT 24 1213438780 ps
T282 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4039739266 Jul 16 07:42:50 PM PDT 24 Jul 16 08:01:04 PM PDT 24 15987849611 ps
T283 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1743378682 Jul 16 07:44:39 PM PDT 24 Jul 16 07:47:21 PM PDT 24 9310224402 ps
T284 /workspace/coverage/default/24.sram_ctrl_bijection.1302663941 Jul 16 07:42:38 PM PDT 24 Jul 16 07:43:32 PM PDT 24 22478605236 ps
T285 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3322333518 Jul 16 07:42:28 PM PDT 24 Jul 16 07:42:42 PM PDT 24 511955404 ps
T286 /workspace/coverage/default/1.sram_ctrl_alert_test.3487572215 Jul 16 07:41:11 PM PDT 24 Jul 16 07:41:27 PM PDT 24 26365532 ps
T287 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2676337741 Jul 16 07:42:53 PM PDT 24 Jul 16 07:44:16 PM PDT 24 1131559376 ps
T288 /workspace/coverage/default/3.sram_ctrl_ram_cfg.2672556143 Jul 16 07:41:20 PM PDT 24 Jul 16 07:41:40 PM PDT 24 29394740 ps
T289 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1645510980 Jul 16 07:43:19 PM PDT 24 Jul 16 07:46:32 PM PDT 24 7954612979 ps
T290 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1627136280 Jul 16 07:41:58 PM PDT 24 Jul 16 07:46:16 PM PDT 24 2491782361 ps
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T292 /workspace/coverage/default/40.sram_ctrl_alert_test.1129354289 Jul 16 07:44:23 PM PDT 24 Jul 16 07:44:25 PM PDT 24 14848354 ps
T293 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.4100974612 Jul 16 07:43:53 PM PDT 24 Jul 16 07:46:07 PM PDT 24 1401814264 ps
T294 /workspace/coverage/default/30.sram_ctrl_bijection.3703539047 Jul 16 07:43:08 PM PDT 24 Jul 16 07:44:25 PM PDT 24 3279334958 ps
T295 /workspace/coverage/default/31.sram_ctrl_bijection.1724761625 Jul 16 07:43:20 PM PDT 24 Jul 16 07:44:25 PM PDT 24 937304669 ps
T296 /workspace/coverage/default/19.sram_ctrl_partial_access.1968051868 Jul 16 07:42:18 PM PDT 24 Jul 16 07:43:29 PM PDT 24 450888307 ps
T297 /workspace/coverage/default/31.sram_ctrl_alert_test.2166198985 Jul 16 07:43:21 PM PDT 24 Jul 16 07:43:25 PM PDT 24 89738782 ps
T298 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3915086984 Jul 16 07:42:23 PM PDT 24 Jul 16 07:42:47 PM PDT 24 4099894840 ps
T299 /workspace/coverage/default/13.sram_ctrl_smoke.23734231 Jul 16 07:41:54 PM PDT 24 Jul 16 07:45:02 PM PDT 24 2749605713 ps
T300 /workspace/coverage/default/44.sram_ctrl_regwen.3439102986 Jul 16 07:44:57 PM PDT 24 Jul 16 07:46:57 PM PDT 24 5154369847 ps
T301 /workspace/coverage/default/36.sram_ctrl_alert_test.2989355050 Jul 16 07:43:56 PM PDT 24 Jul 16 07:43:58 PM PDT 24 23419909 ps
T302 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2836249314 Jul 16 07:41:50 PM PDT 24 Jul 16 07:42:53 PM PDT 24 9408654048 ps
T303 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2306091292 Jul 16 07:45:34 PM PDT 24 Jul 16 07:45:39 PM PDT 24 96987526 ps
T304 /workspace/coverage/default/16.sram_ctrl_executable.2696024883 Jul 16 07:42:04 PM PDT 24 Jul 16 08:03:56 PM PDT 24 58146959105 ps
T305 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3315701806 Jul 16 07:42:52 PM PDT 24 Jul 16 07:43:54 PM PDT 24 213405312 ps
T306 /workspace/coverage/default/13.sram_ctrl_multiple_keys.3101250014 Jul 16 07:41:55 PM PDT 24 Jul 16 08:06:03 PM PDT 24 21481191159 ps
T307 /workspace/coverage/default/15.sram_ctrl_mem_walk.2418541586 Jul 16 07:41:49 PM PDT 24 Jul 16 07:42:08 PM PDT 24 404392439 ps
T308 /workspace/coverage/default/47.sram_ctrl_executable.1408246383 Jul 16 07:45:33 PM PDT 24 Jul 16 07:59:45 PM PDT 24 41721781405 ps
T309 /workspace/coverage/default/7.sram_ctrl_regwen.1637687792 Jul 16 07:41:28 PM PDT 24 Jul 16 07:48:22 PM PDT 24 11363265313 ps
T310 /workspace/coverage/default/37.sram_ctrl_ram_cfg.1664075115 Jul 16 07:43:54 PM PDT 24 Jul 16 07:43:57 PM PDT 24 32626294 ps
T311 /workspace/coverage/default/36.sram_ctrl_executable.3343443120 Jul 16 07:43:52 PM PDT 24 Jul 16 08:03:17 PM PDT 24 16110264399 ps
T312 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2506989558 Jul 16 07:45:34 PM PDT 24 Jul 16 07:45:38 PM PDT 24 291481198 ps
T313 /workspace/coverage/default/43.sram_ctrl_ram_cfg.9945249 Jul 16 07:44:56 PM PDT 24 Jul 16 07:44:58 PM PDT 24 83262348 ps
T314 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3474403495 Jul 16 07:44:11 PM PDT 24 Jul 16 07:44:15 PM PDT 24 110391591 ps
T315 /workspace/coverage/default/9.sram_ctrl_regwen.1974599472 Jul 16 07:41:29 PM PDT 24 Jul 16 07:46:50 PM PDT 24 8271573690 ps
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