Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46863102	1			T1	57765		T2	134686		T3	222
triple_byte_access	2398068	1			T1	1114		T2	2719		T3	207
halfword_access	3601838	1			T1	1719		T2	3977		T3	339
byte_access	4806560	1			T1	2237		T2	5477		T3	431
zero_access	1207855	1			T1	539		T2	1354		T3	118

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29384599

1

T1

31885

T2

73655

T3

692

auto[1]

29492824

1

T1

31489

T2

74558

T3

625

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	23380865	1			T1	29087		T2	66993		T3	121
auto[0]	triple_byte_access	1195769	1			T1	534		T2	1366		T3	107
auto[0]	halfword_access	1797705	1			T1	889		T2	1948		T3	178
auto[0]	byte_access	2402369	1			T1	1102		T2	2690		T3	225
auto[0]	zero_access	607891	1			T1	273		T2	658		T3	61
auto[1]	word_access	23482237	1			T1	28678		T2	67693		T3	101
auto[1]	triple_byte_access	1202299	1			T1	580		T2	1353		T3	100
auto[1]	halfword_access	1804133	1			T1	830		T2	2029		T3	161
auto[1]	byte_access	2404191	1			T1	1135		T2	2787		T3	206
auto[1]	zero_access	599964	1			T1	266		T2	696		T3	57