Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145699656	1			T1	49152		T2	169650		T3	218398
instr_valid_dis	110726016	1			T1	49152		T2	556266		T3	91246
instr_en	22966276	1			T2	105324		T3	62194		T13	229496

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11347900	1			T2	361724		T3	33118		T13	81092
sram_ifetch_valid_disable	111842232	1			T1	49152		T2	737998		T3	60718
sram_ifetch_enable	22509524	1			T2	596784		T3	124562		T13	173476

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145699656	1			T1	49152		T2	169650		T3	218398
hw_debug_en_valid_off	111207112	1			T1	49152		T2	985954		T3	12538
hw_debug_en_on	23174360	1			T2	469546		T3	170844		T13	243878

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111842232	1			T1	49152		T2	737998		T3	60718
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97035518	1			T1	49152		T2	322128		T3	19206
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9922394	1			T2	400742		T3	28946		T13	58940
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4126372	1			T2	95936		T19	75210		T69	12880
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1637186	1			T2	58746		T19	16530		T162	30722
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1638394	1			T2	37190		T19	15608		T69	3874
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4520876	1			T2	105762		T3	33118		T13	41592
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1602928	1			T13	41592		T7	9616		T19	34728
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1862778	1			T2	88706		T161	41194		T167	26064
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8946234	1			T2	138888		T3	31720		T13	109986
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3468586	1			T2	28330		T3	19154		T13	80920
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4196592	1			T2	107508		T13	21280		T76	54968

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8512316	1			T2	366580		T3	33248		T13	131056
lc_exec_en	9707250	1			T2	224896		T3	106006		T13	92300
valid_exec_dis	107497430	1			T1	49152		T2	769998		T3	80044
invalid_exec_dis	33857424	1			T2	958508		T3	157680		T13	254568