Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43770801	1			T1	24576		T2	354661		T3	39700
triple_byte_access	2381960	1			T2	7151		T3	768		T4	2544
halfword_access	3572308	1			T2	10672		T3	1266		T4	3655
byte_access	4773160	1			T2	14193		T3	1580		T4	4970
zero_access	1200026	1			T2	3530		T3	385		T4	1269

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27796899

1

T1

12288

T2

195107

T3

21815

auto[1]

27901356

1

T1

12288

T2

195100

T3

21884

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21837025	1			T1	12288		T2	177347		T3	19807
auto[0]	triple_byte_access	1187782	1			T2	3583		T3	394		T4	1301
auto[0]	halfword_access	1782042	1			T2	5314		T3	623		T4	1882
auto[0]	byte_access	2385748	1			T2	7104		T3	796		T4	2468
auto[0]	zero_access	604302	1			T2	1759		T3	195		T4	644
auto[1]	word_access	21933776	1			T1	12288		T2	177314		T3	19893
auto[1]	triple_byte_access	1194178	1			T2	3568		T3	374		T4	1243
auto[1]	halfword_access	1790266	1			T2	5358		T3	643		T4	1773
auto[1]	byte_access	2387412	1			T2	7089		T3	784		T4	2502
auto[1]	zero_access	595724	1			T2	1771		T3	190		T4	625