Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145347276	1			T1	1894		T2	11168		T3	2010
instr_valid_dis	115038678	1			T1	1894		T2	11168		T3	2010
instr_en	21511903	1			T4	7104		T28	235784		T22	14426

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9551684	1			T12	50150		T28	68790		T22	20638
sram_ifetch_valid_disable	114548386	1			T1	1894		T2	11168		T3	2010
sram_ifetch_enable	21247206	1			T4	7104		T12	20356		T28	252554

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145347276	1			T1	1894		T2	11168		T3	2010
hw_debug_en_valid_off	114239552	1			T1	1894		T2	11168		T3	2010
hw_debug_en_on	19771404	1			T12	84612		T28	63564		T22	130352

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114548386	1			T1	1894		T2	11168		T3	2010
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102837178	1			T1	1894		T2	11168		T3	2010
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8307155	1			T28	46638		T22	14426		T24	15478
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3794072	1			T28	60634		T22	20638		T137	19420
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1699876	1			T28	98		T135	53378		T63	24326
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1432610	1			T28	60536		T137	19420		T119	42792
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3715152	1			T12	14172		T24	142992		T137	61412
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1353140	1			T12	14172		T137	47624		T139	56
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1961614	1			T24	142992		T137	13788		T25	12012
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7583554	1			T12	57498		T22	63226		T24	13016
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3049388	1			T139	20248		T63	15546		T136	66894
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3551616	1			T22	14426		T24	13016		T137	65904

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8937034	1			T4	7104		T28	128610		T24	102348
lc_exec_en	8472698	1			T12	12942		T28	63564		T22	67126
valid_exec_dis	110994190	1			T1	1894		T2	11168		T3	2010
invalid_exec_dis	30798890	1			T4	7104		T12	70506		T28	321344