Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	99.16	94.27	99.72	100.00	95.95	99.12	97.26

Total tests in report: 1023

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
82.55	82.55	95.93	95.93	80.92	80.92	94.97	94.97	61.90	61.90	86.47	86.47	94.40	94.40	63.25	63.25	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4055478079
90.04	7.49	97.46	1.53	82.46	1.54	96.50	1.53	90.48	28.57	89.86	3.38	94.40	0.00	79.16	15.90	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1416438523
93.02	2.98	98.73	1.27	85.66	3.20	96.91	0.42	100.00	9.52	93.00	3.14	94.40	0.00	82.45	3.29	/workspace/coverage/default/41.sram_ctrl_stress_all.380977384
94.10	1.08	98.73	0.00	87.91	2.25	96.95	0.03	100.00	0.00	94.44	1.45	95.28	0.88	85.37	2.93	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3066483384
95.11	1.01	98.90	0.17	88.74	0.83	97.16	0.21	100.00	0.00	95.17	0.72	95.28	0.00	90.49	5.12	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.439455944
95.81	0.71	99.07	0.17	90.52	1.78	97.92	0.76	100.00	0.00	95.89	0.72	95.87	0.59	91.41	0.91	/workspace/coverage/default/2.sram_ctrl_sec_cm.2892962532
96.32	0.51	99.07	0.00	90.52	0.00	98.75	0.83	100.00	0.00	95.89	0.00	95.87	0.00	94.15	2.74	/workspace/coverage/default/35.sram_ctrl_executable.653588260
96.52	0.20	99.07	0.00	90.52	0.00	98.82	0.07	100.00	0.00	95.89	0.00	97.20	1.33	94.15	0.00	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2455937527
96.71	0.19	99.07	0.00	90.52	0.00	98.82	0.00	100.00	0.00	96.14	0.24	98.08	0.88	94.33	0.18	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3178075727
96.89	0.18	99.07	0.00	90.52	0.00	98.82	0.00	100.00	0.00	96.14	0.00	98.08	0.00	95.61	1.28	/workspace/coverage/default/27.sram_ctrl_executable.2500402341
97.02	0.13	99.15	0.08	90.52	0.00	99.65	0.83	100.00	0.00	96.14	0.00	98.08	0.00	95.61	0.00	/workspace/coverage/default/16.sram_ctrl_ram_cfg.3398045600
97.13	0.11	99.15	0.00	90.52	0.00	99.65	0.00	100.00	0.00	96.14	0.00	98.82	0.74	95.61	0.00	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2635388756
97.23	0.10	99.15	0.00	90.52	0.00	99.65	0.00	100.00	0.00	96.14	0.00	98.82	0.00	96.34	0.73	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2432471256
97.31	0.07	99.15	0.00	90.52	0.00	99.65	0.00	100.00	0.00	96.14	0.00	98.97	0.15	96.71	0.37	/workspace/coverage/default/37.sram_ctrl_regwen.1278836378
97.37	0.06	99.15	0.00	90.88	0.36	99.72	0.07	100.00	0.00	96.14	0.00	98.97	0.00	96.71	0.00	/workspace/coverage/default/11.sram_ctrl_alert_test.2765445108
97.42	0.05	99.15	0.00	90.88	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.07	0.37	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1758718641
97.46	0.04	99.15	0.00	91.00	0.12	99.72	0.00	100.00	0.00	96.14	0.00	98.97	0.00	97.26	0.18	/workspace/coverage/default/11.sram_ctrl_lc_escalation.3385316901
97.48	0.02	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.15	97.26	0.00	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1295487640

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2533037795
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3395042338
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2818050036
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3513765505
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2623656309
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1277871726
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3890167248
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3270729553
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.610063113
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2108999651
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1688293256
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3701580833
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1176506877
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3307840898
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1035453273
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.445576049
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1674351388
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4138879150
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2070746797
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1025333102
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1833743089
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2739599118
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2506522892
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1424515262
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1959760058
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3961502465
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1800268758
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1312208550
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2036123153
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3526368511
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.667402487
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1682819051
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.365033978
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3239578757
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3049846109
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4242847952
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1433347816
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2038961535
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2173125830
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3496650137
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1541216661
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2887934961
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.194501957
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.315209143
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1380682988
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1165421113
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1622611687
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3337866649
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.44414564
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2393684
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3810492355
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1031298871
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3819911119
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4076358158
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.988703501
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.636986836
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1302209340
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2246311906
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3632580406
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3576311455
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2605106374
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4202474823
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.985827746
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3369636539
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1896772444
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3293424552
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2313160904
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.372854267
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3745016737
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2687111840
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2935582902
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3968727378
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.20792458
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2182571856
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3869600217
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2077592771
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3187957357
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1958360528
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1342357147
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1070557338
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2662875282
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1465225871
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3729468567
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3594543766
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.403578725
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.948446859
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3225330597
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.441508599
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2596784011
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.545962935
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2411916128
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2114212849
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1275131980
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2223321593
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1054145002
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3406051679
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3854640348
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1126836708
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3353404159
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2461523887
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2863999115
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2366593420
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.711628005
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3596697510
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3348831925
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.540103235
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.204450114
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2293792969
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2022854227
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4133025301
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4072831647
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1037701151
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.293016513
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1312098702
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3177534393
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3685705992
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3869387095
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2154111590
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3019150806
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.448556203
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.807832499
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.525574019
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3273215135
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4186150693
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1102510569
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.170479237
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3322814611
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1547818330
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2569472770
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2616914224
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3489453419
/workspace/coverage/default/0.sram_ctrl_alert_test.157516658
/workspace/coverage/default/0.sram_ctrl_bijection.1874254211
/workspace/coverage/default/0.sram_ctrl_executable.2008548893
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3744695670
/workspace/coverage/default/0.sram_ctrl_max_throughput.3883964809
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.620029524
/workspace/coverage/default/0.sram_ctrl_mem_walk.2739088627
/workspace/coverage/default/0.sram_ctrl_multiple_keys.168813933
/workspace/coverage/default/0.sram_ctrl_partial_access.1272314911
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2999281182
/workspace/coverage/default/0.sram_ctrl_regwen.228067146
/workspace/coverage/default/0.sram_ctrl_sec_cm.3711710726
/workspace/coverage/default/0.sram_ctrl_smoke.748345999
/workspace/coverage/default/0.sram_ctrl_stress_all.2172969854
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4079249825
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.93820385
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3708257915
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1834994447
/workspace/coverage/default/1.sram_ctrl_alert_test.3063253560
/workspace/coverage/default/1.sram_ctrl_bijection.2870638353
/workspace/coverage/default/1.sram_ctrl_executable.2071185776
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2550694043
/workspace/coverage/default/1.sram_ctrl_max_throughput.2963149101
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3679711354
/workspace/coverage/default/1.sram_ctrl_mem_walk.3306641199
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2414763283
/workspace/coverage/default/1.sram_ctrl_partial_access.27386186
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3899806142
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1374951301
/workspace/coverage/default/1.sram_ctrl_regwen.3277432224
/workspace/coverage/default/1.sram_ctrl_sec_cm.2133880439
/workspace/coverage/default/1.sram_ctrl_smoke.256777131
/workspace/coverage/default/1.sram_ctrl_stress_all.1299362438
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4281160143
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.23751520
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3357970394
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2956006137
/workspace/coverage/default/10.sram_ctrl_alert_test.898799952
/workspace/coverage/default/10.sram_ctrl_bijection.1764626038
/workspace/coverage/default/10.sram_ctrl_executable.120664561
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3852071361
/workspace/coverage/default/10.sram_ctrl_max_throughput.3601344977
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1692657704
/workspace/coverage/default/10.sram_ctrl_mem_walk.3739788242
/workspace/coverage/default/10.sram_ctrl_multiple_keys.928326157
/workspace/coverage/default/10.sram_ctrl_partial_access.3857385499
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2979936548
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1462538469
/workspace/coverage/default/10.sram_ctrl_regwen.1235351567
/workspace/coverage/default/10.sram_ctrl_smoke.2152214304
/workspace/coverage/default/10.sram_ctrl_stress_all.97476091
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2269849319
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3567957457
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1698676980
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1847863774
/workspace/coverage/default/11.sram_ctrl_bijection.4204580507
/workspace/coverage/default/11.sram_ctrl_executable.1692090923
/workspace/coverage/default/11.sram_ctrl_max_throughput.1394793776
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4134263661
/workspace/coverage/default/11.sram_ctrl_mem_walk.1620726115
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3870794086
/workspace/coverage/default/11.sram_ctrl_partial_access.2972329803
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3840097341
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1942964904
/workspace/coverage/default/11.sram_ctrl_regwen.2149963439
/workspace/coverage/default/11.sram_ctrl_smoke.431671785
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/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1404681668
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2413039469
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2232392768
/workspace/coverage/default/43.sram_ctrl_alert_test.674297883
/workspace/coverage/default/43.sram_ctrl_bijection.3963721127
/workspace/coverage/default/43.sram_ctrl_executable.3983143469
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2712437349
/workspace/coverage/default/43.sram_ctrl_max_throughput.2291478350
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3339513798
/workspace/coverage/default/43.sram_ctrl_mem_walk.1750659296
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3518588065
/workspace/coverage/default/43.sram_ctrl_partial_access.2610038691
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4262484895
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2492897546
/workspace/coverage/default/43.sram_ctrl_regwen.483035777
/workspace/coverage/default/43.sram_ctrl_smoke.905045650
/workspace/coverage/default/43.sram_ctrl_stress_all.1459443065
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.997183620
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4056712274
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2453322167
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.885719412
/workspace/coverage/default/44.sram_ctrl_alert_test.2542469153
/workspace/coverage/default/44.sram_ctrl_bijection.3044756340
/workspace/coverage/default/44.sram_ctrl_executable.3791867690
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2819335421
/workspace/coverage/default/44.sram_ctrl_max_throughput.3903530
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2023413430
/workspace/coverage/default/44.sram_ctrl_mem_walk.1174445072
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1431290579
/workspace/coverage/default/44.sram_ctrl_partial_access.2242527504
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1062480800
/workspace/coverage/default/44.sram_ctrl_ram_cfg.190895187
/workspace/coverage/default/44.sram_ctrl_regwen.2432181848
/workspace/coverage/default/44.sram_ctrl_smoke.1095817301
/workspace/coverage/default/44.sram_ctrl_stress_all.2544654846
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4161585185
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3606736232
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1530102108
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2389030732
/workspace/coverage/default/45.sram_ctrl_alert_test.2566210361
/workspace/coverage/default/45.sram_ctrl_bijection.3238528088
/workspace/coverage/default/45.sram_ctrl_executable.1213877361
/workspace/coverage/default/45.sram_ctrl_lc_escalation.765764403
/workspace/coverage/default/45.sram_ctrl_max_throughput.2359860816
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2430507339
/workspace/coverage/default/45.sram_ctrl_mem_walk.2690410869
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2474856751
/workspace/coverage/default/45.sram_ctrl_partial_access.893180401
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3838848035
/workspace/coverage/default/45.sram_ctrl_ram_cfg.4003396441
/workspace/coverage/default/45.sram_ctrl_regwen.2551668967
/workspace/coverage/default/45.sram_ctrl_smoke.3754611935
/workspace/coverage/default/45.sram_ctrl_stress_all.2528294943
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2169738239
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1565030092
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1001993261
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1702880079
/workspace/coverage/default/46.sram_ctrl_alert_test.3780063100
/workspace/coverage/default/46.sram_ctrl_bijection.1615407229
/workspace/coverage/default/46.sram_ctrl_executable.3954361571
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3625668771
/workspace/coverage/default/46.sram_ctrl_max_throughput.3544639486
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.4041085051
/workspace/coverage/default/46.sram_ctrl_mem_walk.261067107
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3537340854
/workspace/coverage/default/46.sram_ctrl_partial_access.132985118
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.539194272
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1561022496
/workspace/coverage/default/46.sram_ctrl_regwen.183288388
/workspace/coverage/default/46.sram_ctrl_smoke.188552005
/workspace/coverage/default/46.sram_ctrl_stress_all.2789245284
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3420500316
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4179175260
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3003967152
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.4000856779
/workspace/coverage/default/47.sram_ctrl_alert_test.3781609658
/workspace/coverage/default/47.sram_ctrl_bijection.4268117065
/workspace/coverage/default/47.sram_ctrl_executable.2419346414
/workspace/coverage/default/47.sram_ctrl_lc_escalation.4682361
/workspace/coverage/default/47.sram_ctrl_max_throughput.3851282479
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3686172534
/workspace/coverage/default/47.sram_ctrl_mem_walk.4153807534
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1487746137
/workspace/coverage/default/47.sram_ctrl_partial_access.3019132061
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3099895535
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3583000974
/workspace/coverage/default/47.sram_ctrl_regwen.2707265135
/workspace/coverage/default/47.sram_ctrl_smoke.197812609
/workspace/coverage/default/47.sram_ctrl_stress_all.296491365
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.599355225
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.495801339
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3084395878
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2008591195
/workspace/coverage/default/48.sram_ctrl_alert_test.3729391384
/workspace/coverage/default/48.sram_ctrl_bijection.1821268010
/workspace/coverage/default/48.sram_ctrl_executable.2794113892
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1127887567
/workspace/coverage/default/48.sram_ctrl_max_throughput.1634468244
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1965559314
/workspace/coverage/default/48.sram_ctrl_mem_walk.3772374823
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2889520951
/workspace/coverage/default/48.sram_ctrl_partial_access.281977086
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2537288257
/workspace/coverage/default/48.sram_ctrl_ram_cfg.624507444
/workspace/coverage/default/48.sram_ctrl_regwen.864199963
/workspace/coverage/default/48.sram_ctrl_smoke.3231331724
/workspace/coverage/default/48.sram_ctrl_stress_all.2439001517
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4025050395
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2766012687
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1940343235
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1818585603
/workspace/coverage/default/49.sram_ctrl_alert_test.2379337558
/workspace/coverage/default/49.sram_ctrl_bijection.531710633
/workspace/coverage/default/49.sram_ctrl_executable.3037846806
/workspace/coverage/default/49.sram_ctrl_lc_escalation.259752232
/workspace/coverage/default/49.sram_ctrl_max_throughput.1841520454
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3735423358
/workspace/coverage/default/49.sram_ctrl_mem_walk.1876853583
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2711989190
/workspace/coverage/default/49.sram_ctrl_partial_access.2798043333
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3361721100
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3553360118
/workspace/coverage/default/49.sram_ctrl_regwen.3565352733
/workspace/coverage/default/49.sram_ctrl_smoke.344241443
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1077960643
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3255115541
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.459300387
/workspace/coverage/default/5.sram_ctrl_alert_test.282445465
/workspace/coverage/default/5.sram_ctrl_bijection.877434737
/workspace/coverage/default/5.sram_ctrl_executable.2958800953
/workspace/coverage/default/5.sram_ctrl_lc_escalation.936460429
/workspace/coverage/default/5.sram_ctrl_max_throughput.2705374993
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1417606302
/workspace/coverage/default/5.sram_ctrl_mem_walk.2296093853
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4081652935
/workspace/coverage/default/5.sram_ctrl_partial_access.2023652349
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3761991344
/workspace/coverage/default/5.sram_ctrl_regwen.3790010898
/workspace/coverage/default/5.sram_ctrl_smoke.2415823762
/workspace/coverage/default/5.sram_ctrl_stress_all.2417790938
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3697008135
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.807333414
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1371412312
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.107292954
/workspace/coverage/default/6.sram_ctrl_alert_test.3834111561
/workspace/coverage/default/6.sram_ctrl_bijection.3454671810
/workspace/coverage/default/6.sram_ctrl_executable.359832536
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1877881181
/workspace/coverage/default/6.sram_ctrl_max_throughput.3119746494
/workspace/coverage/default/6.sram_ctrl_mem_walk.2650209080
/workspace/coverage/default/6.sram_ctrl_multiple_keys.720291444
/workspace/coverage/default/6.sram_ctrl_partial_access.545189499
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.753023305
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1521329924
/workspace/coverage/default/6.sram_ctrl_regwen.3292088382
/workspace/coverage/default/6.sram_ctrl_smoke.1378401893
/workspace/coverage/default/6.sram_ctrl_stress_all.2429048738
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2724018141
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1593473674
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.949594465
/workspace/coverage/default/7.sram_ctrl_alert_test.862584719
/workspace/coverage/default/7.sram_ctrl_bijection.2502181026
/workspace/coverage/default/7.sram_ctrl_executable.4263295041
/workspace/coverage/default/7.sram_ctrl_lc_escalation.427055003
/workspace/coverage/default/7.sram_ctrl_max_throughput.2374456164
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3885788440
/workspace/coverage/default/7.sram_ctrl_mem_walk.129996460
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2130608843
/workspace/coverage/default/7.sram_ctrl_partial_access.3057362323
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1603193762
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3224237686
/workspace/coverage/default/7.sram_ctrl_regwen.883356912
/workspace/coverage/default/7.sram_ctrl_smoke.2946980264
/workspace/coverage/default/7.sram_ctrl_stress_all.3612044767
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3801100083
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2872355543
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1389114646
/workspace/coverage/default/8.sram_ctrl_alert_test.2596172
/workspace/coverage/default/8.sram_ctrl_bijection.2161056617
/workspace/coverage/default/8.sram_ctrl_executable.2969019637
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1754781742
/workspace/coverage/default/8.sram_ctrl_max_throughput.2381503142
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1334148117
/workspace/coverage/default/8.sram_ctrl_mem_walk.135228287
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1919066073
/workspace/coverage/default/8.sram_ctrl_partial_access.2899871150
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.632038573
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3084665841
/workspace/coverage/default/8.sram_ctrl_regwen.3316575372
/workspace/coverage/default/8.sram_ctrl_smoke.3583746895
/workspace/coverage/default/8.sram_ctrl_stress_all.1272841328
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.619155340
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1223230672
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.20158707
/workspace/coverage/default/9.sram_ctrl_alert_test.2715731662
/workspace/coverage/default/9.sram_ctrl_bijection.1431965829
/workspace/coverage/default/9.sram_ctrl_executable.4098804381
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3938510921
/workspace/coverage/default/9.sram_ctrl_max_throughput.3038851344
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1795519413
/workspace/coverage/default/9.sram_ctrl_mem_walk.374811573
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1805043093
/workspace/coverage/default/9.sram_ctrl_partial_access.3227938147
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1965308561
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1114284117
/workspace/coverage/default/9.sram_ctrl_regwen.1001457178
/workspace/coverage/default/9.sram_ctrl_smoke.1409506376
/workspace/coverage/default/9.sram_ctrl_stress_all.3855414937
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2068637319
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.540829843
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3227373674

Total test records in report: 1023

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/14.sram_ctrl_max_throughput.2342578442	Jul 18 07:04:02 PM PDT 24	Jul 18 07:04:14 PM PDT 24	137088180 ps
T2	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.16131413	Jul 18 07:07:18 PM PDT 24	Jul 18 07:08:03 PM PDT 24	232318710 ps
T3	/workspace/coverage/default/11.sram_ctrl_partial_access.2972329803	Jul 18 07:04:00 PM PDT 24	Jul 18 07:04:11 PM PDT 24	127865260 ps
T4	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4055478079	Jul 18 07:03:41 PM PDT 24	Jul 18 07:10:25 PM PDT 24	2957567353 ps
T8	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3321665826	Jul 18 07:03:25 PM PDT 24	Jul 18 07:08:03 PM PDT 24	4811836145 ps
T9	/workspace/coverage/default/35.sram_ctrl_multiple_keys.3100603390	Jul 18 07:06:02 PM PDT 24	Jul 18 07:19:41 PM PDT 24	2253387116 ps
T10	/workspace/coverage/default/32.sram_ctrl_partial_access.3859383772	Jul 18 07:05:39 PM PDT 24	Jul 18 07:05:54 PM PDT 24	264109194 ps
T11	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3066483384	Jul 18 07:03:32 PM PDT 24	Jul 18 07:10:48 PM PDT 24	124815559830 ps
T12	/workspace/coverage/default/47.sram_ctrl_executable.2419346414	Jul 18 07:09:17 PM PDT 24	Jul 18 07:16:17 PM PDT 24	4582857345 ps
T13	/workspace/coverage/default/42.sram_ctrl_max_throughput.2149507536	Jul 18 07:07:18 PM PDT 24	Jul 18 07:07:58 PM PDT 24	459658602 ps
T44	/workspace/coverage/default/13.sram_ctrl_partial_access.2040500371	Jul 18 07:04:01 PM PDT 24	Jul 18 07:06:43 PM PDT 24	458625458 ps
T20	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3697008135	Jul 18 07:03:25 PM PDT 24	Jul 18 07:06:14 PM PDT 24	1475591035 ps
T29	/workspace/coverage/default/29.sram_ctrl_ram_cfg.2538543114	Jul 18 07:05:19 PM PDT 24	Jul 18 07:05:26 PM PDT 24	43267668 ps
T64	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.197228129	Jul 18 07:03:28 PM PDT 24	Jul 18 07:03:44 PM PDT 24	65237405 ps
T28	/workspace/coverage/default/49.sram_ctrl_executable.3037846806	Jul 18 07:10:15 PM PDT 24	Jul 18 07:35:57 PM PDT 24	41873911129 ps
T42	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3012599440	Jul 18 07:06:18 PM PDT 24	Jul 18 07:14:37 PM PDT 24	174779595184 ps
T43	/workspace/coverage/default/28.sram_ctrl_partial_access.2787922979	Jul 18 07:05:15 PM PDT 24	Jul 18 07:05:23 PM PDT 24	435757772 ps
T14	/workspace/coverage/default/42.sram_ctrl_alert_test.872033631	Jul 18 07:07:19 PM PDT 24	Jul 18 07:07:25 PM PDT 24	23693057 ps
T21	/workspace/coverage/default/7.sram_ctrl_bijection.2502181026	Jul 18 07:03:45 PM PDT 24	Jul 18 07:05:23 PM PDT 24	68253175067 ps
T106	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.206927137	Jul 18 07:05:16 PM PDT 24	Jul 18 07:10:12 PM PDT 24	3096912599 ps
T22	/workspace/coverage/default/35.sram_ctrl_regwen.3906053383	Jul 18 07:06:02 PM PDT 24	Jul 18 07:13:50 PM PDT 24	9382798818 ps
T74	/workspace/coverage/default/22.sram_ctrl_multiple_keys.3674936536	Jul 18 07:04:43 PM PDT 24	Jul 18 07:15:33 PM PDT 24	11957831919 ps
T75	/workspace/coverage/default/27.sram_ctrl_multiple_keys.1066210762	Jul 18 07:05:06 PM PDT 24	Jul 18 07:25:29 PM PDT 24	3385444931 ps
T76	/workspace/coverage/default/33.sram_ctrl_max_throughput.4097077821	Jul 18 07:05:51 PM PDT 24	Jul 18 07:06:36 PM PDT 24	419223099 ps
T77	/workspace/coverage/default/29.sram_ctrl_multiple_keys.2032481156	Jul 18 07:05:17 PM PDT 24	Jul 18 07:41:00 PM PDT 24	76117235039 ps
T78	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1295487640	Jul 18 07:03:16 PM PDT 24	Jul 18 07:09:11 PM PDT 24	49880449341 ps
T79	/workspace/coverage/default/20.sram_ctrl_partial_access.3980776041	Jul 18 07:04:23 PM PDT 24	Jul 18 07:04:37 PM PDT 24	736572031 ps
T47	/workspace/coverage/default/19.sram_ctrl_mem_walk.846435311	Jul 18 07:04:22 PM PDT 24	Jul 18 07:04:32 PM PDT 24	332663675 ps
T15	/workspace/coverage/default/22.sram_ctrl_alert_test.578428850	Jul 18 07:04:43 PM PDT 24	Jul 18 07:04:45 PM PDT 24	38065006 ps
T80	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1406632842	Jul 18 07:05:51 PM PDT 24	Jul 18 07:05:55 PM PDT 24	181437468 ps
T107	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.448335593	Jul 18 07:04:47 PM PDT 24	Jul 18 07:08:46 PM PDT 24	3293643725 ps
T5	/workspace/coverage/default/36.sram_ctrl_lc_escalation.97908602	Jul 18 07:06:15 PM PDT 24	Jul 18 07:06:21 PM PDT 24	438229039 ps
T51	/workspace/coverage/default/18.sram_ctrl_mem_walk.3285844487	Jul 18 07:04:13 PM PDT 24	Jul 18 07:04:31 PM PDT 24	760337683 ps
T50	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1965559314	Jul 18 07:10:15 PM PDT 24	Jul 18 07:10:25 PM PDT 24	191629266 ps
T143	/workspace/coverage/default/21.sram_ctrl_multiple_keys.4193221760	Jul 18 07:04:26 PM PDT 24	Jul 18 07:11:23 PM PDT 24	13129394962 ps
T147	/workspace/coverage/default/19.sram_ctrl_partial_access.1341452855	Jul 18 07:04:13 PM PDT 24	Jul 18 07:04:26 PM PDT 24	398369651 ps
T45	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1834994447	Jul 18 07:03:16 PM PDT 24	Jul 18 07:15:22 PM PDT 24	12726606504 ps
T145	/workspace/coverage/default/44.sram_ctrl_partial_access.2242527504	Jul 18 07:07:19 PM PDT 24	Jul 18 07:08:00 PM PDT 24	349732465 ps
T144	/workspace/coverage/default/29.sram_ctrl_bijection.2568148188	Jul 18 07:05:19 PM PDT 24	Jul 18 07:06:30 PM PDT 24	5774458825 ps
T93	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3178075727	Jul 18 07:03:42 PM PDT 24	Jul 18 07:03:54 PM PDT 24	310072007 ps
T30	/workspace/coverage/default/6.sram_ctrl_ram_cfg.1521329924	Jul 18 07:03:40 PM PDT 24	Jul 18 07:03:49 PM PDT 24	69869471 ps
T16	/workspace/coverage/default/8.sram_ctrl_alert_test.2596172	Jul 18 07:03:50 PM PDT 24	Jul 18 07:03:56 PM PDT 24	28959843 ps
T24	/workspace/coverage/default/43.sram_ctrl_regwen.483035777	Jul 18 07:07:21 PM PDT 24	Jul 18 07:27:19 PM PDT 24	28620428145 ps
T46	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1847863774	Jul 18 07:03:58 PM PDT 24	Jul 18 07:15:14 PM PDT 24	4235507903 ps
T65	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1959271263	Jul 18 07:04:44 PM PDT 24	Jul 18 07:04:51 PM PDT 24	368453487 ps
T148	/workspace/coverage/default/45.sram_ctrl_bijection.3238528088	Jul 18 07:09:17 PM PDT 24	Jul 18 07:09:39 PM PDT 24	1493638566 ps
T137	/workspace/coverage/default/35.sram_ctrl_executable.653588260	Jul 18 07:06:02 PM PDT 24	Jul 18 07:27:57 PM PDT 24	44289732098 ps
T54	/workspace/coverage/default/0.sram_ctrl_mem_walk.2739088627	Jul 18 07:03:21 PM PDT 24	Jul 18 07:03:38 PM PDT 24	1325904732 ps
T94	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.358933425	Jul 18 07:04:08 PM PDT 24	Jul 18 07:04:21 PM PDT 24	66576359 ps
T95	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.259949694	Jul 18 07:05:32 PM PDT 24	Jul 18 07:24:50 PM PDT 24	9437406578 ps
T6	/workspace/coverage/default/11.sram_ctrl_lc_escalation.3385316901	Jul 18 07:04:01 PM PDT 24	Jul 18 07:04:15 PM PDT 24	1230969473 ps
T139	/workspace/coverage/default/18.sram_ctrl_executable.2405892721	Jul 18 07:04:21 PM PDT 24	Jul 18 07:14:37 PM PDT 24	14760859656 ps
T135	/workspace/coverage/default/10.sram_ctrl_executable.120664561	Jul 18 07:03:59 PM PDT 24	Jul 18 07:13:34 PM PDT 24	5711780427 ps
T142	/workspace/coverage/default/48.sram_ctrl_multiple_keys.2889520951	Jul 18 07:10:17 PM PDT 24	Jul 18 07:36:31 PM PDT 24	15815587977 ps
T31	/workspace/coverage/default/28.sram_ctrl_ram_cfg.2921492904	Jul 18 07:05:16 PM PDT 24	Jul 18 07:05:23 PM PDT 24	87567518 ps
T108	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1603193762	Jul 18 07:03:45 PM PDT 24	Jul 18 07:09:59 PM PDT 24	16165590605 ps
T146	/workspace/coverage/default/42.sram_ctrl_smoke.3230802152	Jul 18 07:07:16 PM PDT 24	Jul 18 07:07:31 PM PDT 24	753283611 ps
T25	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1416438523	Jul 18 07:03:59 PM PDT 24	Jul 18 07:06:59 PM PDT 24	1417004762 ps
T109	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1894533272	Jul 18 07:03:26 PM PDT 24	Jul 18 07:06:47 PM PDT 24	9796541136 ps
T149	/workspace/coverage/default/4.sram_ctrl_multiple_keys.1118386633	Jul 18 07:03:24 PM PDT 24	Jul 18 07:13:23 PM PDT 24	1853848281 ps
T150	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.154587716	Jul 18 07:03:28 PM PDT 24	Jul 18 07:05:12 PM PDT 24	143504937 ps
T151	/workspace/coverage/default/43.sram_ctrl_multiple_keys.3518588065	Jul 18 07:07:20 PM PDT 24	Jul 18 07:19:23 PM PDT 24	16067676971 ps
T152	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.920076979	Jul 18 07:05:02 PM PDT 24	Jul 18 07:08:27 PM PDT 24	9552574242 ps
T63	/workspace/coverage/default/37.sram_ctrl_regwen.1278836378	Jul 18 07:06:16 PM PDT 24	Jul 18 07:30:02 PM PDT 24	9156227148 ps
T55	/workspace/coverage/default/31.sram_ctrl_mem_walk.2965212506	Jul 18 07:05:33 PM PDT 24	Jul 18 07:05:52 PM PDT 24	13167965619 ps
T153	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3084395878	Jul 18 07:09:16 PM PDT 24	Jul 18 07:09:40 PM PDT 24	262185292 ps
T56	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.511145829	Jul 18 07:06:06 PM PDT 24	Jul 18 07:06:14 PM PDT 24	157981070 ps
T154	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3396033146	Jul 18 07:04:09 PM PDT 24	Jul 18 07:04:56 PM PDT 24	415922102 ps
T68	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.421746892	Jul 18 07:07:22 PM PDT 24	Jul 18 07:10:44 PM PDT 24	3872341364 ps
T155	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1163423866	Jul 18 07:04:45 PM PDT 24	Jul 18 07:04:50 PM PDT 24	86136935 ps
T156	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2766012687	Jul 18 07:10:17 PM PDT 24	Jul 18 07:15:12 PM PDT 24	2933953507 ps
T157	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3544943415	Jul 18 07:05:19 PM PDT 24	Jul 18 07:09:57 PM PDT 24	30483924806 ps
T57	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3730743069	Jul 18 07:06:31 PM PDT 24	Jul 18 07:11:59 PM PDT 24	755248695 ps
T158	/workspace/coverage/default/1.sram_ctrl_smoke.256777131	Jul 18 07:03:16 PM PDT 24	Jul 18 07:03:37 PM PDT 24	241746750 ps
T52	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4281160143	Jul 18 07:03:25 PM PDT 24	Jul 18 07:03:58 PM PDT 24	5904626958 ps
T159	/workspace/coverage/default/27.sram_ctrl_alert_test.1959919841	Jul 18 07:05:15 PM PDT 24	Jul 18 07:05:19 PM PDT 24	31356830 ps
T160	/workspace/coverage/default/35.sram_ctrl_partial_access.3424349068	Jul 18 07:06:02 PM PDT 24	Jul 18 07:07:51 PM PDT 24	763705269 ps
T161	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3686172534	Jul 18 07:09:17 PM PDT 24	Jul 18 07:09:27 PM PDT 24	628267977 ps
T162	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1593473674	Jul 18 07:03:39 PM PDT 24	Jul 18 07:04:19 PM PDT 24	399118315 ps
T163	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2537288257	Jul 18 07:10:14 PM PDT 24	Jul 18 07:12:46 PM PDT 24	5652330597 ps
T164	/workspace/coverage/default/44.sram_ctrl_executable.3791867690	Jul 18 07:09:12 PM PDT 24	Jul 18 07:09:22 PM PDT 24	634235075 ps
T165	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.796282948	Jul 18 07:05:18 PM PDT 24	Jul 18 07:10:44 PM PDT 24	39270451900 ps
T166	/workspace/coverage/default/14.sram_ctrl_mem_walk.326575393	Jul 18 07:04:06 PM PDT 24	Jul 18 07:04:27 PM PDT 24	3974011554 ps
T167	/workspace/coverage/default/21.sram_ctrl_mem_walk.3202619936	Jul 18 07:04:28 PM PDT 24	Jul 18 07:04:36 PM PDT 24	104992878 ps
T53	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.929725185	Jul 18 07:03:26 PM PDT 24	Jul 18 07:06:20 PM PDT 24	3055422776 ps
T7	/workspace/coverage/default/45.sram_ctrl_lc_escalation.765764403	Jul 18 07:09:16 PM PDT 24	Jul 18 07:09:27 PM PDT 24	993635472 ps
T118	/workspace/coverage/default/36.sram_ctrl_ram_cfg.3590474571	Jul 18 07:06:20 PM PDT 24	Jul 18 07:06:23 PM PDT 24	51521980 ps
T119	/workspace/coverage/default/30.sram_ctrl_executable.3260340644	Jul 18 07:05:21 PM PDT 24	Jul 18 07:13:20 PM PDT 24	2189112433 ps
T120	/workspace/coverage/default/25.sram_ctrl_partial_access.3816452928	Jul 18 07:05:04 PM PDT 24	Jul 18 07:05:26 PM PDT 24	383218000 ps
T121	/workspace/coverage/default/9.sram_ctrl_alert_test.2715731662	Jul 18 07:03:55 PM PDT 24	Jul 18 07:04:01 PM PDT 24	14466109 ps
T71	/workspace/coverage/default/26.sram_ctrl_regwen.183753751	Jul 18 07:05:04 PM PDT 24	Jul 18 07:08:45 PM PDT 24	12537368574 ps
T122	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.391915421	Jul 18 07:04:44 PM PDT 24	Jul 18 07:06:49 PM PDT 24	1558613443 ps
T123	/workspace/coverage/default/23.sram_ctrl_mem_walk.3294956490	Jul 18 07:04:43 PM PDT 24	Jul 18 07:04:51 PM PDT 24	96339945 ps
T69	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2709440662	Jul 18 07:04:09 PM PDT 24	Jul 18 07:06:28 PM PDT 24	2715981717 ps
T168	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.495294700	Jul 18 07:06:02 PM PDT 24	Jul 18 07:29:23 PM PDT 24	48566393639 ps
T169	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.105104573	Jul 18 07:06:39 PM PDT 24	Jul 18 07:08:56 PM PDT 24	5555032808 ps
T58	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1417606302	Jul 18 07:03:29 PM PDT 24	Jul 18 07:03:43 PM PDT 24	59310678 ps
T136	/workspace/coverage/default/27.sram_ctrl_executable.2500402341	Jul 18 07:05:15 PM PDT 24	Jul 18 07:25:33 PM PDT 24	36969370917 ps
T72	/workspace/coverage/default/5.sram_ctrl_stress_all.2417790938	Jul 18 07:03:28 PM PDT 24	Jul 18 08:02:50 PM PDT 24	178593901987 ps
T170	/workspace/coverage/default/21.sram_ctrl_executable.2183620563	Jul 18 07:04:26 PM PDT 24	Jul 18 07:07:09 PM PDT 24	3180663941 ps
T171	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.883663844	Jul 18 07:03:59 PM PDT 24	Jul 18 07:04:12 PM PDT 24	66252252 ps
T59	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2635388756	Jul 18 07:04:03 PM PDT 24	Jul 18 07:04:41 PM PDT 24	2785641508 ps
T172	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.418816322	Jul 18 07:07:16 PM PDT 24	Jul 18 07:08:20 PM PDT 24	132184138 ps
T173	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.4163252621	Jul 18 07:04:03 PM PDT 24	Jul 18 07:09:24 PM PDT 24	2725480163 ps
T174	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1001993261	Jul 18 07:09:14 PM PDT 24	Jul 18 07:10:17 PM PDT 24	214773402 ps
T175	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4056712274	Jul 18 07:07:20 PM PDT 24	Jul 18 07:12:05 PM PDT 24	2995184466 ps
T23	/workspace/coverage/default/2.sram_ctrl_lc_escalation.708447485	Jul 18 07:03:24 PM PDT 24	Jul 18 07:03:38 PM PDT 24	3939791298 ps
T176	/workspace/coverage/default/7.sram_ctrl_smoke.2946980264	Jul 18 07:03:42 PM PDT 24	Jul 18 07:06:06 PM PDT 24	139187318 ps
T73	/workspace/coverage/default/46.sram_ctrl_regwen.183288388	Jul 18 07:09:14 PM PDT 24	Jul 18 07:15:40 PM PDT 24	32807106150 ps
T177	/workspace/coverage/default/48.sram_ctrl_mem_walk.3772374823	Jul 18 07:10:16 PM PDT 24	Jul 18 07:10:28 PM PDT 24	238469433 ps
T178	/workspace/coverage/default/22.sram_ctrl_max_throughput.44954399	Jul 18 07:04:47 PM PDT 24	Jul 18 07:07:10 PM PDT 24	170060434 ps
T179	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1522886758	Jul 18 07:05:17 PM PDT 24	Jul 18 07:13:25 PM PDT 24	11041352705 ps
T180	/workspace/coverage/default/49.sram_ctrl_partial_access.2798043333	Jul 18 07:10:15 PM PDT 24	Jul 18 07:10:50 PM PDT 24	1219267922 ps
T181	/workspace/coverage/default/48.sram_ctrl_max_throughput.1634468244	Jul 18 07:10:15 PM PDT 24	Jul 18 07:10:40 PM PDT 24	301807652 ps
T182	/workspace/coverage/default/9.sram_ctrl_multiple_keys.1805043093	Jul 18 07:03:50 PM PDT 24	Jul 18 07:25:18 PM PDT 24	3026345572 ps
T183	/workspace/coverage/default/14.sram_ctrl_smoke.3731462206	Jul 18 07:04:04 PM PDT 24	Jul 18 07:04:29 PM PDT 24	894010764 ps
T184	/workspace/coverage/default/47.sram_ctrl_regwen.2707265135	Jul 18 07:09:17 PM PDT 24	Jul 18 07:22:02 PM PDT 24	10619490658 ps
T185	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1372793818	Jul 18 07:05:30 PM PDT 24	Jul 18 07:05:44 PM PDT 24	67705606 ps
T186	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2787725784	Jul 18 07:03:26 PM PDT 24	Jul 18 07:09:25 PM PDT 24	26069261777 ps
T70	/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2169738239	Jul 18 07:09:13 PM PDT 24	Jul 18 07:09:21 PM PDT 24	1414134442 ps
T187	/workspace/coverage/default/30.sram_ctrl_smoke.2590335378	Jul 18 07:05:20 PM PDT 24	Jul 18 07:05:41 PM PDT 24	251797905 ps
T141	/workspace/coverage/default/4.sram_ctrl_lc_escalation.2339302689	Jul 18 07:03:26 PM PDT 24	Jul 18 07:03:40 PM PDT 24	268429072 ps
T188	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1175557590	Jul 18 07:04:04 PM PDT 24	Jul 18 07:05:29 PM PDT 24	293643744 ps
T189	/workspace/coverage/default/36.sram_ctrl_alert_test.3169550456	Jul 18 07:06:21 PM PDT 24	Jul 18 07:06:24 PM PDT 24	76033515 ps
T190	/workspace/coverage/default/37.sram_ctrl_bijection.3476218188	Jul 18 07:06:21 PM PDT 24	Jul 18 07:07:02 PM PDT 24	582891930 ps
T191	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2980059444	Jul 18 07:04:09 PM PDT 24	Jul 18 07:04:20 PM PDT 24	223251177 ps
T192	/workspace/coverage/default/41.sram_ctrl_partial_access.894499017	Jul 18 07:07:18 PM PDT 24	Jul 18 07:07:25 PM PDT 24	219909959 ps
T140	/workspace/coverage/default/26.sram_ctrl_executable.1491956620	Jul 18 07:05:03 PM PDT 24	Jul 18 07:25:09 PM PDT 24	24032071502 ps
T193	/workspace/coverage/default/48.sram_ctrl_regwen.864199963	Jul 18 07:10:14 PM PDT 24	Jul 18 07:15:24 PM PDT 24	16297385492 ps
T194	/workspace/coverage/default/33.sram_ctrl_smoke.2813563223	Jul 18 07:05:46 PM PDT 24	Jul 18 07:07:06 PM PDT 24	1621818651 ps
T195	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2086940795	Jul 18 07:05:46 PM PDT 24	Jul 18 07:09:53 PM PDT 24	2494164767 ps
T196	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1287994777	Jul 18 07:06:15 PM PDT 24	Jul 18 07:10:52 PM PDT 24	100144146473 ps
T26	/workspace/coverage/default/41.sram_ctrl_stress_all.380977384	Jul 18 07:07:16 PM PDT 24	Jul 18 07:40:33 PM PDT 24	98664541557 ps
T197	/workspace/coverage/default/28.sram_ctrl_executable.2668443202	Jul 18 07:05:17 PM PDT 24	Jul 18 07:06:44 PM PDT 24	4621884501 ps
T198	/workspace/coverage/default/42.sram_ctrl_ram_cfg.2715949320	Jul 18 07:07:16 PM PDT 24	Jul 18 07:07:19 PM PDT 24	35516869 ps
T199	/workspace/coverage/default/5.sram_ctrl_bijection.877434737	Jul 18 07:03:31 PM PDT 24	Jul 18 07:04:32 PM PDT 24	12634403927 ps
T200	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1404681668	Jul 18 07:07:16 PM PDT 24	Jul 18 07:13:55 PM PDT 24	14343913046 ps
T201	/workspace/coverage/default/46.sram_ctrl_mem_walk.261067107	Jul 18 07:09:13 PM PDT 24	Jul 18 07:09:28 PM PDT 24	582351660 ps
T202	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.4044970078	Jul 18 07:03:33 PM PDT 24	Jul 18 07:03:48 PM PDT 24	441367098 ps
T203	/workspace/coverage/default/39.sram_ctrl_mem_walk.2782145490	Jul 18 07:06:39 PM PDT 24	Jul 18 07:06:47 PM PDT 24	358682943 ps
T204	/workspace/coverage/default/23.sram_ctrl_stress_all.1996628509	Jul 18 07:04:42 PM PDT 24	Jul 18 07:27:09 PM PDT 24	18199166887 ps
T205	/workspace/coverage/default/5.sram_ctrl_executable.2958800953	Jul 18 07:03:32 PM PDT 24	Jul 18 07:14:20 PM PDT 24	6087844952 ps
T17	/workspace/coverage/default/4.sram_ctrl_sec_cm.116666328	Jul 18 07:03:29 PM PDT 24	Jul 18 07:03:42 PM PDT 24	533261897 ps
T34	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1940343235	Jul 18 07:10:16 PM PDT 24	Jul 18 07:10:45 PM PDT 24	341957785 ps
T35	/workspace/coverage/default/4.sram_ctrl_max_throughput.3232616180	Jul 18 07:03:32 PM PDT 24	Jul 18 07:03:48 PM PDT 24	192605405 ps
T36	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.788804363	Jul 18 07:06:15 PM PDT 24	Jul 18 07:08:33 PM PDT 24	2102872857 ps
T37	/workspace/coverage/default/31.sram_ctrl_multiple_keys.1998519822	Jul 18 07:05:32 PM PDT 24	Jul 18 07:16:48 PM PDT 24	158551954881 ps
T38	/workspace/coverage/default/43.sram_ctrl_smoke.905045650	Jul 18 07:07:23 PM PDT 24	Jul 18 07:07:29 PM PDT 24	190430031 ps
T39	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1352130466	Jul 18 07:05:51 PM PDT 24	Jul 18 07:06:14 PM PDT 24	7029942315 ps
T40	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1421432998	Jul 18 07:04:28 PM PDT 24	Jul 18 07:04:34 PM PDT 24	391854787 ps
T41	/workspace/coverage/default/33.sram_ctrl_multiple_keys.2193274887	Jul 18 07:05:48 PM PDT 24	Jul 18 07:13:43 PM PDT 24	5074693734 ps
T27	/workspace/coverage/default/38.sram_ctrl_lc_escalation.872453485	Jul 18 07:06:20 PM PDT 24	Jul 18 07:06:25 PM PDT 24	280415817 ps
T206	/workspace/coverage/default/11.sram_ctrl_smoke.431671785	Jul 18 07:04:00 PM PDT 24	Jul 18 07:04:22 PM PDT 24	586149196 ps
T48	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1724993986	Jul 18 07:06:04 PM PDT 24	Jul 18 07:07:47 PM PDT 24	1949500669 ps
T207	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3277629788	Jul 18 07:04:58 PM PDT 24	Jul 18 07:05:18 PM PDT 24	96476467 ps
T208	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4109205771	Jul 18 07:05:34 PM PDT 24	Jul 18 07:08:36 PM PDT 24	4820345587 ps
T209	/workspace/coverage/default/16.sram_ctrl_regwen.2308517778	Jul 18 07:04:10 PM PDT 24	Jul 18 07:17:46 PM PDT 24	9823604582 ps
T210	/workspace/coverage/default/37.sram_ctrl_partial_access.3856392647	Jul 18 07:06:16 PM PDT 24	Jul 18 07:06:24 PM PDT 24	1272604134 ps
T18	/workspace/coverage/default/2.sram_ctrl_sec_cm.2892962532	Jul 18 07:03:26 PM PDT 24	Jul 18 07:03:39 PM PDT 24	659003914 ps
T211	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3761991344	Jul 18 07:03:27 PM PDT 24	Jul 18 07:03:38 PM PDT 24	40623547 ps
T212	/workspace/coverage/default/2.sram_ctrl_bijection.1997358565	Jul 18 07:03:27 PM PDT 24	Jul 18 07:04:04 PM PDT 24	1579479366 ps
T213	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2232392768	Jul 18 07:07:18 PM PDT 24	Jul 18 07:29:44 PM PDT 24	5166357106 ps
T214	/workspace/coverage/default/27.sram_ctrl_max_throughput.885505307	Jul 18 07:05:15 PM PDT 24	Jul 18 07:06:13 PM PDT 24	97451050 ps
T215	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3567957457	Jul 18 07:03:46 PM PDT 24	Jul 18 07:10:36 PM PDT 24	3953831948 ps
T216	/workspace/coverage/default/43.sram_ctrl_ram_cfg.2492897546	Jul 18 07:07:16 PM PDT 24	Jul 18 07:07:20 PM PDT 24	48723421 ps
T217	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2257919245	Jul 18 07:05:30 PM PDT 24	Jul 18 07:11:51 PM PDT 24	10529414966 ps
T138	/workspace/coverage/default/37.sram_ctrl_stress_all.3706815498	Jul 18 07:06:18 PM PDT 24	Jul 18 07:45:06 PM PDT 24	177496808090 ps
T218	/workspace/coverage/default/39.sram_ctrl_smoke.3065252728	Jul 18 07:06:30 PM PDT 24	Jul 18 07:07:11 PM PDT 24	329196812 ps
T219	/workspace/coverage/default/40.sram_ctrl_executable.1309891291	Jul 18 07:07:16 PM PDT 24	Jul 18 07:11:34 PM PDT 24	5832864381 ps
T220	/workspace/coverage/default/8.sram_ctrl_partial_access.2899871150	Jul 18 07:03:45 PM PDT 24	Jul 18 07:04:11 PM PDT 24	260792691 ps
T221	/workspace/coverage/default/31.sram_ctrl_smoke.1038317986	Jul 18 07:05:34 PM PDT 24	Jul 18 07:05:48 PM PDT 24	58885196 ps
T222	/workspace/coverage/default/30.sram_ctrl_bijection.3684595444	Jul 18 07:05:22 PM PDT 24	Jul 18 07:05:57 PM PDT 24	494050874 ps
T223	/workspace/coverage/default/4.sram_ctrl_executable.2113462395	Jul 18 07:03:28 PM PDT 24	Jul 18 07:06:16 PM PDT 24	887689037 ps
T224	/workspace/coverage/default/1.sram_ctrl_mem_walk.3306641199	Jul 18 07:03:25 PM PDT 24	Jul 18 07:03:41 PM PDT 24	238043832 ps
T225	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.751387886	Jul 18 07:06:15 PM PDT 24	Jul 18 07:06:23 PM PDT 24	1741528799 ps
T226	/workspace/coverage/default/14.sram_ctrl_alert_test.3810756207	Jul 18 07:04:07 PM PDT 24	Jul 18 07:04:17 PM PDT 24	27908272 ps
T227	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3899806142	Jul 18 07:03:16 PM PDT 24	Jul 18 07:09:40 PM PDT 24	53066278541 ps
T228	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.619155340	Jul 18 07:03:46 PM PDT 24	Jul 18 07:08:20 PM PDT 24	14268865682 ps
T229	/workspace/coverage/default/25.sram_ctrl_bijection.1609299295	Jul 18 07:05:03 PM PDT 24	Jul 18 07:06:28 PM PDT 24	4792144189 ps
T230	/workspace/coverage/default/15.sram_ctrl_lc_escalation.3910623346	Jul 18 07:04:12 PM PDT 24	Jul 18 07:04:25 PM PDT 24	940053633 ps
T231	/workspace/coverage/default/11.sram_ctrl_alert_test.2765445108	Jul 18 07:03:58 PM PDT 24	Jul 18 07:04:06 PM PDT 24	18857516 ps
T232	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3330363656	Jul 18 07:06:16 PM PDT 24	Jul 18 07:07:33 PM PDT 24	921569171 ps
T233	/workspace/coverage/default/29.sram_ctrl_executable.3605572050	Jul 18 07:05:16 PM PDT 24	Jul 18 07:20:28 PM PDT 24	13021533842 ps
T234	/workspace/coverage/default/11.sram_ctrl_max_throughput.1394793776	Jul 18 07:04:02 PM PDT 24	Jul 18 07:04:25 PM PDT 24	137453864 ps
T235	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4025050395	Jul 18 07:10:15 PM PDT 24	Jul 18 07:17:24 PM PDT 24	1415663577 ps
T236	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3255115541	Jul 18 07:10:15 PM PDT 24	Jul 18 07:10:22 PM PDT 24	44428770 ps
T237	/workspace/coverage/default/32.sram_ctrl_ram_cfg.821045317	Jul 18 07:05:48 PM PDT 24	Jul 18 07:05:51 PM PDT 24	33955844 ps
T238	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2269849319	Jul 18 07:03:55 PM PDT 24	Jul 18 07:10:38 PM PDT 24	9757000659 ps
T239	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.885719412	Jul 18 07:09:17 PM PDT 24	Jul 18 07:26:03 PM PDT 24	2647346400 ps
T240	/workspace/coverage/default/32.sram_ctrl_lc_escalation.1695503526	Jul 18 07:05:37 PM PDT 24	Jul 18 07:05:51 PM PDT 24	7112494048 ps
T241	/workspace/coverage/default/16.sram_ctrl_ram_cfg.3398045600	Jul 18 07:04:10 PM PDT 24	Jul 18 07:04:20 PM PDT 24	98761851 ps
T242	/workspace/coverage/default/26.sram_ctrl_multiple_keys.2338188986	Jul 18 07:05:03 PM PDT 24	Jul 18 07:19:00 PM PDT 24	3586362173 ps
T243	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3096465336	Jul 18 07:05:19 PM PDT 24	Jul 18 07:11:22 PM PDT 24	9530122922 ps
T244	/workspace/coverage/default/22.sram_ctrl_regwen.1569232270	Jul 18 07:04:45 PM PDT 24	Jul 18 07:15:55 PM PDT 24	6099028107 ps
T245	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2873881051	Jul 18 07:06:18 PM PDT 24	Jul 18 07:12:48 PM PDT 24	4164771653 ps
T246	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3840097341	Jul 18 07:03:57 PM PDT 24	Jul 18 07:09:13 PM PDT 24	11848242000 ps
T247	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2135368185	Jul 18 07:05:21 PM PDT 24	Jul 18 07:05:43 PM PDT 24	952274958 ps
T248	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2565962016	Jul 18 07:04:11 PM PDT 24	Jul 18 07:05:50 PM PDT 24	4265199300 ps
T249	/workspace/coverage/default/16.sram_ctrl_partial_access.3588072312	Jul 18 07:04:11 PM PDT 24	Jul 18 07:05:06 PM PDT 24	1904137920 ps
T250	/workspace/coverage/default/1.sram_ctrl_stress_all.1299362438	Jul 18 07:03:25 PM PDT 24	Jul 18 07:34:36 PM PDT 24	130906782413 ps
T251	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1892371446	Jul 18 07:05:30 PM PDT 24	Jul 18 07:05:39 PM PDT 24	1726281048 ps
T252	/workspace/coverage/default/33.sram_ctrl_alert_test.88755523	Jul 18 07:05:45 PM PDT 24	Jul 18 07:05:46 PM PDT 24	38711116 ps
T253	/workspace/coverage/default/36.sram_ctrl_bijection.4185613220	Jul 18 07:06:15 PM PDT 24	Jul 18 07:07:26 PM PDT 24	15547699513 ps
T254	/workspace/coverage/default/33.sram_ctrl_executable.117341938	Jul 18 07:05:46 PM PDT 24	Jul 18 07:13:06 PM PDT 24	17838148144 ps
T255	/workspace/coverage/default/47.sram_ctrl_smoke.197812609	Jul 18 07:09:17 PM PDT 24	Jul 18 07:09:28 PM PDT 24	1193996321 ps
T256	/workspace/coverage/default/41.sram_ctrl_ram_cfg.3679716394	Jul 18 07:07:15 PM PDT 24	Jul 18 07:07:18 PM PDT 24	76240938 ps
T257	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3801100083	Jul 18 07:03:41 PM PDT 24	Jul 18 07:07:15 PM PDT 24	4609219423 ps
T258	/workspace/coverage/default/8.sram_ctrl_max_throughput.2381503142	Jul 18 07:03:44 PM PDT 24	Jul 18 07:03:55 PM PDT 24	86694942 ps
T259	/workspace/coverage/default/5.sram_ctrl_max_throughput.2705374993	Jul 18 07:03:32 PM PDT 24	Jul 18 07:03:44 PM PDT 24	194458681 ps
T260	/workspace/coverage/default/14.sram_ctrl_bijection.2635103677	Jul 18 07:04:05 PM PDT 24	Jul 18 07:05:30 PM PDT 24	5438117659 ps
T261	/workspace/coverage/default/3.sram_ctrl_ram_cfg.222773211	Jul 18 07:03:26 PM PDT 24	Jul 18 07:03:37 PM PDT 24	48427642 ps
T262	/workspace/coverage/default/12.sram_ctrl_alert_test.2160596301	Jul 18 07:03:59 PM PDT 24	Jul 18 07:04:08 PM PDT 24	43871844 ps
T263	/workspace/coverage/default/32.sram_ctrl_stress_all.2792600028	Jul 18 07:05:47 PM PDT 24	Jul 18 07:22:32 PM PDT 24	17184797724 ps
T264	/workspace/coverage/default/9.sram_ctrl_mem_walk.374811573	Jul 18 07:03:46 PM PDT 24	Jul 18 07:04:03 PM PDT 24	184300136 ps
T265	/workspace/coverage/default/24.sram_ctrl_lc_escalation.554978083	Jul 18 07:05:02 PM PDT 24	Jul 18 07:05:07 PM PDT 24	151952683 ps
T266	/workspace/coverage/default/6.sram_ctrl_smoke.1378401893	Jul 18 07:03:41 PM PDT 24	Jul 18 07:03:52 PM PDT 24	401365102 ps
T267	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3456768198	Jul 18 07:05:30 PM PDT 24	Jul 18 07:06:18 PM PDT 24	424163095 ps
T268	/workspace/coverage/default/8.sram_ctrl_executable.2969019637	Jul 18 07:03:43 PM PDT 24	Jul 18 07:17:49 PM PDT 24	6527694740 ps
T269	/workspace/coverage/default/2.sram_ctrl_alert_test.3525580912	Jul 18 07:03:29 PM PDT 24	Jul 18 07:03:41 PM PDT 24	39758305 ps
T270	/workspace/coverage/default/35.sram_ctrl_max_throughput.835515078	Jul 18 07:06:06 PM PDT 24	Jul 18 07:09:06 PM PDT 24	138314454 ps
T271	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.191653805	Jul 18 07:03:55 PM PDT 24	Jul 18 07:07:26 PM PDT 24	2100207172 ps
T272	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1234845520	Jul 18 07:04:22 PM PDT 24	Jul 18 07:04:31 PM PDT 24	592682497 ps
T273	/workspace/coverage/default/41.sram_ctrl_executable.3799773458	Jul 18 07:07:23 PM PDT 24	Jul 18 07:29:09 PM PDT 24	18023224904 ps
T274	/workspace/coverage/default/17.sram_ctrl_bijection.4152924983	Jul 18 07:04:13 PM PDT 24	Jul 18 07:04:51 PM PDT 24	3483525850 ps
T275	/workspace/coverage/default/3.sram_ctrl_max_throughput.2308634064	Jul 18 07:03:27 PM PDT 24	Jul 18 07:03:41 PM PDT 24	173994773 ps
T276	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1350718716	Jul 18 07:04:45 PM PDT 24	Jul 18 07:20:29 PM PDT 24	2830255641 ps
T277	/workspace/coverage/default/19.sram_ctrl_executable.827185009	Jul 18 07:04:13 PM PDT 24	Jul 18 07:17:31 PM PDT 24	31628265734 ps
T278	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1742031119	Jul 18 07:07:18 PM PDT 24	Jul 18 07:14:22 PM PDT 24	6331259382 ps
T279	/workspace/coverage/default/41.sram_ctrl_regwen.2406797574	Jul 18 07:07:23 PM PDT 24	Jul 18 07:25:02 PM PDT 24	102015344142 ps
T280	/workspace/coverage/default/41.sram_ctrl_max_throughput.668187083	Jul 18 07:07:15 PM PDT 24	Jul 18 07:07:50 PM PDT 24	178354287 ps
T281	/workspace/coverage/default/24.sram_ctrl_stress_all.3640454554	Jul 18 07:05:00 PM PDT 24	Jul 18 07:40:23 PM PDT 24	156727824193 ps
T282	/workspace/coverage/default/22.sram_ctrl_bijection.513648792	Jul 18 07:04:45 PM PDT 24	Jul 18 07:05:07 PM PDT 24	322356026 ps
T283	/workspace/coverage/default/2.sram_ctrl_stress_all.2205392800	Jul 18 07:03:23 PM PDT 24	Jul 18 07:51:16 PM PDT 24	9497833896 ps
T284	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3724495581	Jul 18 07:05:16 PM PDT 24	Jul 18 07:05:47 PM PDT 24	232642392 ps
T285	/workspace/coverage/default/26.sram_ctrl_stress_all.906670874	Jul 18 07:05:07 PM PDT 24	Jul 18 07:30:47 PM PDT 24	12686583280 ps
T286	/workspace/coverage/default/48.sram_ctrl_ram_cfg.624507444	Jul 18 07:10:14 PM PDT 24	Jul 18 07:10:16 PM PDT 24	27006829 ps
T287	/workspace/coverage/default/23.sram_ctrl_executable.142659124	Jul 18 07:04:43 PM PDT 24	Jul 18 07:14:10 PM PDT 24	19963083121 ps
T288	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4085641310	Jul 18 07:04:06 PM PDT 24	Jul 18 07:04:19 PM PDT 24	131922295 ps
T289	/workspace/coverage/default/38.sram_ctrl_max_throughput.3140130231	Jul 18 07:06:21 PM PDT 24	Jul 18 07:06:24 PM PDT 24	81393547 ps
T290	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1251557719	Jul 18 07:05:16 PM PDT 24	Jul 18 07:07:49 PM PDT 24	352525945 ps
T291	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.211473543	Jul 18 07:06:03 PM PDT 24	Jul 18 07:07:33 PM PDT 24	189228605 ps
T292	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1318129061	Jul 18 07:05:03 PM PDT 24	Jul 18 07:05:16 PM PDT 24	583077499 ps
T293	/workspace/coverage/default/16.sram_ctrl_mem_walk.1492036996	Jul 18 07:04:08 PM PDT 24	Jul 18 07:04:26 PM PDT 24	136216173 ps
T294	/workspace/coverage/default/46.sram_ctrl_smoke.188552005	Jul 18 07:09:14 PM PDT 24	Jul 18 07:09:59 PM PDT 24	385505468 ps
T295	/workspace/coverage/default/20.sram_ctrl_lc_escalation.1840969432	Jul 18 07:04:24 PM PDT 24	Jul 18 07:04:32 PM PDT 24	576736125 ps
T296	/workspace/coverage/default/4.sram_ctrl_alert_test.1562843278	Jul 18 07:03:26 PM PDT 24	Jul 18 07:03:37 PM PDT 24	35264995 ps
T297	/workspace/coverage/default/1.sram_ctrl_max_throughput.2963149101	Jul 18 07:03:16 PM PDT 24	Jul 18 07:03:31 PM PDT 24	702894900 ps
T49	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2568416736	Jul 18 07:05:16 PM PDT 24	Jul 18 07:05:32 PM PDT 24	379606503 ps
T298	/workspace/coverage/default/31.sram_ctrl_executable.1413158635	Jul 18 07:05:29 PM PDT 24	Jul 18 07:07:19 PM PDT 24	620349160 ps
T299	/workspace/coverage/default/37.sram_ctrl_ram_cfg.2758137019	Jul 18 07:06:18 PM PDT 24	Jul 18 07:06:21 PM PDT 24	28731708 ps