| T792 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1942964904 |
|
|
Jul 18 07:03:58 PM PDT 24 |
Jul 18 07:04:06 PM PDT 24 |
101521494 ps |
| T793 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1151416360 |
|
|
Jul 18 07:04:47 PM PDT 24 |
Jul 18 07:07:43 PM PDT 24 |
1216224771 ps |
| T794 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1692657704 |
|
|
Jul 18 07:03:56 PM PDT 24 |
Jul 18 07:04:08 PM PDT 24 |
174978371 ps |
| T795 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1210664855 |
|
|
Jul 18 07:06:02 PM PDT 24 |
Jul 18 07:12:23 PM PDT 24 |
4684949046 ps |
| T796 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1778898817 |
|
|
Jul 18 07:06:02 PM PDT 24 |
Jul 18 07:06:06 PM PDT 24 |
38810272 ps |
| T797 |
/workspace/coverage/default/32.sram_ctrl_regwen.43809184 |
|
|
Jul 18 07:05:47 PM PDT 24 |
Jul 18 07:25:07 PM PDT 24 |
53865920245 ps |
| T798 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1589525476 |
|
|
Jul 18 07:07:18 PM PDT 24 |
Jul 18 07:07:28 PM PDT 24 |
1324356261 ps |
| T799 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1274741276 |
|
|
Jul 18 07:04:09 PM PDT 24 |
Jul 18 07:04:30 PM PDT 24 |
769385973 ps |
| T800 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2068492803 |
|
|
Jul 18 07:05:47 PM PDT 24 |
Jul 18 07:05:51 PM PDT 24 |
30225768 ps |
| T801 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3684086410 |
|
|
Jul 18 07:04:45 PM PDT 24 |
Jul 18 07:04:48 PM PDT 24 |
67292999 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_bijection.1431965829 |
|
|
Jul 18 07:03:43 PM PDT 24 |
Jul 18 07:04:31 PM PDT 24 |
1843732741 ps |
| T803 |
/workspace/coverage/default/49.sram_ctrl_smoke.344241443 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 07:12:11 PM PDT 24 |
2058727494 ps |
| T117 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2310018732 |
|
|
Jul 18 07:06:00 PM PDT 24 |
Jul 18 07:09:15 PM PDT 24 |
7713450702 ps |
| T804 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.4273164667 |
|
|
Jul 18 07:07:18 PM PDT 24 |
Jul 18 07:17:46 PM PDT 24 |
3906003045 ps |
| T805 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1316593824 |
|
|
Jul 18 07:07:17 PM PDT 24 |
Jul 18 07:07:32 PM PDT 24 |
3356547043 ps |
| T806 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2439001517 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 08:27:24 PM PDT 24 |
58376313619 ps |
| T807 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1727907015 |
|
|
Jul 18 07:03:57 PM PDT 24 |
Jul 18 07:04:04 PM PDT 24 |
32378537 ps |
| T808 |
/workspace/coverage/default/36.sram_ctrl_regwen.3558477199 |
|
|
Jul 18 07:06:16 PM PDT 24 |
Jul 18 07:10:03 PM PDT 24 |
1386599608 ps |
| T809 |
/workspace/coverage/default/43.sram_ctrl_executable.3983143469 |
|
|
Jul 18 07:07:22 PM PDT 24 |
Jul 18 07:20:20 PM PDT 24 |
5559201175 ps |
| T810 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1919066073 |
|
|
Jul 18 07:03:43 PM PDT 24 |
Jul 18 07:11:03 PM PDT 24 |
9861362752 ps |
| T811 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1653974895 |
|
|
Jul 18 07:04:13 PM PDT 24 |
Jul 18 07:11:17 PM PDT 24 |
90368681392 ps |
| T812 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.222524425 |
|
|
Jul 18 07:05:33 PM PDT 24 |
Jul 18 07:05:43 PM PDT 24 |
3130424228 ps |
| T813 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3224237686 |
|
|
Jul 18 07:03:42 PM PDT 24 |
Jul 18 07:03:50 PM PDT 24 |
27108047 ps |
| T814 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.719727172 |
|
|
Jul 18 07:05:19 PM PDT 24 |
Jul 18 07:06:50 PM PDT 24 |
4734608194 ps |
| T815 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4079249825 |
|
|
Jul 18 07:03:21 PM PDT 24 |
Jul 18 07:04:18 PM PDT 24 |
583702537 ps |
| T816 |
/workspace/coverage/default/18.sram_ctrl_regwen.491979128 |
|
|
Jul 18 07:04:17 PM PDT 24 |
Jul 18 07:06:36 PM PDT 24 |
513811902 ps |
| T817 |
/workspace/coverage/default/49.sram_ctrl_bijection.531710633 |
|
|
Jul 18 07:10:14 PM PDT 24 |
Jul 18 07:11:30 PM PDT 24 |
4175826838 ps |
| T818 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1672537627 |
|
|
Jul 18 07:06:01 PM PDT 24 |
Jul 18 07:11:56 PM PDT 24 |
3638934434 ps |
| T819 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.92545556 |
|
|
Jul 18 07:06:31 PM PDT 24 |
Jul 18 07:06:36 PM PDT 24 |
57013642 ps |
| T820 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1613876191 |
|
|
Jul 18 07:04:23 PM PDT 24 |
Jul 18 07:04:33 PM PDT 24 |
300581064 ps |
| T821 |
/workspace/coverage/default/45.sram_ctrl_regwen.2551668967 |
|
|
Jul 18 07:09:18 PM PDT 24 |
Jul 18 07:23:28 PM PDT 24 |
49346012652 ps |
| T822 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.599355225 |
|
|
Jul 18 07:10:19 PM PDT 24 |
Jul 18 07:11:44 PM PDT 24 |
4338857494 ps |
| T823 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.788138955 |
|
|
Jul 18 07:05:48 PM PDT 24 |
Jul 18 07:05:53 PM PDT 24 |
89172167 ps |
| T824 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.1834858792 |
|
|
Jul 18 07:04:14 PM PDT 24 |
Jul 18 07:04:36 PM PDT 24 |
146816934 ps |
| T825 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3084665841 |
|
|
Jul 18 07:03:44 PM PDT 24 |
Jul 18 07:03:53 PM PDT 24 |
78301642 ps |
| T826 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3214094101 |
|
|
Jul 18 07:04:02 PM PDT 24 |
Jul 18 07:06:29 PM PDT 24 |
4429008026 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1461810924 |
|
|
Jul 18 07:06:19 PM PDT 24 |
Jul 18 07:06:21 PM PDT 24 |
14258498 ps |
| T828 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2611927315 |
|
|
Jul 18 07:05:02 PM PDT 24 |
Jul 18 07:05:06 PM PDT 24 |
72262648 ps |
| T829 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3099895535 |
|
|
Jul 18 07:09:20 PM PDT 24 |
Jul 18 07:19:47 PM PDT 24 |
26797014107 ps |
| T830 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2469441598 |
|
|
Jul 18 07:05:19 PM PDT 24 |
Jul 18 07:05:31 PM PDT 24 |
359913911 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_stress_all.4052313989 |
|
|
Jul 18 07:04:18 PM PDT 24 |
Jul 18 07:40:41 PM PDT 24 |
8123637500 ps |
| T832 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2847354063 |
|
|
Jul 18 07:06:14 PM PDT 24 |
Jul 18 07:10:45 PM PDT 24 |
1401714620 ps |
| T833 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3606736232 |
|
|
Jul 18 07:07:21 PM PDT 24 |
Jul 18 07:11:31 PM PDT 24 |
15324552190 ps |
| T834 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1149279333 |
|
|
Jul 18 07:03:54 PM PDT 24 |
Jul 18 07:13:22 PM PDT 24 |
90245862594 ps |
| T835 |
/workspace/coverage/default/31.sram_ctrl_partial_access.502321075 |
|
|
Jul 18 07:05:29 PM PDT 24 |
Jul 18 07:07:00 PM PDT 24 |
2313028058 ps |
| T836 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3855414937 |
|
|
Jul 18 07:03:48 PM PDT 24 |
Jul 18 07:37:02 PM PDT 24 |
84627850824 ps |
| T837 |
/workspace/coverage/default/12.sram_ctrl_bijection.3126283916 |
|
|
Jul 18 07:03:57 PM PDT 24 |
Jul 18 07:05:25 PM PDT 24 |
3625444167 ps |
| T838 |
/workspace/coverage/default/42.sram_ctrl_executable.1015617859 |
|
|
Jul 18 07:07:20 PM PDT 24 |
Jul 18 07:33:10 PM PDT 24 |
5711085572 ps |
| T839 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.707366788 |
|
|
Jul 18 07:03:58 PM PDT 24 |
Jul 18 07:05:12 PM PDT 24 |
450002250 ps |
| T840 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1786432882 |
|
|
Jul 18 07:05:02 PM PDT 24 |
Jul 18 07:09:00 PM PDT 24 |
707951880 ps |
| T841 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4081652935 |
|
|
Jul 18 07:03:29 PM PDT 24 |
Jul 18 07:27:07 PM PDT 24 |
42598771377 ps |
| T842 |
/workspace/coverage/default/35.sram_ctrl_smoke.3384562207 |
|
|
Jul 18 07:06:04 PM PDT 24 |
Jul 18 07:06:21 PM PDT 24 |
1371367661 ps |
| T843 |
/workspace/coverage/default/42.sram_ctrl_partial_access.1227622112 |
|
|
Jul 18 07:07:20 PM PDT 24 |
Jul 18 07:07:47 PM PDT 24 |
1149201472 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_regwen.3677071647 |
|
|
Jul 18 07:06:01 PM PDT 24 |
Jul 18 07:26:11 PM PDT 24 |
4480953762 ps |
| T845 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1702880079 |
|
|
Jul 18 07:09:14 PM PDT 24 |
Jul 18 07:32:08 PM PDT 24 |
4774714651 ps |
| T846 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3357199366 |
|
|
Jul 18 07:06:18 PM PDT 24 |
Jul 18 07:36:36 PM PDT 24 |
15619887242 ps |
| T847 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2745493950 |
|
|
Jul 18 07:04:10 PM PDT 24 |
Jul 18 07:09:29 PM PDT 24 |
6677079753 ps |
| T848 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1989951874 |
|
|
Jul 18 07:05:47 PM PDT 24 |
Jul 18 07:09:54 PM PDT 24 |
718147201 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_partial_access.893180401 |
|
|
Jul 18 07:09:14 PM PDT 24 |
Jul 18 07:11:55 PM PDT 24 |
211875583 ps |
| T850 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2507325858 |
|
|
Jul 18 07:05:31 PM PDT 24 |
Jul 18 07:05:35 PM PDT 24 |
13017853 ps |
| T851 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3273343934 |
|
|
Jul 18 07:04:45 PM PDT 24 |
Jul 18 07:10:07 PM PDT 24 |
52153367756 ps |
| T852 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3485050381 |
|
|
Jul 18 07:05:02 PM PDT 24 |
Jul 18 07:06:47 PM PDT 24 |
8567719849 ps |
| T853 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1223230672 |
|
|
Jul 18 07:03:43 PM PDT 24 |
Jul 18 07:05:22 PM PDT 24 |
139869720 ps |
| T854 |
/workspace/coverage/default/8.sram_ctrl_bijection.2161056617 |
|
|
Jul 18 07:03:45 PM PDT 24 |
Jul 18 07:05:14 PM PDT 24 |
4770455435 ps |
| T855 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1062480800 |
|
|
Jul 18 07:07:17 PM PDT 24 |
Jul 18 07:18:03 PM PDT 24 |
113924518433 ps |
| T856 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.239773260 |
|
|
Jul 18 07:05:05 PM PDT 24 |
Jul 18 07:05:15 PM PDT 24 |
472937579 ps |
| T857 |
/workspace/coverage/default/1.sram_ctrl_partial_access.27386186 |
|
|
Jul 18 07:03:16 PM PDT 24 |
Jul 18 07:05:23 PM PDT 24 |
1401343261 ps |
| T858 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.797909777 |
|
|
Jul 18 07:06:02 PM PDT 24 |
Jul 18 07:06:13 PM PDT 24 |
555157209 ps |
| T859 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1530102108 |
|
|
Jul 18 07:07:20 PM PDT 24 |
Jul 18 07:08:11 PM PDT 24 |
462049177 ps |
| T860 |
/workspace/coverage/default/15.sram_ctrl_regwen.3769720624 |
|
|
Jul 18 07:04:10 PM PDT 24 |
Jul 18 07:13:33 PM PDT 24 |
4753510510 ps |
| T861 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2265243404 |
|
|
Jul 18 07:04:22 PM PDT 24 |
Jul 18 07:40:24 PM PDT 24 |
21969555613 ps |
| T862 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2856520890 |
|
|
Jul 18 07:05:01 PM PDT 24 |
Jul 18 07:05:22 PM PDT 24 |
1048185684 ps |
| T863 |
/workspace/coverage/default/6.sram_ctrl_partial_access.545189499 |
|
|
Jul 18 07:03:42 PM PDT 24 |
Jul 18 07:04:01 PM PDT 24 |
424358537 ps |
| T864 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.2690410869 |
|
|
Jul 18 07:09:15 PM PDT 24 |
Jul 18 07:09:25 PM PDT 24 |
896283678 ps |
| T865 |
/workspace/coverage/default/22.sram_ctrl_stress_all.2755594416 |
|
|
Jul 18 07:04:45 PM PDT 24 |
Jul 18 08:09:55 PM PDT 24 |
181750706482 ps |
| T866 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1045803313 |
|
|
Jul 18 07:05:15 PM PDT 24 |
Jul 18 07:07:18 PM PDT 24 |
507445310 ps |
| T867 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1272841328 |
|
|
Jul 18 07:03:41 PM PDT 24 |
Jul 18 08:32:47 PM PDT 24 |
81521520844 ps |
| T868 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4262484895 |
|
|
Jul 18 07:07:18 PM PDT 24 |
Jul 18 07:14:40 PM PDT 24 |
11732128491 ps |
| T869 |
/workspace/coverage/default/10.sram_ctrl_alert_test.898799952 |
|
|
Jul 18 07:03:55 PM PDT 24 |
Jul 18 07:04:01 PM PDT 24 |
14815266 ps |
| T870 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2871426428 |
|
|
Jul 18 07:06:17 PM PDT 24 |
Jul 18 07:06:23 PM PDT 24 |
362458962 ps |
| T871 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.3054556795 |
|
|
Jul 18 07:06:04 PM PDT 24 |
Jul 18 07:06:11 PM PDT 24 |
691130427 ps |
| T872 |
/workspace/coverage/default/36.sram_ctrl_smoke.2114392388 |
|
|
Jul 18 07:06:02 PM PDT 24 |
Jul 18 07:06:17 PM PDT 24 |
2114314224 ps |
| T873 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3735423358 |
|
|
Jul 18 07:10:17 PM PDT 24 |
Jul 18 07:10:29 PM PDT 24 |
643156279 ps |
| T874 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.129996460 |
|
|
Jul 18 07:03:45 PM PDT 24 |
Jul 18 07:04:01 PM PDT 24 |
142745675 ps |
| T875 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3328952793 |
|
|
Jul 18 07:06:32 PM PDT 24 |
Jul 18 07:06:45 PM PDT 24 |
1171447559 ps |
| T876 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1650302298 |
|
|
Jul 18 07:05:04 PM PDT 24 |
Jul 18 07:06:11 PM PDT 24 |
483185913 ps |
| T877 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2273720736 |
|
|
Jul 18 07:04:44 PM PDT 24 |
Jul 18 07:18:06 PM PDT 24 |
27934691223 ps |
| T878 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2855237946 |
|
|
Jul 18 07:04:42 PM PDT 24 |
Jul 18 08:13:04 PM PDT 24 |
44731280112 ps |
| T879 |
/workspace/coverage/default/3.sram_ctrl_bijection.2672593048 |
|
|
Jul 18 07:03:25 PM PDT 24 |
Jul 18 07:04:33 PM PDT 24 |
3360474209 ps |
| T880 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2023413430 |
|
|
Jul 18 07:09:13 PM PDT 24 |
Jul 18 07:09:19 PM PDT 24 |
116749637 ps |
| T881 |
/workspace/coverage/default/27.sram_ctrl_stress_all.801532135 |
|
|
Jul 18 07:05:20 PM PDT 24 |
Jul 18 08:11:19 PM PDT 24 |
49922873775 ps |
| T882 |
/workspace/coverage/default/8.sram_ctrl_regwen.3316575372 |
|
|
Jul 18 07:03:49 PM PDT 24 |
Jul 18 07:14:13 PM PDT 24 |
31668059398 ps |
| T883 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.4248986784 |
|
|
Jul 18 07:06:03 PM PDT 24 |
Jul 18 07:06:12 PM PDT 24 |
345202173 ps |
| T884 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.4138030252 |
|
|
Jul 18 07:04:19 PM PDT 24 |
Jul 18 07:04:31 PM PDT 24 |
2004765813 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_executable.529665433 |
|
|
Jul 18 07:04:10 PM PDT 24 |
Jul 18 07:26:31 PM PDT 24 |
116520821438 ps |
| T886 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3995206320 |
|
|
Jul 18 07:04:22 PM PDT 24 |
Jul 18 07:12:34 PM PDT 24 |
3249388908 ps |
| T887 |
/workspace/coverage/default/38.sram_ctrl_alert_test.817712243 |
|
|
Jul 18 07:06:39 PM PDT 24 |
Jul 18 07:06:41 PM PDT 24 |
30820908 ps |
| T888 |
/workspace/coverage/default/23.sram_ctrl_regwen.1981502665 |
|
|
Jul 18 07:04:44 PM PDT 24 |
Jul 18 07:23:53 PM PDT 24 |
11774868660 ps |
| T889 |
/workspace/coverage/default/43.sram_ctrl_alert_test.674297883 |
|
|
Jul 18 07:07:18 PM PDT 24 |
Jul 18 07:07:22 PM PDT 24 |
21168567 ps |
| T890 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3120654303 |
|
|
Jul 18 07:03:27 PM PDT 24 |
Jul 18 07:03:39 PM PDT 24 |
123914865 ps |
| T891 |
/workspace/coverage/default/7.sram_ctrl_alert_test.862584719 |
|
|
Jul 18 07:03:41 PM PDT 24 |
Jul 18 07:03:50 PM PDT 24 |
16787154 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.615110440 |
|
|
Jul 18 07:05:19 PM PDT 24 |
Jul 18 07:21:08 PM PDT 24 |
11598216603 ps |
| T893 |
/workspace/coverage/default/29.sram_ctrl_partial_access.4237742651 |
|
|
Jul 18 07:05:19 PM PDT 24 |
Jul 18 07:06:31 PM PDT 24 |
461126983 ps |
| T894 |
/workspace/coverage/default/1.sram_ctrl_bijection.2870638353 |
|
|
Jul 18 07:03:17 PM PDT 24 |
Jul 18 07:04:39 PM PDT 24 |
9471787498 ps |
| T895 |
/workspace/coverage/default/40.sram_ctrl_bijection.469312849 |
|
|
Jul 18 07:06:31 PM PDT 24 |
Jul 18 07:07:55 PM PDT 24 |
17612957341 ps |
| T896 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1841520454 |
|
|
Jul 18 07:10:14 PM PDT 24 |
Jul 18 07:10:40 PM PDT 24 |
271442126 ps |
| T897 |
/workspace/coverage/default/16.sram_ctrl_smoke.1138821197 |
|
|
Jul 18 07:04:12 PM PDT 24 |
Jul 18 07:04:39 PM PDT 24 |
8998639790 ps |
| T898 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1535190662 |
|
|
Jul 18 07:03:25 PM PDT 24 |
Jul 18 07:07:01 PM PDT 24 |
2163227126 ps |
| T899 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.438206760 |
|
|
Jul 18 07:04:46 PM PDT 24 |
Jul 18 07:09:58 PM PDT 24 |
5275059675 ps |
| T900 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.997183620 |
|
|
Jul 18 07:07:21 PM PDT 24 |
Jul 18 07:07:34 PM PDT 24 |
443730443 ps |
| T901 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2610038691 |
|
|
Jul 18 07:07:20 PM PDT 24 |
Jul 18 07:07:32 PM PDT 24 |
165525979 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_smoke.3179090219 |
|
|
Jul 18 07:04:45 PM PDT 24 |
Jul 18 07:04:49 PM PDT 24 |
81800373 ps |
| T903 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1998909658 |
|
|
Jul 18 07:06:39 PM PDT 24 |
Jul 18 07:06:41 PM PDT 24 |
41019531 ps |
| T904 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2932061840 |
|
|
Jul 18 07:04:12 PM PDT 24 |
Jul 18 07:04:30 PM PDT 24 |
60398766 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.4061760845 |
|
|
Jul 18 07:05:34 PM PDT 24 |
Jul 18 07:05:37 PM PDT 24 |
48524529 ps |
| T906 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3117901448 |
|
|
Jul 18 07:05:14 PM PDT 24 |
Jul 18 07:05:24 PM PDT 24 |
331576434 ps |
| T907 |
/workspace/coverage/default/20.sram_ctrl_bijection.1696486870 |
|
|
Jul 18 07:04:20 PM PDT 24 |
Jul 18 07:05:39 PM PDT 24 |
4547866849 ps |
| T908 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.720291444 |
|
|
Jul 18 07:03:41 PM PDT 24 |
Jul 18 07:10:37 PM PDT 24 |
4235230028 ps |
| T909 |
/workspace/coverage/default/21.sram_ctrl_stress_all.2656776463 |
|
|
Jul 18 07:04:44 PM PDT 24 |
Jul 18 07:55:38 PM PDT 24 |
244219599948 ps |
| T910 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.135228287 |
|
|
Jul 18 07:03:50 PM PDT 24 |
Jul 18 07:04:01 PM PDT 24 |
133762593 ps |
| T911 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.488539493 |
|
|
Jul 18 07:05:16 PM PDT 24 |
Jul 18 07:05:22 PM PDT 24 |
321734184 ps |
| T912 |
/workspace/coverage/default/9.sram_ctrl_regwen.1001457178 |
|
|
Jul 18 07:03:48 PM PDT 24 |
Jul 18 07:15:57 PM PDT 24 |
7184644073 ps |
| T913 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3611024096 |
|
|
Jul 18 07:06:15 PM PDT 24 |
Jul 18 07:06:22 PM PDT 24 |
96716527 ps |
| T914 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1890204080 |
|
|
Jul 18 07:04:09 PM PDT 24 |
Jul 18 07:04:24 PM PDT 24 |
495752260 ps |
| T915 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.4022609769 |
|
|
Jul 18 07:04:26 PM PDT 24 |
Jul 18 07:04:36 PM PDT 24 |
3692383115 ps |
| T916 |
/workspace/coverage/default/7.sram_ctrl_executable.4263295041 |
|
|
Jul 18 07:03:39 PM PDT 24 |
Jul 18 07:29:04 PM PDT 24 |
8646062952 ps |
| T917 |
/workspace/coverage/default/0.sram_ctrl_smoke.748345999 |
|
|
Jul 18 07:03:18 PM PDT 24 |
Jul 18 07:03:37 PM PDT 24 |
158537239 ps |
| T918 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2474856751 |
|
|
Jul 18 07:09:15 PM PDT 24 |
Jul 18 07:26:27 PM PDT 24 |
6470925411 ps |
| T919 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2305179508 |
|
|
Jul 18 07:05:14 PM PDT 24 |
Jul 18 07:05:23 PM PDT 24 |
1172930903 ps |
| T920 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3028075095 |
|
|
Jul 18 07:03:29 PM PDT 24 |
Jul 18 07:31:40 PM PDT 24 |
29240158140 ps |
| T921 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2177466047 |
|
|
Jul 18 07:05:47 PM PDT 24 |
Jul 18 07:06:02 PM PDT 24 |
78017866 ps |
| T922 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2103639210 |
|
|
Jul 18 07:03:27 PM PDT 24 |
Jul 18 07:28:31 PM PDT 24 |
3953174738 ps |
| T923 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1952733980 |
|
|
Jul 18 07:03:59 PM PDT 24 |
Jul 18 07:04:12 PM PDT 24 |
64783153 ps |
| T924 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3562202699 |
|
|
Jul 18 07:06:36 PM PDT 24 |
Jul 18 07:07:22 PM PDT 24 |
1273300312 ps |
| T925 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2499020462 |
|
|
Jul 18 07:06:01 PM PDT 24 |
Jul 18 07:11:38 PM PDT 24 |
3377139197 ps |
| T926 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.564694734 |
|
|
Jul 18 07:04:11 PM PDT 24 |
Jul 18 07:04:59 PM PDT 24 |
436985879 ps |
| T927 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2031940724 |
|
|
Jul 18 07:03:59 PM PDT 24 |
Jul 18 07:17:11 PM PDT 24 |
30743286500 ps |
| T928 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3019132061 |
|
|
Jul 18 07:09:16 PM PDT 24 |
Jul 18 07:09:36 PM PDT 24 |
108685607 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3783816180 |
|
|
Jul 18 07:06:32 PM PDT 24 |
Jul 18 07:13:54 PM PDT 24 |
12043720285 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2455937527 |
|
|
Jul 18 06:58:20 PM PDT 24 |
Jul 18 06:58:27 PM PDT 24 |
1634537436 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3729468567 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:30 PM PDT 24 |
3570097230 ps |
| T930 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1165421113 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
200654188 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.439455944 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:29 PM PDT 24 |
867203416 ps |
| T931 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3019150806 |
|
|
Jul 18 06:58:27 PM PDT 24 |
Jul 18 06:58:37 PM PDT 24 |
408363987 ps |
| T81 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3353404159 |
|
|
Jul 18 06:58:20 PM PDT 24 |
Jul 18 06:58:26 PM PDT 24 |
1869589326 ps |
| T932 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4242847952 |
|
|
Jul 18 06:58:36 PM PDT 24 |
Jul 18 06:58:44 PM PDT 24 |
51832206 ps |
| T110 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1958360528 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
88604832 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.610063113 |
|
|
Jul 18 06:58:11 PM PDT 24 |
Jul 18 06:58:18 PM PDT 24 |
401873160 ps |
| T104 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.365033978 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
17041888 ps |
| T933 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2863999115 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
841008221 ps |
| T111 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.20792458 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:45 PM PDT 24 |
15392369 ps |
| T934 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1312208550 |
|
|
Jul 18 06:58:26 PM PDT 24 |
Jul 18 06:58:38 PM PDT 24 |
28446076 ps |
| T62 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.204450114 |
|
|
Jul 18 06:58:22 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
160785299 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4138879150 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
343316445 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4072831647 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
22790486 ps |
| T124 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2154111590 |
|
|
Jul 18 06:58:27 PM PDT 24 |
Jul 18 06:58:38 PM PDT 24 |
594803915 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2818050036 |
|
|
Jul 18 06:58:12 PM PDT 24 |
Jul 18 06:58:17 PM PDT 24 |
25593787 ps |
| T113 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.667402487 |
|
|
Jul 18 06:58:26 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
37973110 ps |
| T935 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3496650137 |
|
|
Jul 18 06:58:28 PM PDT 24 |
Jul 18 06:58:40 PM PDT 24 |
268831980 ps |
| T83 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1682819051 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
217834653 ps |
| T936 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1126836708 |
|
|
Jul 18 06:58:22 PM PDT 24 |
Jul 18 06:58:29 PM PDT 24 |
26935286 ps |
| T937 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.448556203 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
45709549 ps |
| T938 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1031298871 |
|
|
Jul 18 06:58:36 PM PDT 24 |
Jul 18 06:58:45 PM PDT 24 |
80546724 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3701580833 |
|
|
Jul 18 06:58:22 PM PDT 24 |
Jul 18 06:58:29 PM PDT 24 |
18380600 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1465225871 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
21308145 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3225330597 |
|
|
Jul 18 06:58:20 PM PDT 24 |
Jul 18 06:58:25 PM PDT 24 |
325065544 ps |
| T105 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1547818330 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:27 PM PDT 24 |
37276498 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2182571856 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
754453351 ps |
| T941 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4076358158 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
106947694 ps |
| T86 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1800268758 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:27 PM PDT 24 |
15240988 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1176506877 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:27 PM PDT 24 |
38243593 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.441508599 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:31 PM PDT 24 |
23332427 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2461523887 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
34956403 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3745016737 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
24938631 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3854640348 |
|
|
Jul 18 06:58:22 PM PDT 24 |
Jul 18 06:58:30 PM PDT 24 |
45785163 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1312098702 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
22175511 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4202474823 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
454561951 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3890167248 |
|
|
Jul 18 06:58:11 PM PDT 24 |
Jul 18 06:58:17 PM PDT 24 |
20843604 ps |
| T948 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.636986836 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
1519423246 ps |
| T89 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2623656309 |
|
|
Jul 18 06:58:12 PM PDT 24 |
Jul 18 06:58:17 PM PDT 24 |
12825136 ps |
| T949 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1959760058 |
|
|
Jul 18 06:58:29 PM PDT 24 |
Jul 18 06:58:37 PM PDT 24 |
18786432 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2070746797 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
117374795 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.807832499 |
|
|
Jul 18 06:58:27 PM PDT 24 |
Jul 18 06:58:38 PM PDT 24 |
335598404 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2313160904 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
137246662 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3810492355 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:45 PM PDT 24 |
32689165 ps |
| T953 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.540103235 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:37 PM PDT 24 |
137457981 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2887934961 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
115088890 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3322814611 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
422126524 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1277871726 |
|
|
Jul 18 06:58:12 PM PDT 24 |
Jul 18 06:58:19 PM PDT 24 |
927804698 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1433347816 |
|
|
Jul 18 06:58:26 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
19593474 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2596784011 |
|
|
Jul 18 06:58:26 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
123563215 ps |
| T98 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2393684 |
|
|
Jul 18 06:58:36 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
811117212 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2935582902 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:50 PM PDT 24 |
766675290 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2687111840 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
136018595 ps |
| T958 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3869387095 |
|
|
Jul 18 06:58:27 PM PDT 24 |
Jul 18 06:58:37 PM PDT 24 |
199439246 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3369636539 |
|
|
Jul 18 06:58:36 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
187813487 ps |
| T960 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2077592771 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
502446517 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1070557338 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
33998899 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1380682988 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:45 PM PDT 24 |
122184608 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3395042338 |
|
|
Jul 18 06:58:03 PM PDT 24 |
Jul 18 06:58:11 PM PDT 24 |
123277951 ps |
| T964 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.372854267 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:51 PM PDT 24 |
419338890 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3968727378 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
80854047 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2739599118 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
54786360 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2223321593 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:27 PM PDT 24 |
53170159 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1302209340 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
25388182 ps |
| T99 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1688293256 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:30 PM PDT 24 |
184562982 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1037701151 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
122269881 ps |
| T100 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1035453273 |
|
|
Jul 18 06:58:20 PM PDT 24 |
Jul 18 06:58:27 PM PDT 24 |
458122205 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2533037795 |
|
|
Jul 18 06:58:02 PM PDT 24 |
Jul 18 06:58:08 PM PDT 24 |
69949052 ps |
| T134 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1758718641 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
879059609 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.403578725 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
140190644 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.170479237 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
15084776 ps |
| T972 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.985827746 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:45 PM PDT 24 |
23318205 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.445576049 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
64477908 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3337866649 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
99094878 ps |
| T975 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3293424552 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:50 PM PDT 24 |
125615699 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2506522892 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
41096965 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1102510569 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
124526936 ps |
| T103 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4133025301 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:38 PM PDT 24 |
2777783422 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3685705992 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:26 PM PDT 24 |
45453637 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.545962935 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
47761232 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3270729553 |
|
|
Jul 18 06:58:12 PM PDT 24 |
Jul 18 06:58:20 PM PDT 24 |
79920063 ps |
| T127 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2036123153 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
1070372065 ps |
| T981 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2173125830 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
64926065 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2569472770 |
|
|
Jul 18 06:58:27 PM PDT 24 |
Jul 18 06:58:38 PM PDT 24 |
27779564 ps |
| T983 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3239578757 |
|
|
Jul 18 06:58:28 PM PDT 24 |
Jul 18 06:58:40 PM PDT 24 |
132264326 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.948446859 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:32 PM PDT 24 |
28603580 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2114212849 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:30 PM PDT 24 |
175500725 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.44414564 |
|
|
Jul 18 06:58:35 PM PDT 24 |
Jul 18 06:58:43 PM PDT 24 |
15022902 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3869600217 |
|
|
Jul 18 06:58:35 PM PDT 24 |
Jul 18 06:58:43 PM PDT 24 |
64535355 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2662875282 |
|
|
Jul 18 06:58:21 PM PDT 24 |
Jul 18 06:58:28 PM PDT 24 |
34071576 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2293792969 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
59841526 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2366593420 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:31 PM PDT 24 |
49790796 ps |
| T131 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1541216661 |
|
|
Jul 18 06:58:23 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
1384040581 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3177534393 |
|
|
Jul 18 06:58:18 PM PDT 24 |
Jul 18 06:58:23 PM PDT 24 |
474492806 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3526368511 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
54337259 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3049846109 |
|
|
Jul 18 06:58:29 PM PDT 24 |
Jul 18 06:58:39 PM PDT 24 |
953190394 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3406051679 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
19789135 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3513765505 |
|
|
Jul 18 06:58:02 PM PDT 24 |
Jul 18 06:58:08 PM PDT 24 |
96393443 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3819911119 |
|
|
Jul 18 06:58:36 PM PDT 24 |
Jul 18 06:58:44 PM PDT 24 |
422352695 ps |
| T132 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1896772444 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:52 PM PDT 24 |
132506606 ps |
| T995 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.711628005 |
|
|
Jul 18 06:58:19 PM PDT 24 |
Jul 18 06:58:23 PM PDT 24 |
60405787 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.525574019 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:33 PM PDT 24 |
71875792 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1622611687 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
182053385 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3187957357 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
327748790 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3632580406 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
186981213 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2108999651 |
|
|
Jul 18 06:58:22 PM PDT 24 |
Jul 18 06:58:30 PM PDT 24 |
24924146 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2022854227 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:34 PM PDT 24 |
20525802 ps |
| T1002 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1674351388 |
|
|
Jul 18 06:58:24 PM PDT 24 |
Jul 18 06:58:36 PM PDT 24 |
83110534 ps |
| T1003 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3348831925 |
|
|
Jul 18 06:58:25 PM PDT 24 |
Jul 18 06:58:35 PM PDT 24 |
25088789 ps |