Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14211577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59615862

1

T2

8135

T3

85017

T4

104082

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36814481	1			T2	4505		T3	45146		T4	57410
values[0x0]	17086827	1			T2	2218		T3	22106		T4	27375
values[0x1]	19926131	1			T2	2236		T3	22921		T4	29728

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7082980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66744459

1

T2

8558

T3

87543

T4

109339

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	258793	1			T2	31		T3	309		T8	742
valid_sources[0x01]	284907	1			T2	37		T3	283		T8	806
valid_sources[0x02]	349562	1			T2	52		T3	390		T8	757
valid_sources[0x03]	254587	1			T2	25		T3	311		T8	679
valid_sources[0x04]	320600	1			T2	35		T3	453		T8	728
valid_sources[0x05]	265374	1			T2	31		T3	347		T8	799
valid_sources[0x06]	294446	1			T2	33		T3	372		T8	692
valid_sources[0x07]	251143	1			T2	32		T3	395		T8	711
valid_sources[0x08]	309174	1			T2	36		T3	417		T8	788
valid_sources[0x09]	316965	1			T2	38		T3	380		T8	743
valid_sources[0x0a]	242777	1			T2	29		T3	314		T8	785
valid_sources[0x0b]	275840	1			T2	42		T3	380		T8	820
valid_sources[0x0c]	280713	1			T2	35		T3	373		T8	740
valid_sources[0x0d]	276743	1			T2	37		T3	347		T8	790
valid_sources[0x0e]	349083	1			T2	26		T3	349		T8	770
valid_sources[0x0f]	266351	1			T2	37		T3	352		T8	684
valid_sources[0x10]	263333	1			T2	29		T3	268		T8	742
valid_sources[0x11]	258362	1			T2	24		T3	359		T8	654
valid_sources[0x12]	275420	1			T2	46		T3	356		T8	817
valid_sources[0x13]	271209	1			T2	30		T3	373		T8	760
valid_sources[0x14]	291126	1			T2	36		T3	331		T8	789
valid_sources[0x15]	325464	1			T2	28		T3	396		T8	744
valid_sources[0x16]	248289	1			T2	28		T3	343		T8	761
valid_sources[0x17]	278186	1			T2	41		T3	359		T8	718
valid_sources[0x18]	264354	1			T2	38		T3	334		T8	743
valid_sources[0x19]	276835	1			T2	20		T3	405		T8	721
valid_sources[0x1a]	258933	1			T2	31		T3	288		T8	775
valid_sources[0x1b]	315766	1			T2	40		T3	337		T8	722
valid_sources[0x1c]	275374	1			T2	28		T3	361		T8	753
valid_sources[0x1d]	242312	1			T2	35		T3	394		T8	735
valid_sources[0x1e]	275315	1			T2	27		T3	392		T8	678
valid_sources[0x1f]	241820	1			T2	37		T3	384		T8	777
valid_sources[0x20]	254582	1			T2	33		T3	332		T8	668
valid_sources[0x21]	310811	1			T2	32		T3	355		T8	769
valid_sources[0x22]	252334	1			T2	28		T3	402		T8	731
valid_sources[0x23]	265437	1			T2	34		T3	338		T8	760
valid_sources[0x24]	270470	1			T2	33		T3	446		T8	810
valid_sources[0x25]	315156	1			T2	34		T3	385		T8	782
valid_sources[0x26]	267801	1			T2	38		T3	362		T8	744
valid_sources[0x27]	291813	1			T2	25		T3	391		T4	3621
valid_sources[0x28]	307571	1			T2	47		T3	340		T8	791
valid_sources[0x29]	318656	1			T2	32		T3	381		T8	747
valid_sources[0x2a]	352291	1			T2	34		T3	347		T8	711
valid_sources[0x2b]	314978	1			T2	46		T3	381		T8	719
valid_sources[0x2c]	281082	1			T2	34		T3	326		T8	692
valid_sources[0x2d]	291345	1			T2	39		T3	352		T4	9810
valid_sources[0x2e]	268383	1			T2	33		T3	330		T8	779
valid_sources[0x2f]	284058	1			T2	34		T3	333		T8	750
valid_sources[0x30]	294942	1			T2	42		T3	379		T8	653
valid_sources[0x31]	325219	1			T2	43		T3	328		T8	784
valid_sources[0x32]	301140	1			T2	22		T3	360		T8	704
valid_sources[0x33]	275335	1			T2	36		T3	364		T8	770
valid_sources[0x34]	243219	1			T2	24		T3	335		T8	696
valid_sources[0x35]	272489	1			T2	31		T3	418		T8	757
valid_sources[0x36]	298710	1			T2	32		T3	314		T8	779
valid_sources[0x37]	263264	1			T2	22		T3	301		T8	777
valid_sources[0x38]	317578	1			T2	39		T3	379		T8	666
valid_sources[0x39]	273361	1			T2	39		T3	304		T8	681
valid_sources[0x3a]	376154	1			T2	38		T3	356		T8	738
valid_sources[0x3b]	290092	1			T2	35		T3	354		T8	752
valid_sources[0x3c]	360391	1			T2	35		T3	361		T4	6940
valid_sources[0x3d]	308510	1			T2	32		T3	368		T8	661
valid_sources[0x3e]	363585	1			T2	24		T3	349		T8	759
valid_sources[0x3f]	254807	1			T2	29		T3	350		T8	869
valid_sources[0x40]	364053	1			T2	27		T3	346		T8	726
valid_sources[0x41]	262666	1			T2	29		T3	397		T8	680
valid_sources[0x42]	254724	1			T2	36		T3	361		T8	782
valid_sources[0x43]	291534	1			T2	43		T3	455		T8	750
valid_sources[0x44]	270907	1			T2	24		T3	313		T8	727
valid_sources[0x45]	336577	1			T2	33		T3	323		T8	781
valid_sources[0x46]	279362	1			T2	20		T3	312		T8	737
valid_sources[0x47]	275394	1			T2	41		T3	325		T8	720
valid_sources[0x48]	298159	1			T2	31		T3	315		T8	745
valid_sources[0x49]	351994	1			T2	37		T3	393		T8	674
valid_sources[0x4a]	317795	1			T2	41		T3	326		T8	747
valid_sources[0x4b]	286024	1			T2	49		T3	415		T4	2668
valid_sources[0x4c]	257297	1			T2	47		T3	366		T8	766
valid_sources[0x4d]	269754	1			T2	28		T3	331		T8	735
valid_sources[0x4e]	272767	1			T2	31		T3	365		T8	747
valid_sources[0x4f]	330140	1			T2	34		T3	325		T8	648
valid_sources[0x50]	366769	1			T2	34		T3	382		T8	677
valid_sources[0x51]	247896	1			T2	48		T3	341		T8	752
valid_sources[0x52]	257082	1			T2	36		T3	424		T8	678
valid_sources[0x53]	279544	1			T2	35		T3	379		T8	628
valid_sources[0x54]	288744	1			T2	35		T3	326		T8	714
valid_sources[0x55]	266601	1			T2	22		T3	392		T8	688
valid_sources[0x56]	258413	1			T2	31		T3	303		T8	760
valid_sources[0x57]	271884	1			T2	26		T3	310		T8	801
valid_sources[0x58]	311142	1			T2	29		T3	397		T8	686
valid_sources[0x59]	273423	1			T2	43		T3	230		T4	9705
valid_sources[0x5a]	323404	1			T2	39		T3	391		T8	706
valid_sources[0x5b]	289141	1			T2	34		T3	343		T8	718
valid_sources[0x5c]	440601	1			T2	34		T3	369		T8	772
valid_sources[0x5d]	254336	1			T2	28		T3	357		T8	759
valid_sources[0x5e]	267923	1			T2	40		T3	362		T8	725
valid_sources[0x5f]	253513	1			T2	31		T3	329		T8	744
valid_sources[0x60]	283009	1			T2	41		T3	409		T4	15
valid_sources[0x61]	292292	1			T2	30		T3	295		T8	691
valid_sources[0x62]	353937	1			T2	23		T3	384		T4	6861
valid_sources[0x63]	409465	1			T2	35		T3	421		T8	776
valid_sources[0x64]	292115	1			T2	49		T3	306		T8	777
valid_sources[0x65]	326047	1			T2	45		T3	333		T8	726
valid_sources[0x66]	332687	1			T2	35		T3	324		T4	3727
valid_sources[0x67]	273888	1			T2	38		T3	413		T8	669
valid_sources[0x68]	383313	1			T2	32		T3	392		T8	671
valid_sources[0x69]	264543	1			T2	28		T3	294		T8	733
valid_sources[0x6a]	256121	1			T2	33		T3	386		T8	783
valid_sources[0x6b]	273694	1			T2	24		T3	324		T8	712
valid_sources[0x6c]	296315	1			T2	34		T3	349		T8	714
valid_sources[0x6d]	291686	1			T2	40		T3	350		T8	746
valid_sources[0x6e]	306950	1			T2	35		T3	344		T8	741
valid_sources[0x6f]	284414	1			T2	42		T3	408		T8	754
valid_sources[0x70]	257749	1			T2	40		T3	257		T8	762
valid_sources[0x71]	270189	1			T2	37		T3	288		T4	22405
valid_sources[0x72]	256004	1			T2	40		T3	351		T8	771
valid_sources[0x73]	291590	1			T2	24		T3	385		T8	727
valid_sources[0x74]	282000	1			T2	34		T3	387		T8	743
valid_sources[0x75]	260906	1			T2	39		T3	387		T8	671
valid_sources[0x76]	264799	1			T2	35		T3	331		T8	772
valid_sources[0x77]	244173	1			T2	32		T3	364		T8	704
valid_sources[0x78]	257409	1			T2	34		T3	357		T8	736
valid_sources[0x79]	269936	1			T2	37		T3	350		T8	733
valid_sources[0x7a]	263215	1			T2	48		T3	311		T8	779
valid_sources[0x7b]	269888	1			T2	40		T3	334		T8	726
valid_sources[0x7c]	265536	1			T2	30		T3	301		T8	752
valid_sources[0x7d]	314261	1			T2	35		T3	318		T8	788
valid_sources[0x7e]	330554	1			T2	32		T3	305		T8	736
valid_sources[0x7f]	247032	1			T2	33		T3	325		T8	663
valid_sources[0x80]	298707	1			T2	24		T3	282		T8	666

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29711852

1

T2

4096

T3

42546

T4

52087

values[0x0]

all_enables

biggest_size

14952896

1

T2

2081

T3

21364

T4

25890

values[0x1]

all_enables

biggest_size

14951114

1

T2

1958

T3

21107

T4

26105

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118864

1

T2

2

T3

60

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	46020	1			T3	63		T10	679		T12	1546
values[0x0]	52588	1			T1	1		T2	1		T3	41
values[0x1]	55884	1			T2	1		T3	42		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

127157

1

T2

2

T3

72

T4

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	606	1			T10	11		T12	26		T19	6
valid_sources[0x01]	887	1			T10	15		T12	14		T139	2
valid_sources[0x02]	439	1			T10	12		T12	20		T43	1
valid_sources[0x03]	636	1			T10	14		T12	23		T19	4
valid_sources[0x04]	544	1			T10	10		T12	15		T6	1
valid_sources[0x05]	985	1			T10	12		T12	27		T22	3
valid_sources[0x06]	486	1			T10	11		T12	8		T68	3
valid_sources[0x07]	614	1			T10	9		T12	31		T68	2
valid_sources[0x08]	503	1			T10	16		T12	29		T39	1
valid_sources[0x09]	656	1			T10	11		T12	15		T22	1
valid_sources[0x0a]	622	1			T10	10		T12	33		T6	3
valid_sources[0x0b]	950	1			T10	9		T12	40		T60	1
valid_sources[0x0c]	516	1			T10	11		T12	33		T19	1
valid_sources[0x0d]	617	1			T10	17		T12	43		T76	1
valid_sources[0x0e]	673	1			T10	9		T12	32		T53	11
valid_sources[0x0f]	537	1			T10	8		T12	25		T133	1
valid_sources[0x10]	581	1			T10	13		T12	20		T67	2
valid_sources[0x11]	738	1			T10	10		T12	21		T60	1
valid_sources[0x12]	626	1			T10	19		T12	18		T6	1
valid_sources[0x13]	429	1			T10	9		T12	11		T67	1
valid_sources[0x14]	576	1			T10	5		T12	19		T22	3
valid_sources[0x15]	750	1			T2	1		T10	10		T12	26
valid_sources[0x16]	609	1			T10	6		T12	17		T43	1
valid_sources[0x17]	624	1			T10	10		T12	34		T53	12
valid_sources[0x18]	511	1			T10	10		T12	21		T140	1
valid_sources[0x19]	492	1			T10	5		T12	13		T68	1
valid_sources[0x1a]	524	1			T10	26		T12	21		T6	1
valid_sources[0x1b]	488	1			T10	12		T12	16		T54	8
valid_sources[0x1c]	474	1			T10	12		T12	14		T141	1
valid_sources[0x1d]	512	1			T10	12		T12	38		T19	1
valid_sources[0x1e]	779	1			T10	12		T12	18		T22	9
valid_sources[0x1f]	486	1			T10	6		T12	33		T142	1
valid_sources[0x20]	434	1			T10	11		T12	13		T68	2
valid_sources[0x21]	579	1			T10	9		T12	23		T22	3
valid_sources[0x22]	580	1			T4	1		T10	6		T12	32
valid_sources[0x23]	619	1			T10	13		T12	16		T40	3
valid_sources[0x24]	462	1			T10	7		T12	35		T6	1
valid_sources[0x25]	503	1			T10	14		T12	19		T19	2
valid_sources[0x26]	496	1			T10	14		T12	31		T6	1
valid_sources[0x27]	895	1			T10	9		T12	18		T53	22
valid_sources[0x28]	519	1			T10	3		T12	10		T22	12
valid_sources[0x29]	512	1			T10	8		T12	17		T67	1
valid_sources[0x2a]	852	1			T10	7		T12	25		T52	208
valid_sources[0x2b]	719	1			T10	4		T12	25		T19	3
valid_sources[0x2c]	874	1			T10	5		T12	15		T36	13
valid_sources[0x2d]	766	1			T10	13		T12	21		T6	1
valid_sources[0x2e]	1048	1			T10	11		T12	23		T53	13
valid_sources[0x2f]	542	1			T10	12		T12	36		T19	1
valid_sources[0x30]	560	1			T10	12		T12	30		T67	1
valid_sources[0x31]	516	1			T10	7		T12	17		T53	38
valid_sources[0x32]	890	1			T10	13		T12	23		T19	3
valid_sources[0x33]	429	1			T10	9		T12	44		T67	1
valid_sources[0x34]	526	1			T10	13		T12	29		T52	1
valid_sources[0x35]	783	1			T10	7		T12	27		T143	190
valid_sources[0x36]	1155	1			T10	14		T12	30		T67	1
valid_sources[0x37]	529	1			T9	22		T10	4		T12	25
valid_sources[0x38]	656	1			T10	5		T12	28		T19	8
valid_sources[0x39]	750	1			T10	11		T12	19		T41	1
valid_sources[0x3a]	563	1			T10	10		T12	20		T139	1
valid_sources[0x3b]	467	1			T10	5		T12	12		T19	6
valid_sources[0x3c]	505	1			T10	11		T12	16		T55	2
valid_sources[0x3d]	560	1			T10	11		T12	29		T19	4
valid_sources[0x3e]	959	1			T10	11		T12	16		T60	1
valid_sources[0x3f]	743	1			T10	7		T12	23		T67	1
valid_sources[0x40]	461	1			T10	9		T12	29		T6	1
valid_sources[0x41]	785	1			T10	12		T12	24		T53	20
valid_sources[0x42]	508	1			T10	7		T12	19		T68	1
valid_sources[0x43]	657	1			T10	12		T12	26		T38	24
valid_sources[0x44]	833	1			T10	13		T12	20		T67	2
valid_sources[0x45]	452	1			T10	6		T12	27		T68	2
valid_sources[0x46]	505	1			T10	17		T12	19		T39	2
valid_sources[0x47]	1090	1			T10	10		T12	26		T68	1
valid_sources[0x48]	1009	1			T10	14		T12	37		T19	1
valid_sources[0x49]	473	1			T10	11		T12	31		T53	39
valid_sources[0x4a]	842	1			T10	10		T12	24		T67	1
valid_sources[0x4b]	503	1			T10	13		T12	15		T19	1
valid_sources[0x4c]	463	1			T10	15		T12	16		T19	2
valid_sources[0x4d]	451	1			T10	9		T12	17		T67	1
valid_sources[0x4e]	646	1			T10	13		T12	44		T20	1
valid_sources[0x4f]	650	1			T10	8		T12	13		T67	1
valid_sources[0x50]	698	1			T10	16		T12	24		T43	1
valid_sources[0x51]	651	1			T10	7		T12	28		T60	1
valid_sources[0x52]	459	1			T10	16		T12	13		T6	1
valid_sources[0x53]	544	1			T10	13		T12	28		T139	1
valid_sources[0x54]	646	1			T10	10		T12	33		T22	186
valid_sources[0x55]	452	1			T10	10		T12	23		T52	2
valid_sources[0x56]	546	1			T10	10		T12	28		T6	1
valid_sources[0x57]	677	1			T10	14		T12	33		T144	1
valid_sources[0x58]	496	1			T4	1		T10	6		T12	27
valid_sources[0x59]	534	1			T10	9		T12	20		T19	2
valid_sources[0x5a]	509	1			T10	10		T12	31		T51	2
valid_sources[0x5b]	459	1			T10	9		T12	20		T140	1
valid_sources[0x5c]	686	1			T10	6		T12	23		T40	1
valid_sources[0x5d]	525	1			T10	9		T12	24		T39	2
valid_sources[0x5e]	662	1			T10	7		T12	24		T67	2
valid_sources[0x5f]	425	1			T10	8		T12	28		T139	1
valid_sources[0x60]	628	1			T10	9		T12	23		T39	1
valid_sources[0x61]	503	1			T10	5		T12	36		T22	4
valid_sources[0x62]	562	1			T10	5		T12	23		T113	2
valid_sources[0x63]	467	1			T10	7		T12	28		T6	2
valid_sources[0x64]	532	1			T10	6		T12	11		T53	10
valid_sources[0x65]	704	1			T10	12		T12	40		T6	1
valid_sources[0x66]	584	1			T10	6		T12	15		T67	1
valid_sources[0x67]	595	1			T10	16		T12	14		T140	1
valid_sources[0x68]	760	1			T10	15		T12	20		T22	16
valid_sources[0x69]	546	1			T10	8		T12	20		T41	1
valid_sources[0x6a]	440	1			T10	13		T12	19		T82	2
valid_sources[0x6b]	575	1			T10	14		T12	16		T41	1
valid_sources[0x6c]	614	1			T10	8		T12	25		T67	1
valid_sources[0x6d]	431	1			T4	1		T10	15		T12	17
valid_sources[0x6e]	465	1			T10	11		T12	33		T136	1
valid_sources[0x6f]	567	1			T10	8		T12	15		T6	1
valid_sources[0x70]	959	1			T10	12		T12	38		T67	2
valid_sources[0x71]	607	1			T10	11		T12	39		T60	1
valid_sources[0x72]	498	1			T10	12		T12	20		T6	1
valid_sources[0x73]	559	1			T10	8		T12	24		T67	1
valid_sources[0x74]	1146	1			T10	11		T12	12		T68	1
valid_sources[0x75]	455	1			T10	10		T12	39		T53	24
valid_sources[0x76]	572	1			T10	15		T12	46		T144	1
valid_sources[0x77]	501	1			T10	5		T12	22		T68	4
valid_sources[0x78]	665	1			T10	6		T12	24		T19	2
valid_sources[0x79]	462	1			T10	15		T12	22		T136	1
valid_sources[0x7a]	519	1			T10	16		T12	29		T46	1
valid_sources[0x7b]	552	1			T10	11		T12	32		T60	1
valid_sources[0x7c]	587	1			T10	4		T12	21		T60	1
valid_sources[0x7d]	517	1			T10	23		T12	31		T67	1
valid_sources[0x7e]	843	1			T10	10		T12	37		T67	1
valid_sources[0x7f]	529	1			T10	14		T12	21		T6	2
valid_sources[0x80]	541	1			T10	12		T12	21		T39	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33131

1

T3

33

T10

628

T12

1423

values[0x0]

all_enables

biggest_size

44094

1

T2

1

T3

17

T4

4

values[0x1]

all_enables

biggest_size

41639

1

T2

1

T3

10

T8

1