Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13867900

1

T2

824

T3

4236

T4

10431

full_word

54557439

1

T2

8135

T3

75815

T4

104082

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68424999	1			T2	8959		T3	80051		T4	114513
auto[TlIntgErrCmd]	112	1			T57	6		T58	9		T59	10
auto[TlIntgErrData]	109	1			T57	7		T58	4		T59	6
auto[TlIntgErrBoth]	119	1			T57	7		T58	7		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31376190

1

T2

4505

T3

38216

T4

57410

auto[1]

37049149

1

T2

4454

T3

41835

T4

57103

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6638183	1			T2	409		T3	1969		T4	5323
auto[TlIntgErrNone]	partial	auto[1]	7229405	1			T2	415		T3	2267		T4	5108
auto[TlIntgErrNone]	full_word	auto[0]	24737852	1			T2	4096		T3	36247		T4	52087
auto[TlIntgErrNone]	full_word	auto[1]	29819559	1			T2	4039		T3	39568		T4	51995
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T57	5		T58	3		T59	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T57	1		T58	4		T59	9
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T127	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T58	2		T127	1		T124	2
auto[TlIntgErrData]	partial	auto[0]	47	1			T57	3		T58	4		T59	1
auto[TlIntgErrData]	partial	auto[1]	51	1			T57	2		T59	4		T128	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T57	1		T129	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T57	1		T59	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T57	3		T58	2		T59	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T57	3		T58	5		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T57	1		T131	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T130	1		T129	1		T125	1