Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	561388	1			T3	66		T5	24199		T19	17
auto[1]	10952274	1			T2	4485		T3	622		T4	46872
auto[2]	469979	1			T3	37		T5	20534		T19	26
auto[3]	10863584	1			T2	4431		T3	519		T4	46548

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14482346	1			T2	7388		T3	883		T4	77288
auto[1]	2206966	1			T2	707		T3	147		T4	7628
auto[2]	2236544	1			T2	765		T3	191		T4	7759
auto[3]	3921369	1			T2	56		T3	23		T4	745

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8358885

1

T2

8904

T3

1243

T4

93349

auto[1]

14488340

1

T2

12

T3

1

T4

71

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	219883	1			T3	53		T19	17		T41	6
auto[0]	auto[0]	auto[1]	22695	1			T3	8		T5	1		T41	1
auto[0]	auto[0]	auto[2]	22507	1			T3	5		T5	1		T41	2
auto[0]	auto[0]	auto[3]	6988	1			T5	2		T37	8		T112	2
auto[0]	auto[1]	auto[0]	3233019	1			T2	3743		T3	462		T4	38765
auto[0]	auto[1]	auto[1]	331966	1			T2	326		T3	101		T4	3770
auto[0]	auto[1]	auto[2]	326930	1			T2	385		T3	47		T4	3901
auto[0]	auto[1]	auto[3]	54589	1			T2	22		T3	12		T4	400
auto[0]	auto[2]	auto[0]	183732	1			T6	1		T22	10		T112	144
auto[0]	auto[2]	auto[1]	18798	1			T37	1		T22	1		T112	13
auto[0]	auto[2]	auto[2]	23179	1			T3	34		T19	23		T41	6
auto[0]	auto[2]	auto[3]	6237	1			T3	3		T5	3		T19	3
auto[0]	auto[3]	auto[0]	3195990	1			T2	3633		T3	367		T4	38466
auto[0]	auto[3]	auto[1]	323127	1			T2	381		T3	38		T4	3853
auto[0]	auto[3]	auto[2]	333284	1			T2	380		T3	105		T4	3849
auto[0]	auto[3]	auto[3]	55961	1			T2	34		T3	8		T4	345
auto[1]	auto[0]	auto[0]	9670	1			T5	783		T37	1215		T112	1
auto[1]	auto[0]	auto[1]	43309	1			T5	3527		T37	5639		T138	1
auto[1]	auto[0]	auto[2]	42968	1			T5	3611		T37	5592		T138	2
auto[1]	auto[0]	auto[3]	193368	1			T5	16274		T37	25229		T137	2
auto[1]	auto[1]	auto[0]	3817708	1			T2	9		T4	28		T8	2567
auto[1]	auto[1]	auto[1]	730747	1			T4	2		T8	11749		T5	3624
auto[1]	auto[1]	auto[2]	725464	1			T4	6		T8	11952		T9	1
auto[1]	auto[1]	auto[3]	1731851	1			T8	53370		T5	16262		T35	1
auto[1]	auto[2]	auto[0]	6556	1			T5	738		T37	1116		T138	12
auto[1]	auto[2]	auto[1]	28489	1			T5	3272		T37	5069		T138	1
auto[1]	auto[2]	auto[2]	37000	1			T5	2937		T37	4692		T138	1
auto[1]	auto[2]	auto[3]	165988	1			T5	13584		T37	20949		T137	1
auto[1]	auto[3]	auto[0]	3815788	1			T2	3		T3	1		T4	29
auto[1]	auto[3]	auto[1]	707835	1			T4	3		T8	11835		T5	287
auto[1]	auto[3]	auto[2]	725212	1			T4	3		T8	11766		T9	1
auto[1]	auto[3]	auto[3]	1706387	1			T8	53193		T5	13728		T54	51809