Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	285485412	164020	0	0
ctrl_regwen_rd_A	285485412	3608	0	0
exec_rd_A	285485412	3589	0	0
exec_regwen_rd_A	285485412	3672	0	0
readback_rd_A	285485412	2386	0	0
readback_regwen_rd_A	285485412	2210	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285485412	164020	0	0
T10	79790	4246	0	0
T11	1908	0	0	0
T12	242090	9785	0	0
T19	103919	0	0	0
T22	0	1419	0	0
T35	292189	0	0	0
T42	5508	0	0	0
T43	44133	0	0	0
T44	0	5096	0	0
T46	8664	0	0	0
T49	0	5062	0	0
T52	0	4451	0	0
T53	0	7153	0	0
T54	405801	0	0	0
T55	225677	0	0	0
T56	0	3934	0	0
T65	0	4419	0	0
T66	0	813	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285485412	3608	0	0
T20	961980	0	0	0
T22	24673	56	0	0
T23	2843	0	0	0
T44	0	155	0	0
T52	108788	0	0	0
T66	0	72	0	0
T68	515019	0	0	0
T82	363228	0	0	0
T105	0	164	0	0
T106	0	291	0	0
T107	0	364	0	0
T108	0	168	0	0
T109	0	131	0	0
T110	0	107	0	0
T111	0	272	0	0
T112	32517	0	0	0
T113	392771	0	0	0
T114	4842	0	0	0
T115	25901	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285485412	3589	0	0
T20	961980	0	0	0
T22	24673	94	0	0
T23	2843	0	0	0
T44	0	190	0	0
T52	108788	0	0	0
T66	0	43	0	0
T68	515019	0	0	0
T82	363228	0	0	0
T105	0	86	0	0
T106	0	275	0	0
T107	0	355	0	0
T108	0	113	0	0
T109	0	109	0	0
T110	0	99	0	0
T111	0	263	0	0
T112	32517	0	0	0
T113	392771	0	0	0
T114	4842	0	0	0
T115	25901	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285485412	3672	0	0
T20	961980	0	0	0
T22	24673	71	0	0
T23	2843	0	0	0
T44	0	202	0	0
T52	108788	0	0	0
T66	0	43	0	0
T68	515019	0	0	0
T82	363228	0	0	0
T105	0	107	0	0
T106	0	296	0	0
T107	0	354	0	0
T108	0	153	0	0
T109	0	126	0	0
T110	0	117	0	0
T111	0	395	0	0
T112	32517	0	0	0
T113	392771	0	0	0
T114	4842	0	0	0
T115	25901	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285485412	2386	0	0
T20	961980	0	0	0
T22	24673	48	0	0
T23	2843	0	0	0
T44	0	132	0	0
T52	108788	0	0	0
T66	0	10	0	0
T68	515019	0	0	0
T82	363228	0	0	0
T105	0	152	0	0
T106	0	190	0	0
T107	0	311	0	0
T108	0	111	0	0
T109	0	139	0	0
T110	0	90	0	0
T111	0	267	0	0
T112	32517	0	0	0
T113	392771	0	0	0
T114	4842	0	0	0
T115	25901	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285485412	2210	0	0
T20	961980	0	0	0
T22	24673	52	0	0
T23	2843	0	0	0
T44	0	145	0	0
T52	108788	0	0	0
T66	0	38	0	0
T68	515019	0	0	0
T82	363228	0	0	0
T105	0	100	0	0
T106	0	179	0	0
T107	0	261	0	0
T108	0	112	0	0
T109	0	88	0	0
T110	0	76	0	0
T111	0	245	0	0
T112	32517	0	0	0
T113	392771	0	0	0
T114	4842	0	0	0
T115	25901	0	0	0