Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	139503090	1			T1	129840		T2	529898		T3	16246
instr_valid_dis	108936549	1			T1	129840		T2	125386		T3	16246
instr_en	21615266	1			T2	268564		T13	84778		T27	324158

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10212549	1			T2	183126		T11	82		T13	77752
sram_ifetch_valid_disable	109629588	1			T1	129840		T2	189446		T3	16246
sram_ifetch_enable	19660953	1			T2	157326		T11	40894		T13	137938

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	139503090	1			T1	129840		T2	529898		T3	16246
hw_debug_en_valid_off	110170812	1			T1	129840		T2	299352		T3	16246
hw_debug_en_on	19020440	1			T2	214146		T11	33794		T13	176444

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109629588	1			T1	129840		T2	189446		T3	16246
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97402194	1			T1	129840		T2	67716		T3	16246
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8310801	1			T2	121730		T13	42882		T27	175060
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3925372	1			T2	108206		T13	50680		T21	112040
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1487436	1			T13	16136		T21	80372		T22	504
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1851030	1			T2	80278		T21	31668		T68	13880
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4373778	1			T2	74920		T11	82		T13	27072
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1441864	1			T2	26468		T11	82		T13	27072
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2140778	1			T2	18352		T27	28316		T68	51460
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7491522	1			T2	60844		T11	12818		T13	99084
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2518836	1			T2	2180		T11	12818		T13	99084
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3416888	1			T2	58664		T27	19436		T21	166030

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8393315	1			T2	48204		T13	41896		T27	120782
lc_exec_en	7155140	1			T2	78382		T11	20894		T13	50288
valid_exec_dis	105480586	1			T1	129840		T2	159804		T3	16246
invalid_exec_dis	29873502	1			T2	340452		T11	40976		T13	215690