Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42209263	1			T1	59081		T2	96387		T3	8123
triple_byte_access	2448763	1			T1	1165		T2	1902		T4	2026
halfword_access	3673751	1			T1	1716		T2	2910		T4	3165
byte_access	4907211	1			T1	2346		T2	3844		T4	4290
zero_access	1235492	1			T1	612		T2	897		T4	994

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27175026

1

T1

32498

T2

53125

T3

4103

auto[1]

27299454

1

T1

32422

T2

52815

T3

4020

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21046711	1			T1	29593		T2	48346		T3	4103
auto[0]	triple_byte_access	1220310	1			T1	561		T2	970		T4	1013
auto[0]	halfword_access	1834693	1			T1	849		T2	1423		T4	1545
auto[0]	byte_access	2452238	1			T1	1156		T2	1935		T4	2106
auto[0]	zero_access	621074	1			T1	339		T2	451		T4	508
auto[1]	word_access	21162552	1			T1	29488		T2	48041		T3	4020
auto[1]	triple_byte_access	1228453	1			T1	604		T2	932		T4	1013
auto[1]	halfword_access	1839058	1			T1	867		T2	1487		T4	1620
auto[1]	byte_access	2454973	1			T1	1190		T2	1909		T4	2184
auto[1]	zero_access	614418	1			T1	273		T2	446		T4	486