| T791 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.4252779231 |
|
|
Jul 20 05:05:25 PM PDT 24 |
Jul 20 05:33:06 PM PDT 24 |
189084979970 ps |
| T792 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1991554207 |
|
|
Jul 20 05:01:27 PM PDT 24 |
Jul 20 05:01:29 PM PDT 24 |
30039018 ps |
| T793 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3029263487 |
|
|
Jul 20 05:09:47 PM PDT 24 |
Jul 20 05:09:53 PM PDT 24 |
342620133 ps |
| T794 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1769342559 |
|
|
Jul 20 05:10:30 PM PDT 24 |
Jul 20 05:10:34 PM PDT 24 |
324452919 ps |
| T795 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2048603351 |
|
|
Jul 20 05:11:03 PM PDT 24 |
Jul 20 05:11:37 PM PDT 24 |
183950655 ps |
| T796 |
/workspace/coverage/default/40.sram_ctrl_executable.3744332037 |
|
|
Jul 20 05:10:01 PM PDT 24 |
Jul 20 05:21:06 PM PDT 24 |
37833988039 ps |
| T797 |
/workspace/coverage/default/33.sram_ctrl_smoke.1303759003 |
|
|
Jul 20 05:08:05 PM PDT 24 |
Jul 20 05:08:19 PM PDT 24 |
1507646944 ps |
| T798 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.3231235979 |
|
|
Jul 20 05:03:31 PM PDT 24 |
Jul 20 05:18:10 PM PDT 24 |
17096351929 ps |
| T799 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1819670070 |
|
|
Jul 20 05:08:35 PM PDT 24 |
Jul 20 05:29:24 PM PDT 24 |
3591421631 ps |
| T800 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2135200458 |
|
|
Jul 20 05:02:23 PM PDT 24 |
Jul 20 05:02:35 PM PDT 24 |
470245863 ps |
| T801 |
/workspace/coverage/default/0.sram_ctrl_partial_access.273823544 |
|
|
Jul 20 05:01:00 PM PDT 24 |
Jul 20 05:01:11 PM PDT 24 |
1835256135 ps |
| T802 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.219482767 |
|
|
Jul 20 05:08:05 PM PDT 24 |
Jul 20 05:19:04 PM PDT 24 |
1692086728 ps |
| T803 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2605878795 |
|
|
Jul 20 05:03:55 PM PDT 24 |
Jul 20 05:04:03 PM PDT 24 |
224009441 ps |
| T804 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.810233991 |
|
|
Jul 20 05:10:23 PM PDT 24 |
Jul 20 05:12:30 PM PDT 24 |
294189847 ps |
| T805 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1440937844 |
|
|
Jul 20 05:01:18 PM PDT 24 |
Jul 20 05:01:20 PM PDT 24 |
87246453 ps |
| T806 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1169884532 |
|
|
Jul 20 05:11:13 PM PDT 24 |
Jul 20 05:11:14 PM PDT 24 |
14547200 ps |
| T807 |
/workspace/coverage/default/31.sram_ctrl_bijection.1796597675 |
|
|
Jul 20 05:07:38 PM PDT 24 |
Jul 20 05:07:58 PM PDT 24 |
923979857 ps |
| T808 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4172670611 |
|
|
Jul 20 05:02:24 PM PDT 24 |
Jul 20 05:07:28 PM PDT 24 |
6801537501 ps |
| T809 |
/workspace/coverage/default/24.sram_ctrl_regwen.2410630525 |
|
|
Jul 20 05:05:53 PM PDT 24 |
Jul 20 05:11:28 PM PDT 24 |
1437380829 ps |
| T810 |
/workspace/coverage/default/42.sram_ctrl_alert_test.38578779 |
|
|
Jul 20 05:10:39 PM PDT 24 |
Jul 20 05:10:40 PM PDT 24 |
16878585 ps |
| T811 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3679193974 |
|
|
Jul 20 05:11:39 PM PDT 24 |
Jul 20 05:11:40 PM PDT 24 |
252158295 ps |
| T812 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1782823971 |
|
|
Jul 20 05:10:29 PM PDT 24 |
Jul 20 05:27:12 PM PDT 24 |
9270913005 ps |
| T813 |
/workspace/coverage/default/20.sram_ctrl_executable.168974407 |
|
|
Jul 20 05:04:46 PM PDT 24 |
Jul 20 05:22:35 PM PDT 24 |
2857878325 ps |
| T814 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3992278791 |
|
|
Jul 20 05:07:46 PM PDT 24 |
Jul 20 05:17:30 PM PDT 24 |
19149689913 ps |
| T815 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1843284431 |
|
|
Jul 20 05:02:58 PM PDT 24 |
Jul 20 05:46:05 PM PDT 24 |
9614668072 ps |
| T816 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2321305151 |
|
|
Jul 20 05:11:27 PM PDT 24 |
Jul 20 05:11:29 PM PDT 24 |
100027260 ps |
| T817 |
/workspace/coverage/default/29.sram_ctrl_regwen.1556128970 |
|
|
Jul 20 05:07:13 PM PDT 24 |
Jul 20 05:12:12 PM PDT 24 |
1557355276 ps |
| T818 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2127626045 |
|
|
Jul 20 05:09:45 PM PDT 24 |
Jul 20 05:12:30 PM PDT 24 |
448674951 ps |
| T819 |
/workspace/coverage/default/4.sram_ctrl_smoke.2103627190 |
|
|
Jul 20 05:01:27 PM PDT 24 |
Jul 20 05:02:22 PM PDT 24 |
537784166 ps |
| T820 |
/workspace/coverage/default/34.sram_ctrl_executable.1200492301 |
|
|
Jul 20 05:08:30 PM PDT 24 |
Jul 20 05:21:38 PM PDT 24 |
27112184776 ps |
| T821 |
/workspace/coverage/default/43.sram_ctrl_regwen.1175848841 |
|
|
Jul 20 05:10:56 PM PDT 24 |
Jul 20 05:26:40 PM PDT 24 |
22779090023 ps |
| T822 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3665819030 |
|
|
Jul 20 05:09:37 PM PDT 24 |
Jul 20 05:28:48 PM PDT 24 |
51680475161 ps |
| T823 |
/workspace/coverage/default/14.sram_ctrl_smoke.208368469 |
|
|
Jul 20 05:02:56 PM PDT 24 |
Jul 20 05:03:40 PM PDT 24 |
438197987 ps |
| T824 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.4072916829 |
|
|
Jul 20 05:09:13 PM PDT 24 |
Jul 20 05:09:31 PM PDT 24 |
73356834 ps |
| T825 |
/workspace/coverage/default/33.sram_ctrl_regwen.2478484194 |
|
|
Jul 20 05:08:16 PM PDT 24 |
Jul 20 05:19:38 PM PDT 24 |
38896155563 ps |
| T826 |
/workspace/coverage/default/3.sram_ctrl_smoke.2204080518 |
|
|
Jul 20 05:01:18 PM PDT 24 |
Jul 20 05:03:18 PM PDT 24 |
1202689580 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3564163076 |
|
|
Jul 20 05:10:11 PM PDT 24 |
Jul 20 05:10:24 PM PDT 24 |
2621471238 ps |
| T828 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1080727251 |
|
|
Jul 20 05:08:15 PM PDT 24 |
Jul 20 05:08:21 PM PDT 24 |
366134829 ps |
| T829 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2410051 |
|
|
Jul 20 05:03:46 PM PDT 24 |
Jul 20 05:14:39 PM PDT 24 |
23732783976 ps |
| T830 |
/workspace/coverage/default/13.sram_ctrl_bijection.2714385661 |
|
|
Jul 20 05:02:48 PM PDT 24 |
Jul 20 05:03:35 PM PDT 24 |
1480764284 ps |
| T831 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1162666503 |
|
|
Jul 20 05:01:39 PM PDT 24 |
Jul 20 05:02:00 PM PDT 24 |
2196889270 ps |
| T832 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2188539327 |
|
|
Jul 20 05:06:24 PM PDT 24 |
Jul 20 05:13:29 PM PDT 24 |
12825988069 ps |
| T833 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1659960216 |
|
|
Jul 20 05:01:38 PM PDT 24 |
Jul 20 05:01:43 PM PDT 24 |
255165958 ps |
| T834 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1173380404 |
|
|
Jul 20 05:02:40 PM PDT 24 |
Jul 20 05:55:24 PM PDT 24 |
53628058503 ps |
| T835 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.3619996924 |
|
|
Jul 20 05:11:54 PM PDT 24 |
Jul 20 05:12:01 PM PDT 24 |
1161972194 ps |
| T836 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2787135638 |
|
|
Jul 20 05:01:09 PM PDT 24 |
Jul 20 05:01:18 PM PDT 24 |
2630275122 ps |
| T837 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2271547326 |
|
|
Jul 20 05:08:46 PM PDT 24 |
Jul 20 05:11:39 PM PDT 24 |
8238760292 ps |
| T838 |
/workspace/coverage/default/21.sram_ctrl_regwen.1198159264 |
|
|
Jul 20 05:05:01 PM PDT 24 |
Jul 20 05:10:17 PM PDT 24 |
1766085545 ps |
| T839 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3553291177 |
|
|
Jul 20 05:02:10 PM PDT 24 |
Jul 20 05:02:11 PM PDT 24 |
73856782 ps |
| T840 |
/workspace/coverage/default/30.sram_ctrl_executable.2841770036 |
|
|
Jul 20 05:07:41 PM PDT 24 |
Jul 20 05:15:29 PM PDT 24 |
15214082954 ps |
| T841 |
/workspace/coverage/default/40.sram_ctrl_bijection.507434215 |
|
|
Jul 20 05:09:55 PM PDT 24 |
Jul 20 05:11:05 PM PDT 24 |
6179379290 ps |
| T842 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.559351646 |
|
|
Jul 20 05:07:12 PM PDT 24 |
Jul 20 05:08:19 PM PDT 24 |
122699903 ps |
| T843 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2984591035 |
|
|
Jul 20 05:02:56 PM PDT 24 |
Jul 20 05:19:44 PM PDT 24 |
23422216372 ps |
| T32 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.4105241955 |
|
|
Jul 20 05:01:18 PM PDT 24 |
Jul 20 05:01:21 PM PDT 24 |
333031561 ps |
| T844 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.1938130322 |
|
|
Jul 20 05:07:38 PM PDT 24 |
Jul 20 05:07:47 PM PDT 24 |
138169667 ps |
| T845 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.380817660 |
|
|
Jul 20 05:03:05 PM PDT 24 |
Jul 20 05:03:11 PM PDT 24 |
147028158 ps |
| T846 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2154979473 |
|
|
Jul 20 05:11:27 PM PDT 24 |
Jul 20 05:13:37 PM PDT 24 |
154306126 ps |
| T847 |
/workspace/coverage/default/36.sram_ctrl_executable.4188965405 |
|
|
Jul 20 05:09:01 PM PDT 24 |
Jul 20 05:21:17 PM PDT 24 |
9138536029 ps |
| T848 |
/workspace/coverage/default/7.sram_ctrl_bijection.3541895660 |
|
|
Jul 20 05:01:34 PM PDT 24 |
Jul 20 05:02:28 PM PDT 24 |
804779629 ps |
| T849 |
/workspace/coverage/default/2.sram_ctrl_regwen.1623002182 |
|
|
Jul 20 05:01:18 PM PDT 24 |
Jul 20 05:04:49 PM PDT 24 |
9979192898 ps |
| T850 |
/workspace/coverage/default/40.sram_ctrl_stress_all.922192521 |
|
|
Jul 20 05:10:11 PM PDT 24 |
Jul 20 05:52:38 PM PDT 24 |
26373951270 ps |
| T851 |
/workspace/coverage/default/38.sram_ctrl_smoke.282771829 |
|
|
Jul 20 05:09:16 PM PDT 24 |
Jul 20 05:11:43 PM PDT 24 |
2942605805 ps |
| T852 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2774867206 |
|
|
Jul 20 05:09:36 PM PDT 24 |
Jul 20 05:09:39 PM PDT 24 |
77308562 ps |
| T853 |
/workspace/coverage/default/17.sram_ctrl_smoke.2830665916 |
|
|
Jul 20 05:03:46 PM PDT 24 |
Jul 20 05:06:02 PM PDT 24 |
1557979253 ps |
| T854 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2125686908 |
|
|
Jul 20 05:01:26 PM PDT 24 |
Jul 20 05:01:32 PM PDT 24 |
97721751 ps |
| T855 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2409395795 |
|
|
Jul 20 05:01:38 PM PDT 24 |
Jul 20 05:03:54 PM PDT 24 |
217814248 ps |
| T856 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.873041640 |
|
|
Jul 20 05:10:56 PM PDT 24 |
Jul 20 05:10:58 PM PDT 24 |
29149078 ps |
| T857 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1337847491 |
|
|
Jul 20 05:11:03 PM PDT 24 |
Jul 20 05:11:16 PM PDT 24 |
682860013 ps |
| T858 |
/workspace/coverage/default/9.sram_ctrl_executable.3611273581 |
|
|
Jul 20 05:02:00 PM PDT 24 |
Jul 20 05:25:45 PM PDT 24 |
15820630851 ps |
| T859 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3267967817 |
|
|
Jul 20 05:04:47 PM PDT 24 |
Jul 20 05:04:48 PM PDT 24 |
37556589 ps |
| T860 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1601567464 |
|
|
Jul 20 05:11:39 PM PDT 24 |
Jul 20 05:40:39 PM PDT 24 |
33365734442 ps |
| T861 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.816538070 |
|
|
Jul 20 05:02:00 PM PDT 24 |
Jul 20 05:02:05 PM PDT 24 |
296118913 ps |
| T862 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.72785477 |
|
|
Jul 20 05:07:56 PM PDT 24 |
Jul 20 05:12:36 PM PDT 24 |
15394352192 ps |
| T863 |
/workspace/coverage/default/39.sram_ctrl_stress_all.591601444 |
|
|
Jul 20 05:09:53 PM PDT 24 |
Jul 20 06:14:33 PM PDT 24 |
45200227175 ps |
| T864 |
/workspace/coverage/default/43.sram_ctrl_smoke.4005266816 |
|
|
Jul 20 05:10:38 PM PDT 24 |
Jul 20 05:12:41 PM PDT 24 |
739043998 ps |
| T865 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2107673237 |
|
|
Jul 20 05:10:22 PM PDT 24 |
Jul 20 05:10:28 PM PDT 24 |
65257329 ps |
| T866 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.4132471464 |
|
|
Jul 20 05:07:27 PM PDT 24 |
Jul 20 05:07:33 PM PDT 24 |
56233798 ps |
| T867 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1842729796 |
|
|
Jul 20 05:01:37 PM PDT 24 |
Jul 20 05:04:13 PM PDT 24 |
590307268 ps |
| T868 |
/workspace/coverage/default/6.sram_ctrl_partial_access.370500184 |
|
|
Jul 20 05:01:37 PM PDT 24 |
Jul 20 05:01:40 PM PDT 24 |
189949358 ps |
| T869 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3150031933 |
|
|
Jul 20 05:02:26 PM PDT 24 |
Jul 20 05:04:24 PM PDT 24 |
143842975 ps |
| T870 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2000558419 |
|
|
Jul 20 05:12:11 PM PDT 24 |
Jul 20 05:12:15 PM PDT 24 |
2813824991 ps |
| T871 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2491467009 |
|
|
Jul 20 05:03:14 PM PDT 24 |
Jul 20 05:05:18 PM PDT 24 |
670614390 ps |
| T872 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2163404960 |
|
|
Jul 20 05:03:30 PM PDT 24 |
Jul 20 05:03:36 PM PDT 24 |
1317547562 ps |
| T873 |
/workspace/coverage/default/22.sram_ctrl_bijection.88905391 |
|
|
Jul 20 05:05:08 PM PDT 24 |
Jul 20 05:06:11 PM PDT 24 |
3041260638 ps |
| T874 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3188376456 |
|
|
Jul 20 05:09:46 PM PDT 24 |
Jul 20 05:10:02 PM PDT 24 |
279209418 ps |
| T875 |
/workspace/coverage/default/7.sram_ctrl_alert_test.288011833 |
|
|
Jul 20 05:01:43 PM PDT 24 |
Jul 20 05:01:44 PM PDT 24 |
50554095 ps |
| T876 |
/workspace/coverage/default/2.sram_ctrl_executable.2345308965 |
|
|
Jul 20 05:01:20 PM PDT 24 |
Jul 20 05:15:58 PM PDT 24 |
2308513615 ps |
| T877 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1230746398 |
|
|
Jul 20 05:11:54 PM PDT 24 |
Jul 20 05:12:00 PM PDT 24 |
344013515 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_partial_access.163356480 |
|
|
Jul 20 05:10:39 PM PDT 24 |
Jul 20 05:10:46 PM PDT 24 |
1380874840 ps |
| T879 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.217643686 |
|
|
Jul 20 05:10:37 PM PDT 24 |
Jul 20 05:27:57 PM PDT 24 |
41233447303 ps |
| T880 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.332756584 |
|
|
Jul 20 05:04:31 PM PDT 24 |
Jul 20 05:04:35 PM PDT 24 |
1531236824 ps |
| T881 |
/workspace/coverage/default/17.sram_ctrl_bijection.3859673123 |
|
|
Jul 20 05:03:46 PM PDT 24 |
Jul 20 05:04:34 PM PDT 24 |
751049275 ps |
| T122 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1193940356 |
|
|
Jul 20 05:03:13 PM PDT 24 |
Jul 20 05:03:51 PM PDT 24 |
15450532648 ps |
| T882 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.3774950505 |
|
|
Jul 20 05:07:54 PM PDT 24 |
Jul 20 05:10:21 PM PDT 24 |
705382209 ps |
| T883 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.530076783 |
|
|
Jul 20 05:07:04 PM PDT 24 |
Jul 20 05:07:06 PM PDT 24 |
84686532 ps |
| T884 |
/workspace/coverage/default/31.sram_ctrl_alert_test.4129879194 |
|
|
Jul 20 05:07:55 PM PDT 24 |
Jul 20 05:07:57 PM PDT 24 |
29775944 ps |
| T885 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.783736773 |
|
|
Jul 20 05:05:42 PM PDT 24 |
Jul 20 05:05:48 PM PDT 24 |
875413116 ps |
| T123 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3174741454 |
|
|
Jul 20 05:06:07 PM PDT 24 |
Jul 20 05:13:06 PM PDT 24 |
11215526621 ps |
| T886 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3696670785 |
|
|
Jul 20 05:04:20 PM PDT 24 |
Jul 20 05:04:29 PM PDT 24 |
690609158 ps |
| T887 |
/workspace/coverage/default/39.sram_ctrl_alert_test.2149781371 |
|
|
Jul 20 05:09:52 PM PDT 24 |
Jul 20 05:09:53 PM PDT 24 |
15357628 ps |
| T888 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4246966760 |
|
|
Jul 20 05:11:55 PM PDT 24 |
Jul 20 05:16:58 PM PDT 24 |
33510627871 ps |
| T889 |
/workspace/coverage/default/40.sram_ctrl_smoke.2907672859 |
|
|
Jul 20 05:09:52 PM PDT 24 |
Jul 20 05:10:03 PM PDT 24 |
1052088391 ps |
| T890 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3247331538 |
|
|
Jul 20 05:01:25 PM PDT 24 |
Jul 20 05:02:32 PM PDT 24 |
193216576 ps |
| T891 |
/workspace/coverage/default/48.sram_ctrl_executable.478809927 |
|
|
Jul 20 05:12:02 PM PDT 24 |
Jul 20 05:26:15 PM PDT 24 |
48323857742 ps |
| T892 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3743103465 |
|
|
Jul 20 05:04:12 PM PDT 24 |
Jul 20 05:04:13 PM PDT 24 |
17799858 ps |
| T893 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4116262893 |
|
|
Jul 20 05:08:27 PM PDT 24 |
Jul 20 05:09:16 PM PDT 24 |
295301366 ps |
| T894 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.349019933 |
|
|
Jul 20 05:12:02 PM PDT 24 |
Jul 20 05:12:03 PM PDT 24 |
389823533 ps |
| T895 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.390639116 |
|
|
Jul 20 05:05:09 PM PDT 24 |
Jul 20 05:09:47 PM PDT 24 |
10154399163 ps |
| T896 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.1515704225 |
|
|
Jul 20 05:08:43 PM PDT 24 |
Jul 20 05:08:50 PM PDT 24 |
364955210 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_executable.3972430620 |
|
|
Jul 20 05:01:27 PM PDT 24 |
Jul 20 05:17:13 PM PDT 24 |
8651215618 ps |
| T898 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3153511040 |
|
|
Jul 20 05:01:04 PM PDT 24 |
Jul 20 05:10:31 PM PDT 24 |
1933555413 ps |
| T899 |
/workspace/coverage/default/2.sram_ctrl_bijection.3802048263 |
|
|
Jul 20 05:01:18 PM PDT 24 |
Jul 20 05:02:30 PM PDT 24 |
5967503572 ps |
| T900 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2013216246 |
|
|
Jul 20 05:03:29 PM PDT 24 |
Jul 20 05:15:54 PM PDT 24 |
3547965902 ps |
| T901 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1577724665 |
|
|
Jul 20 05:02:38 PM PDT 24 |
Jul 20 05:02:42 PM PDT 24 |
169109069 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3472244934 |
|
|
Jul 20 05:07:57 PM PDT 24 |
Jul 20 05:08:39 PM PDT 24 |
2057212692 ps |
| T903 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2807343278 |
|
|
Jul 20 05:11:39 PM PDT 24 |
Jul 20 05:11:51 PM PDT 24 |
602654239 ps |
| T904 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1028552565 |
|
|
Jul 20 05:08:17 PM PDT 24 |
Jul 20 05:11:39 PM PDT 24 |
33306975860 ps |
| T905 |
/workspace/coverage/default/35.sram_ctrl_regwen.2286360304 |
|
|
Jul 20 05:08:42 PM PDT 24 |
Jul 20 05:23:21 PM PDT 24 |
11910059523 ps |
| T906 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1965140944 |
|
|
Jul 20 05:01:32 PM PDT 24 |
Jul 20 05:01:34 PM PDT 24 |
36397715 ps |
| T907 |
/workspace/coverage/default/0.sram_ctrl_smoke.1592754623 |
|
|
Jul 20 05:01:10 PM PDT 24 |
Jul 20 05:03:25 PM PDT 24 |
552231862 ps |
| T908 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.154639688 |
|
|
Jul 20 05:01:20 PM PDT 24 |
Jul 20 05:01:28 PM PDT 24 |
506579273 ps |
| T909 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1501319198 |
|
|
Jul 20 05:06:56 PM PDT 24 |
Jul 20 05:06:57 PM PDT 24 |
22955673 ps |
| T910 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.1993944507 |
|
|
Jul 20 05:06:17 PM PDT 24 |
Jul 20 05:06:23 PM PDT 24 |
1654358076 ps |
| T911 |
/workspace/coverage/default/34.sram_ctrl_bijection.1554736498 |
|
|
Jul 20 05:08:28 PM PDT 24 |
Jul 20 05:08:58 PM PDT 24 |
4704970764 ps |
| T912 |
/workspace/coverage/default/26.sram_ctrl_executable.2231429644 |
|
|
Jul 20 05:06:34 PM PDT 24 |
Jul 20 05:08:15 PM PDT 24 |
8759475950 ps |
| T913 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.833528922 |
|
|
Jul 20 05:06:18 PM PDT 24 |
Jul 20 05:06:23 PM PDT 24 |
266222855 ps |
| T914 |
/workspace/coverage/default/16.sram_ctrl_bijection.1203128508 |
|
|
Jul 20 05:03:30 PM PDT 24 |
Jul 20 05:03:52 PM PDT 24 |
1272819076 ps |
| T915 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.572434899 |
|
|
Jul 20 05:03:17 PM PDT 24 |
Jul 20 05:07:22 PM PDT 24 |
36075375038 ps |
| T916 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.303997735 |
|
|
Jul 20 05:11:47 PM PDT 24 |
Jul 20 05:13:34 PM PDT 24 |
448304578 ps |
| T917 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3825776006 |
|
|
Jul 20 05:11:05 PM PDT 24 |
Jul 20 05:13:59 PM PDT 24 |
1796231571 ps |
| T918 |
/workspace/coverage/default/22.sram_ctrl_stress_all.2295010831 |
|
|
Jul 20 05:05:17 PM PDT 24 |
Jul 20 05:22:43 PM PDT 24 |
14372014510 ps |
| T919 |
/workspace/coverage/default/25.sram_ctrl_executable.1865772872 |
|
|
Jul 20 05:06:15 PM PDT 24 |
Jul 20 05:21:46 PM PDT 24 |
2953284638 ps |
| T920 |
/workspace/coverage/default/21.sram_ctrl_bijection.2508116010 |
|
|
Jul 20 05:04:53 PM PDT 24 |
Jul 20 05:05:20 PM PDT 24 |
6459665782 ps |
| T921 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1914939506 |
|
|
Jul 20 05:07:21 PM PDT 24 |
Jul 20 05:10:14 PM PDT 24 |
1000336624 ps |
| T922 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1960431415 |
|
|
Jul 20 05:12:22 PM PDT 24 |
Jul 20 05:19:31 PM PDT 24 |
2298402835 ps |
| T923 |
/workspace/coverage/default/37.sram_ctrl_alert_test.3612502709 |
|
|
Jul 20 05:09:16 PM PDT 24 |
Jul 20 05:09:17 PM PDT 24 |
11804680 ps |
| T924 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.41834329 |
|
|
Jul 20 05:01:32 PM PDT 24 |
Jul 20 05:01:33 PM PDT 24 |
50241724 ps |
| T925 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1468070082 |
|
|
Jul 20 05:10:01 PM PDT 24 |
Jul 20 05:10:02 PM PDT 24 |
47960159 ps |
| T926 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3029349473 |
|
|
Jul 20 05:02:31 PM PDT 24 |
Jul 20 05:02:35 PM PDT 24 |
128356390 ps |
| T927 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.4278440993 |
|
|
Jul 20 05:04:06 PM PDT 24 |
Jul 20 05:04:16 PM PDT 24 |
241025498 ps |
| T928 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1554744583 |
|
|
Jul 20 05:07:03 PM PDT 24 |
Jul 20 05:09:23 PM PDT 24 |
195873072 ps |
| T76 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1360439111 |
|
|
Jul 20 06:48:35 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
26367746 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.649454144 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:11 PM PDT 24 |
164970474 ps |
| T929 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3294169941 |
|
|
Jul 20 06:48:34 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
67961716 ps |
| T930 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.790206500 |
|
|
Jul 20 06:48:23 PM PDT 24 |
Jul 20 06:48:28 PM PDT 24 |
318105948 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.296880607 |
|
|
Jul 20 06:48:23 PM PDT 24 |
Jul 20 06:48:27 PM PDT 24 |
1580359773 ps |
| T931 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3851312842 |
|
|
Jul 20 06:48:10 PM PDT 24 |
Jul 20 06:48:14 PM PDT 24 |
89172227 ps |
| T86 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3705396997 |
|
|
Jul 20 06:48:22 PM PDT 24 |
Jul 20 06:48:24 PM PDT 24 |
110357527 ps |
| T932 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3991159507 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:28 PM PDT 24 |
52361628 ps |
| T124 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3219148647 |
|
|
Jul 20 06:48:27 PM PDT 24 |
Jul 20 06:48:29 PM PDT 24 |
162438245 ps |
| T933 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1067655166 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:13 PM PDT 24 |
94705402 ps |
| T108 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.301047201 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:26 PM PDT 24 |
20839686 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2056305143 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
438621788 ps |
| T934 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4183205592 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:37 PM PDT 24 |
70798139 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3347380945 |
|
|
Jul 20 06:48:07 PM PDT 24 |
Jul 20 06:48:11 PM PDT 24 |
183193011 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4036293673 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:19 PM PDT 24 |
822272234 ps |
| T117 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.740479442 |
|
|
Jul 20 06:48:07 PM PDT 24 |
Jul 20 06:48:09 PM PDT 24 |
49379628 ps |
| T73 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4294029751 |
|
|
Jul 20 06:48:17 PM PDT 24 |
Jul 20 06:48:22 PM PDT 24 |
2264930035 ps |
| T109 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2885330100 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:26 PM PDT 24 |
40990143 ps |
| T74 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2214093673 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
254309814 ps |
| T936 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1468398122 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:36 PM PDT 24 |
67961991 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.795986992 |
|
|
Jul 20 06:48:39 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
53948690 ps |
| T937 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.765482693 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:32 PM PDT 24 |
601269028 ps |
| T110 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2777215032 |
|
|
Jul 20 06:48:33 PM PDT 24 |
Jul 20 06:48:36 PM PDT 24 |
90606482 ps |
| T938 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3238301158 |
|
|
Jul 20 06:48:33 PM PDT 24 |
Jul 20 06:48:39 PM PDT 24 |
612232928 ps |
| T140 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1708452015 |
|
|
Jul 20 06:48:30 PM PDT 24 |
Jul 20 06:48:32 PM PDT 24 |
97937092 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2758649375 |
|
|
Jul 20 06:48:34 PM PDT 24 |
Jul 20 06:48:40 PM PDT 24 |
943071954 ps |
| T939 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1619981281 |
|
|
Jul 20 06:48:34 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
23667342 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.813714078 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:13 PM PDT 24 |
339955980 ps |
| T941 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1107483781 |
|
|
Jul 20 06:48:18 PM PDT 24 |
Jul 20 06:48:24 PM PDT 24 |
489790411 ps |
| T111 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3670521425 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:35 PM PDT 24 |
15514821 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3443444958 |
|
|
Jul 20 06:48:33 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
3084072340 ps |
| T91 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3327018487 |
|
|
Jul 20 06:48:18 PM PDT 24 |
Jul 20 06:48:22 PM PDT 24 |
1537642127 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3472231233 |
|
|
Jul 20 06:48:20 PM PDT 24 |
Jul 20 06:48:24 PM PDT 24 |
179431502 ps |
| T133 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2366913443 |
|
|
Jul 20 06:48:07 PM PDT 24 |
Jul 20 06:48:10 PM PDT 24 |
346926712 ps |
| T943 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2552516432 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:10 PM PDT 24 |
19133668 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1337823144 |
|
|
Jul 20 06:48:06 PM PDT 24 |
Jul 20 06:48:10 PM PDT 24 |
195232272 ps |
| T944 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2134185532 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:26 PM PDT 24 |
14579494 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1729498237 |
|
|
Jul 20 06:48:31 PM PDT 24 |
Jul 20 06:48:36 PM PDT 24 |
4428241312 ps |
| T93 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1028852241 |
|
|
Jul 20 06:48:33 PM PDT 24 |
Jul 20 06:48:35 PM PDT 24 |
51303841 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.245250468 |
|
|
Jul 20 06:48:10 PM PDT 24 |
Jul 20 06:48:16 PM PDT 24 |
888907121 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2129995043 |
|
|
Jul 20 06:48:17 PM PDT 24 |
Jul 20 06:48:20 PM PDT 24 |
36697808 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1543846132 |
|
|
Jul 20 06:48:17 PM PDT 24 |
Jul 20 06:48:19 PM PDT 24 |
17216521 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1497960987 |
|
|
Jul 20 06:48:15 PM PDT 24 |
Jul 20 06:48:20 PM PDT 24 |
300756638 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3777360411 |
|
|
Jul 20 06:48:35 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
38933893 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.345813433 |
|
|
Jul 20 06:48:30 PM PDT 24 |
Jul 20 06:48:32 PM PDT 24 |
167050334 ps |
| T95 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3963466615 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:17 PM PDT 24 |
17179953 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.28733661 |
|
|
Jul 20 06:48:17 PM PDT 24 |
Jul 20 06:48:21 PM PDT 24 |
808878383 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.656015383 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:35 PM PDT 24 |
22605768 ps |
| T952 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2379940007 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:31 PM PDT 24 |
1073127369 ps |
| T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.842963799 |
|
|
Jul 20 06:48:10 PM PDT 24 |
Jul 20 06:48:14 PM PDT 24 |
83713176 ps |
| T137 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.350942138 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:27 PM PDT 24 |
148051775 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.696639662 |
|
|
Jul 20 06:48:07 PM PDT 24 |
Jul 20 06:48:09 PM PDT 24 |
15195418 ps |
| T954 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.978609443 |
|
|
Jul 20 06:48:35 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
111332482 ps |
| T134 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1809358940 |
|
|
Jul 20 06:48:26 PM PDT 24 |
Jul 20 06:48:29 PM PDT 24 |
335219826 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2659456145 |
|
|
Jul 20 06:48:17 PM PDT 24 |
Jul 20 06:48:18 PM PDT 24 |
15612496 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3876970809 |
|
|
Jul 20 06:48:11 PM PDT 24 |
Jul 20 06:48:13 PM PDT 24 |
66240816 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1158264381 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:28 PM PDT 24 |
1337163833 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1516948319 |
|
|
Jul 20 06:48:07 PM PDT 24 |
Jul 20 06:48:09 PM PDT 24 |
16121665 ps |
| T103 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1130138689 |
|
|
Jul 20 06:48:35 PM PDT 24 |
Jul 20 06:48:41 PM PDT 24 |
878517838 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1818524405 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:18 PM PDT 24 |
248996400 ps |
| T959 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1962873523 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:39 PM PDT 24 |
194349816 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3726076838 |
|
|
Jul 20 06:48:18 PM PDT 24 |
Jul 20 06:48:20 PM PDT 24 |
58980008 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2338474590 |
|
|
Jul 20 06:48:10 PM PDT 24 |
Jul 20 06:48:13 PM PDT 24 |
59702530 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4192668045 |
|
|
Jul 20 06:48:06 PM PDT 24 |
Jul 20 06:48:09 PM PDT 24 |
515250145 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3040710023 |
|
|
Jul 20 06:48:12 PM PDT 24 |
Jul 20 06:48:17 PM PDT 24 |
1664254094 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1078362691 |
|
|
Jul 20 06:48:35 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
60300818 ps |
| T963 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1431972930 |
|
|
Jul 20 06:48:23 PM PDT 24 |
Jul 20 06:48:26 PM PDT 24 |
337501192 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2001750078 |
|
|
Jul 20 06:48:18 PM PDT 24 |
Jul 20 06:48:21 PM PDT 24 |
72253151 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2405318321 |
|
|
Jul 20 06:48:10 PM PDT 24 |
Jul 20 06:48:14 PM PDT 24 |
246182339 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.517952544 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:18 PM PDT 24 |
14469508 ps |
| T138 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2020794476 |
|
|
Jul 20 06:48:22 PM PDT 24 |
Jul 20 06:48:24 PM PDT 24 |
110489812 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1176148288 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:36 PM PDT 24 |
259626764 ps |
| T107 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1737363899 |
|
|
Jul 20 06:48:33 PM PDT 24 |
Jul 20 06:48:39 PM PDT 24 |
856769547 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1200606802 |
|
|
Jul 20 06:48:06 PM PDT 24 |
Jul 20 06:48:09 PM PDT 24 |
43678661 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2136876265 |
|
|
Jul 20 06:48:18 PM PDT 24 |
Jul 20 06:48:20 PM PDT 24 |
36515980 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.834749991 |
|
|
Jul 20 06:48:34 PM PDT 24 |
Jul 20 06:48:37 PM PDT 24 |
15395316 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1416508518 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:28 PM PDT 24 |
42194161 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1943140247 |
|
|
Jul 20 06:48:31 PM PDT 24 |
Jul 20 06:48:33 PM PDT 24 |
14428821 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1703536013 |
|
|
Jul 20 06:48:09 PM PDT 24 |
Jul 20 06:48:14 PM PDT 24 |
264110092 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1281519103 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:11 PM PDT 24 |
35751144 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3896901310 |
|
|
Jul 20 06:48:19 PM PDT 24 |
Jul 20 06:48:21 PM PDT 24 |
17042457 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1444226615 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:27 PM PDT 24 |
64340170 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2485013565 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:10 PM PDT 24 |
48484114 ps |
| T139 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4049299501 |
|
|
Jul 20 06:48:15 PM PDT 24 |
Jul 20 06:48:18 PM PDT 24 |
213245337 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2780145530 |
|
|
Jul 20 06:48:18 PM PDT 24 |
Jul 20 06:48:21 PM PDT 24 |
439026075 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2048788009 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:26 PM PDT 24 |
16898263 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.277418275 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:11 PM PDT 24 |
131121037 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2858184293 |
|
|
Jul 20 06:48:23 PM PDT 24 |
Jul 20 06:48:27 PM PDT 24 |
3822911685 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2175593693 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:18 PM PDT 24 |
102960869 ps |
| T982 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3698421736 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:28 PM PDT 24 |
672444528 ps |
| T983 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1581471386 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:36 PM PDT 24 |
490112679 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1941772441 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:18 PM PDT 24 |
28527551 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1551745698 |
|
|
Jul 20 06:48:10 PM PDT 24 |
Jul 20 06:48:13 PM PDT 24 |
31623689 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1845109816 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:29 PM PDT 24 |
297487821 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1698869977 |
|
|
Jul 20 06:48:07 PM PDT 24 |
Jul 20 06:48:09 PM PDT 24 |
115025646 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1070647402 |
|
|
Jul 20 06:48:33 PM PDT 24 |
Jul 20 06:48:38 PM PDT 24 |
178579474 ps |
| T989 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2720478368 |
|
|
Jul 20 06:48:26 PM PDT 24 |
Jul 20 06:48:31 PM PDT 24 |
1136287100 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2767093636 |
|
|
Jul 20 06:48:09 PM PDT 24 |
Jul 20 06:48:12 PM PDT 24 |
61109752 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.269076950 |
|
|
Jul 20 06:48:24 PM PDT 24 |
Jul 20 06:48:25 PM PDT 24 |
182936177 ps |
| T992 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1822156302 |
|
|
Jul 20 06:48:32 PM PDT 24 |
Jul 20 06:48:34 PM PDT 24 |
19474583 ps |
| T993 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.272253928 |
|
|
Jul 20 06:48:31 PM PDT 24 |
Jul 20 06:48:32 PM PDT 24 |
33541292 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.922943813 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:27 PM PDT 24 |
14501632 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1553993917 |
|
|
Jul 20 06:48:20 PM PDT 24 |
Jul 20 06:48:22 PM PDT 24 |
55734531 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1798682226 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:11 PM PDT 24 |
55909662 ps |
| T997 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3574451790 |
|
|
Jul 20 06:48:26 PM PDT 24 |
Jul 20 06:48:28 PM PDT 24 |
88819185 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3843690149 |
|
|
Jul 20 06:48:16 PM PDT 24 |
Jul 20 06:48:17 PM PDT 24 |
26174969 ps |
| T999 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4192876293 |
|
|
Jul 20 06:48:25 PM PDT 24 |
Jul 20 06:48:26 PM PDT 24 |
30069455 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.737580517 |
|
|
Jul 20 06:48:12 PM PDT 24 |
Jul 20 06:48:14 PM PDT 24 |
24765095 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.217341226 |
|
|
Jul 20 06:48:08 PM PDT 24 |
Jul 20 06:48:10 PM PDT 24 |
18729765 ps |