Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145209246	1			T1	12284		T2	587748		T3	440670
instr_valid_dis	112825707	1			T1	12284		T2	587748		T3	440670
instr_en	20412017	1			T6	132954		T20	560762		T28	113340

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12749116	1			T6	16504		T20	605884		T28	78084
sram_ifetch_valid_disable	111943081	1			T1	12284		T2	587748		T3	440670
sram_ifetch_enable	20517049	1			T12	24798		T6	187762		T20	27078

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145209246	1			T1	12284		T2	587748		T3	440670
hw_debug_en_valid_off	110670305	1			T1	12284		T2	587748		T3	440670
hw_debug_en_on	23960623	1			T6	132954		T20	614576		T28	171948

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111943081	1			T1	12284		T2	587748		T3	440670
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	98325407	1			T1	12284		T2	587748		T3	440670
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8270344	1			T20	92196		T28	36182		T124	43302
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4835060	1			T6	16504		T20	62518		T28	25176
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2441582	1			T6	16504		T20	62518		T28	17544
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1641692	1			T28	714		T62	83588		T74	96706
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5974626	1			T20	543366		T28	52908		T124	57214
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2053268	1			T20	44894		T28	52908		T124	23222
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2484592	1			T20	468566		T124	33992		T22	21802
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9310568	1			T20	71210		T28	18408		T27	31172
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3926662	1			T20	20066		T28	18408		T27	31172
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3355602	1			T20	51144		T124	43302		T22	11056

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7275129	1			T6	132954		T28	76444		T124	68768
lc_exec_en	8675429	1			T6	132954		T28	100632		T27	39654
valid_exec_dis	106894133	1			T1	12284		T2	587748		T3	440670
invalid_exec_dis	33266165	1			T12	24798		T6	204266		T20	632962