Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43437531	1			T1	6142		T2	267115		T3	39977
triple_byte_access	2421131	1			T2	5381		T3	36008		T9	145
halfword_access	3632832	1			T2	8101		T3	54394		T9	201
byte_access	4852925	1			T2	10662		T3	71722		T9	379
zero_access	1220063	1			T2	2615		T3	18234		T9	174

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27725808

1

T1

2048

T2

146796

T3

110146

auto[1]

27838674

1

T1

4094

T2

147078

T3

110189

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21668939	1			T1	2048		T2	133548		T3	19978
auto[0]	triple_byte_access	1207482	1			T2	2618		T3	17991		T9	22
auto[0]	halfword_access	1811923	1			T2	4043		T3	27052		T9	53
auto[0]	byte_access	2423604	1			T2	5305		T3	35949		T9	165
auto[0]	zero_access	613860	1			T2	1282		T3	9176		T9	124
auto[1]	word_access	21768592	1			T1	4094		T2	133567		T3	19999
auto[1]	triple_byte_access	1213649	1			T2	2763		T3	18017		T9	123
auto[1]	halfword_access	1820909	1			T2	4058		T3	27342		T9	148
auto[1]	byte_access	2429321	1			T2	5357		T3	35773		T9	214
auto[1]	zero_access	606203	1			T2	1333		T3	9058		T9	50