Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	139506612	1			T1	434070		T2	506334		T4	15096
instr_valid_dis	107874892	1			T1	434070		T2	506334		T4	15096
instr_en	23509719	1			T13	60528		T24	21192		T28	217248

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9978005	1			T13	102884		T24	46248		T28	81576
sram_ifetch_valid_disable	110959758	1			T1	434070		T2	506334		T4	15096
sram_ifetch_enable	18568849	1			T13	8386		T24	18098		T28	215026

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	139506612	1			T1	434070		T2	506334		T4	15096
hw_debug_en_valid_off	110874305	1			T1	434070		T2	506334		T4	15096
hw_debug_en_on	19238643	1			T13	21908		T24	61884		T28	242990

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110959758	1			T1	434070		T2	506334		T4	15096
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	97804524	1			T1	434070		T2	506334		T4	15096
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9424589	1			T24	468		T28	106344		T23	12904
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4386593	1			T13	31350		T24	2626		T28	28044
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1480916	1			T19	44292		T69	21594		T144	54120
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2498735	1			T13	31350		T24	2626		T28	28044
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3580618	1			T13	21908		T24	43622		T28	53532
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1017480	1			T13	18740		T24	43622		T19	11956
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1915214	1			T13	3168		T28	53532		T140	120
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8105525	1			T24	18262		T28	108004		T63	764
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2905679	1			T24	18262		T27	53076		T19	107804
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3648782	1			T28	24074		T140	20958		T144	11868

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8697579	1			T13	8386		T24	18098		T28	29328
lc_exec_en	7552500	1			T28	81454		T19	29108		T7	15740
valid_exec_dis	105905090	1			T1	434070		T2	506334		T4	15096
invalid_exec_dis	28546854	1			T13	111270		T24	64346		T28	296602