Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	41469155	1			T1	197323		T2	45959		T4	4516
triple_byte_access	2627171	1			T1	3974		T2	41678		T4	94
halfword_access	3946855	1			T1	5884		T2	62365		T4	149
byte_access	5269525	1			T1	7864		T2	82248		T4	165
zero_access	1326963	1			T1	1990		T2	20917		T4	47

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27273360

1

T1

108724

T2

126644

T4

2510

auto[1]

27366309

1

T1

108311

T2

126523

T4

2461

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	20689943	1			T1	98819		T2	22852		T4	2264
auto[0]	triple_byte_access	1311739	1			T1	2006		T2	20853		T4	56
auto[0]	halfword_access	1969518	1			T1	2912		T2	31236		T4	79
auto[0]	byte_access	2634784	1			T1	3979		T2	41125		T4	91
auto[0]	zero_access	667376	1			T1	1008		T2	10578		T4	20
auto[1]	word_access	20779212	1			T1	98504		T2	23107		T4	2252
auto[1]	triple_byte_access	1315432	1			T1	1968		T2	20825		T4	38
auto[1]	halfword_access	1977337	1			T1	2972		T2	31129		T4	70
auto[1]	byte_access	2634741	1			T1	3885		T2	41123		T4	74
auto[1]	zero_access	659587	1			T1	982		T2	10339		T4	27