| T792 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.777131147 |
|
|
Jul 22 06:53:08 PM PDT 24 |
Jul 22 06:56:35 PM PDT 24 |
1625878159 ps |
| T793 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2836603573 |
|
|
Jul 22 06:53:38 PM PDT 24 |
Jul 22 06:54:56 PM PDT 24 |
11571015 ps |
| T794 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.829078003 |
|
|
Jul 22 06:54:50 PM PDT 24 |
Jul 22 06:56:07 PM PDT 24 |
1550418622 ps |
| T795 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.2413367850 |
|
|
Jul 22 06:55:00 PM PDT 24 |
Jul 22 06:56:12 PM PDT 24 |
66007620 ps |
| T796 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4194234629 |
|
|
Jul 22 06:51:26 PM PDT 24 |
Jul 22 06:52:24 PM PDT 24 |
1538333606 ps |
| T797 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1501005199 |
|
|
Jul 22 06:51:28 PM PDT 24 |
Jul 22 06:52:45 PM PDT 24 |
328570102 ps |
| T798 |
/workspace/coverage/default/28.sram_ctrl_alert_test.2682087377 |
|
|
Jul 22 06:53:49 PM PDT 24 |
Jul 22 06:55:07 PM PDT 24 |
44816502 ps |
| T799 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.706979476 |
|
|
Jul 22 06:53:17 PM PDT 24 |
Jul 22 07:01:51 PM PDT 24 |
5712187946 ps |
| T800 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2049368522 |
|
|
Jul 22 06:52:34 PM PDT 24 |
Jul 22 06:53:37 PM PDT 24 |
51665350 ps |
| T801 |
/workspace/coverage/default/17.sram_ctrl_bijection.1352439114 |
|
|
Jul 22 06:53:08 PM PDT 24 |
Jul 22 06:54:50 PM PDT 24 |
6302173763 ps |
| T802 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2260132741 |
|
|
Jul 22 06:55:37 PM PDT 24 |
Jul 22 06:56:35 PM PDT 24 |
178047664 ps |
| T803 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3866956947 |
|
|
Jul 22 06:54:58 PM PDT 24 |
Jul 22 06:59:49 PM PDT 24 |
2289866838 ps |
| T804 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2073142409 |
|
|
Jul 22 06:54:42 PM PDT 24 |
Jul 22 07:00:39 PM PDT 24 |
4739262922 ps |
| T805 |
/workspace/coverage/default/0.sram_ctrl_executable.3878633937 |
|
|
Jul 22 06:50:49 PM PDT 24 |
Jul 22 07:06:32 PM PDT 24 |
66660781378 ps |
| T806 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1395354836 |
|
|
Jul 22 06:50:47 PM PDT 24 |
Jul 22 06:51:25 PM PDT 24 |
399955462 ps |
| T807 |
/workspace/coverage/default/7.sram_ctrl_executable.3069966807 |
|
|
Jul 22 06:52:35 PM PDT 24 |
Jul 22 06:58:32 PM PDT 24 |
2185616196 ps |
| T808 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3769523786 |
|
|
Jul 22 06:55:48 PM PDT 24 |
Jul 22 06:58:13 PM PDT 24 |
257844495 ps |
| T809 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2569819628 |
|
|
Jul 22 06:51:03 PM PDT 24 |
Jul 22 06:51:53 PM PDT 24 |
74576530 ps |
| T810 |
/workspace/coverage/default/11.sram_ctrl_bijection.4081049890 |
|
|
Jul 22 06:52:34 PM PDT 24 |
Jul 22 06:53:51 PM PDT 24 |
226712944 ps |
| T811 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2771896318 |
|
|
Jul 22 06:50:52 PM PDT 24 |
Jul 22 06:58:50 PM PDT 24 |
23247138880 ps |
| T812 |
/workspace/coverage/default/17.sram_ctrl_regwen.1105907125 |
|
|
Jul 22 06:54:15 PM PDT 24 |
Jul 22 06:55:55 PM PDT 24 |
485388822 ps |
| T117 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2521535233 |
|
|
Jul 22 06:53:42 PM PDT 24 |
Jul 22 06:55:19 PM PDT 24 |
1679297859 ps |
| T813 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1584061591 |
|
|
Jul 22 06:56:27 PM PDT 24 |
Jul 22 06:56:57 PM PDT 24 |
45285180 ps |
| T814 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.102730848 |
|
|
Jul 22 06:53:14 PM PDT 24 |
Jul 22 07:14:40 PM PDT 24 |
3412309345 ps |
| T815 |
/workspace/coverage/default/21.sram_ctrl_partial_access.4196911977 |
|
|
Jul 22 06:53:24 PM PDT 24 |
Jul 22 06:54:52 PM PDT 24 |
737236658 ps |
| T816 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.662495525 |
|
|
Jul 22 06:53:26 PM PDT 24 |
Jul 22 06:54:51 PM PDT 24 |
2275047806 ps |
| T817 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2111110446 |
|
|
Jul 22 06:53:17 PM PDT 24 |
Jul 22 07:23:27 PM PDT 24 |
13605851693 ps |
| T818 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1374280008 |
|
|
Jul 22 06:51:25 PM PDT 24 |
Jul 22 07:26:31 PM PDT 24 |
24638643196 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.4121088180 |
|
|
Jul 22 06:53:26 PM PDT 24 |
Jul 22 06:55:27 PM PDT 24 |
448031468 ps |
| T820 |
/workspace/coverage/default/13.sram_ctrl_regwen.1008258629 |
|
|
Jul 22 06:52:47 PM PDT 24 |
Jul 22 06:55:25 PM PDT 24 |
699937317 ps |
| T821 |
/workspace/coverage/default/10.sram_ctrl_bijection.1193857701 |
|
|
Jul 22 06:52:34 PM PDT 24 |
Jul 22 06:54:22 PM PDT 24 |
875406334 ps |
| T822 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1000735782 |
|
|
Jul 22 06:52:51 PM PDT 24 |
Jul 22 06:54:26 PM PDT 24 |
87970364 ps |
| T33 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2674622169 |
|
|
Jul 22 06:51:01 PM PDT 24 |
Jul 22 06:51:47 PM PDT 24 |
116417772 ps |
| T823 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.4150400495 |
|
|
Jul 22 06:55:45 PM PDT 24 |
Jul 22 06:56:38 PM PDT 24 |
277107480 ps |
| T824 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.218283453 |
|
|
Jul 22 06:50:51 PM PDT 24 |
Jul 22 06:51:35 PM PDT 24 |
1342908123 ps |
| T825 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2295188837 |
|
|
Jul 22 06:52:38 PM PDT 24 |
Jul 22 06:53:47 PM PDT 24 |
316143126 ps |
| T826 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3117214523 |
|
|
Jul 22 06:54:23 PM PDT 24 |
Jul 22 06:56:19 PM PDT 24 |
204698917 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.461015724 |
|
|
Jul 22 06:55:24 PM PDT 24 |
Jul 22 06:56:30 PM PDT 24 |
1867476119 ps |
| T828 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2957452901 |
|
|
Jul 22 06:53:41 PM PDT 24 |
Jul 22 07:04:50 PM PDT 24 |
10684350309 ps |
| T829 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3628578193 |
|
|
Jul 22 06:53:28 PM PDT 24 |
Jul 22 06:54:51 PM PDT 24 |
752729572 ps |
| T830 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1018491658 |
|
|
Jul 22 06:52:51 PM PDT 24 |
Jul 22 06:54:33 PM PDT 24 |
111394528 ps |
| T831 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2584928502 |
|
|
Jul 22 06:53:42 PM PDT 24 |
Jul 22 06:58:19 PM PDT 24 |
9458022286 ps |
| T832 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2597162258 |
|
|
Jul 22 06:53:52 PM PDT 24 |
Jul 22 06:55:16 PM PDT 24 |
1759731074 ps |
| T833 |
/workspace/coverage/default/24.sram_ctrl_regwen.3443638094 |
|
|
Jul 22 06:53:28 PM PDT 24 |
Jul 22 07:09:21 PM PDT 24 |
2177506798 ps |
| T834 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2221958252 |
|
|
Jul 22 06:52:32 PM PDT 24 |
Jul 22 06:53:33 PM PDT 24 |
24855650 ps |
| T835 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.475093731 |
|
|
Jul 22 06:53:51 PM PDT 24 |
Jul 22 06:55:14 PM PDT 24 |
1303374521 ps |
| T836 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.1361588705 |
|
|
Jul 22 06:54:25 PM PDT 24 |
Jul 22 06:55:47 PM PDT 24 |
435307732 ps |
| T837 |
/workspace/coverage/default/41.sram_ctrl_bijection.3599083257 |
|
|
Jul 22 06:55:26 PM PDT 24 |
Jul 22 06:57:30 PM PDT 24 |
13725536704 ps |
| T838 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2861529219 |
|
|
Jul 22 06:53:33 PM PDT 24 |
Jul 22 07:16:58 PM PDT 24 |
87797556273 ps |
| T839 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1772312218 |
|
|
Jul 22 06:53:52 PM PDT 24 |
Jul 22 06:55:14 PM PDT 24 |
926569578 ps |
| T840 |
/workspace/coverage/default/14.sram_ctrl_alert_test.1281332326 |
|
|
Jul 22 06:53:08 PM PDT 24 |
Jul 22 06:54:20 PM PDT 24 |
14537025 ps |
| T841 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2828625120 |
|
|
Jul 22 06:55:38 PM PDT 24 |
Jul 22 06:56:34 PM PDT 24 |
28747130 ps |
| T842 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1976924538 |
|
|
Jul 22 06:52:32 PM PDT 24 |
Jul 22 06:55:58 PM PDT 24 |
8390894354 ps |
| T843 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2773847595 |
|
|
Jul 22 06:54:15 PM PDT 24 |
Jul 22 06:55:42 PM PDT 24 |
135721518 ps |
| T844 |
/workspace/coverage/default/33.sram_ctrl_bijection.867934953 |
|
|
Jul 22 06:53:57 PM PDT 24 |
Jul 22 06:55:52 PM PDT 24 |
22836608285 ps |
| T845 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3043302568 |
|
|
Jul 22 06:56:18 PM PDT 24 |
Jul 22 06:57:03 PM PDT 24 |
765512448 ps |
| T846 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1946608315 |
|
|
Jul 22 06:55:10 PM PDT 24 |
Jul 22 06:56:20 PM PDT 24 |
523545380 ps |
| T847 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.52694032 |
|
|
Jul 22 06:53:28 PM PDT 24 |
Jul 22 06:54:44 PM PDT 24 |
40988113 ps |
| T848 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3985656878 |
|
|
Jul 22 06:54:23 PM PDT 24 |
Jul 22 06:56:46 PM PDT 24 |
190438925 ps |
| T849 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.914659562 |
|
|
Jul 22 06:53:09 PM PDT 24 |
Jul 22 06:58:23 PM PDT 24 |
6356216441 ps |
| T850 |
/workspace/coverage/default/36.sram_ctrl_regwen.2908262480 |
|
|
Jul 22 06:54:49 PM PDT 24 |
Jul 22 07:04:37 PM PDT 24 |
35802806849 ps |
| T851 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.54007417 |
|
|
Jul 22 06:53:21 PM PDT 24 |
Jul 22 06:54:41 PM PDT 24 |
571065666 ps |
| T852 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.4281602788 |
|
|
Jul 22 06:53:39 PM PDT 24 |
Jul 22 06:54:57 PM PDT 24 |
43308567 ps |
| T853 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2692977748 |
|
|
Jul 22 06:53:49 PM PDT 24 |
Jul 22 07:06:40 PM PDT 24 |
4958378515 ps |
| T854 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3137649707 |
|
|
Jul 22 06:53:40 PM PDT 24 |
Jul 22 07:05:58 PM PDT 24 |
2938614417 ps |
| T855 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2320666579 |
|
|
Jul 22 06:53:33 PM PDT 24 |
Jul 22 06:55:21 PM PDT 24 |
317129744 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.969563725 |
|
|
Jul 22 06:53:13 PM PDT 24 |
Jul 22 07:00:27 PM PDT 24 |
54585777840 ps |
| T857 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.671867010 |
|
|
Jul 22 06:53:15 PM PDT 24 |
Jul 22 07:16:16 PM PDT 24 |
36081894567 ps |
| T858 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2192068256 |
|
|
Jul 22 06:52:29 PM PDT 24 |
Jul 22 06:58:10 PM PDT 24 |
8342806674 ps |
| T859 |
/workspace/coverage/default/5.sram_ctrl_regwen.2518565609 |
|
|
Jul 22 06:51:23 PM PDT 24 |
Jul 22 06:56:45 PM PDT 24 |
7599442499 ps |
| T860 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1632547987 |
|
|
Jul 22 06:54:22 PM PDT 24 |
Jul 22 06:55:46 PM PDT 24 |
898203834 ps |
| T861 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1543896329 |
|
|
Jul 22 06:53:42 PM PDT 24 |
Jul 22 06:55:00 PM PDT 24 |
49800361 ps |
| T862 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3813184869 |
|
|
Jul 22 06:55:35 PM PDT 24 |
Jul 22 06:56:39 PM PDT 24 |
1330084000 ps |
| T863 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1181344448 |
|
|
Jul 22 06:55:55 PM PDT 24 |
Jul 22 06:57:16 PM PDT 24 |
125456060 ps |
| T864 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3376306348 |
|
|
Jul 22 06:50:53 PM PDT 24 |
Jul 22 06:58:30 PM PDT 24 |
16233119066 ps |
| T865 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1086589997 |
|
|
Jul 22 06:54:36 PM PDT 24 |
Jul 22 07:05:34 PM PDT 24 |
26406428091 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3074067159 |
|
|
Jul 22 06:53:14 PM PDT 24 |
Jul 22 06:59:17 PM PDT 24 |
1067349188 ps |
| T867 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.6344269 |
|
|
Jul 22 06:51:30 PM PDT 24 |
Jul 22 06:56:51 PM PDT 24 |
3929002587 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2503438918 |
|
|
Jul 22 06:53:52 PM PDT 24 |
Jul 22 06:55:11 PM PDT 24 |
45564272 ps |
| T869 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.246663321 |
|
|
Jul 22 06:52:53 PM PDT 24 |
Jul 22 06:54:05 PM PDT 24 |
915018321 ps |
| T870 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3423614072 |
|
|
Jul 22 06:52:53 PM PDT 24 |
Jul 22 06:59:29 PM PDT 24 |
4199476759 ps |
| T871 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1467900274 |
|
|
Jul 22 06:52:17 PM PDT 24 |
Jul 22 07:11:37 PM PDT 24 |
48182799620 ps |
| T872 |
/workspace/coverage/default/6.sram_ctrl_regwen.2491616846 |
|
|
Jul 22 06:51:38 PM PDT 24 |
Jul 22 07:06:17 PM PDT 24 |
15356576535 ps |
| T873 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1906017568 |
|
|
Jul 22 06:55:11 PM PDT 24 |
Jul 22 07:00:13 PM PDT 24 |
4638040775 ps |
| T874 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3320179730 |
|
|
Jul 22 06:55:37 PM PDT 24 |
Jul 22 07:00:53 PM PDT 24 |
5385742991 ps |
| T875 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2229141574 |
|
|
Jul 22 06:51:21 PM PDT 24 |
Jul 22 07:02:05 PM PDT 24 |
10175824068 ps |
| T876 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.4129685517 |
|
|
Jul 22 06:55:35 PM PDT 24 |
Jul 22 07:05:47 PM PDT 24 |
11691424916 ps |
| T877 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1620513324 |
|
|
Jul 22 06:54:23 PM PDT 24 |
Jul 22 06:55:40 PM PDT 24 |
25802605 ps |
| T878 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1989295764 |
|
|
Jul 22 06:53:34 PM PDT 24 |
Jul 22 06:54:51 PM PDT 24 |
14137502 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2888755776 |
|
|
Jul 22 06:55:57 PM PDT 24 |
Jul 22 06:57:47 PM PDT 24 |
2236277563 ps |
| T880 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3368572376 |
|
|
Jul 22 06:55:15 PM PDT 24 |
Jul 22 06:56:20 PM PDT 24 |
99543679 ps |
| T881 |
/workspace/coverage/default/28.sram_ctrl_executable.2531401349 |
|
|
Jul 22 06:55:55 PM PDT 24 |
Jul 22 07:08:31 PM PDT 24 |
5086872477 ps |
| T882 |
/workspace/coverage/default/21.sram_ctrl_executable.3278706095 |
|
|
Jul 22 06:53:29 PM PDT 24 |
Jul 22 07:04:37 PM PDT 24 |
8081664872 ps |
| T883 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3298295773 |
|
|
Jul 22 06:54:21 PM PDT 24 |
Jul 22 07:30:01 PM PDT 24 |
62117737933 ps |
| T884 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1485105746 |
|
|
Jul 22 06:55:57 PM PDT 24 |
Jul 22 06:56:45 PM PDT 24 |
28218842 ps |
| T885 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.179810759 |
|
|
Jul 22 06:52:31 PM PDT 24 |
Jul 22 06:55:01 PM PDT 24 |
126288073 ps |
| T886 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.4278671939 |
|
|
Jul 22 06:53:33 PM PDT 24 |
Jul 22 06:55:01 PM PDT 24 |
2109930852 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_bijection.1777590211 |
|
|
Jul 22 06:53:34 PM PDT 24 |
Jul 22 06:56:03 PM PDT 24 |
6410748521 ps |
| T888 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1504983356 |
|
|
Jul 22 06:51:33 PM PDT 24 |
Jul 22 06:52:32 PM PDT 24 |
447238645 ps |
| T889 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3228862692 |
|
|
Jul 22 06:56:01 PM PDT 24 |
Jul 22 06:57:14 PM PDT 24 |
859585972 ps |
| T890 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3317311542 |
|
|
Jul 22 06:52:34 PM PDT 24 |
Jul 22 07:09:43 PM PDT 24 |
56884459053 ps |
| T891 |
/workspace/coverage/default/43.sram_ctrl_regwen.2626645707 |
|
|
Jul 22 06:57:22 PM PDT 24 |
Jul 22 07:23:53 PM PDT 24 |
39592963704 ps |
| T892 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1266734330 |
|
|
Jul 22 06:55:45 PM PDT 24 |
Jul 22 07:23:04 PM PDT 24 |
82989365497 ps |
| T893 |
/workspace/coverage/default/39.sram_ctrl_executable.2704562675 |
|
|
Jul 22 06:55:13 PM PDT 24 |
Jul 22 07:04:08 PM PDT 24 |
6426805941 ps |
| T894 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3453906183 |
|
|
Jul 22 06:53:34 PM PDT 24 |
Jul 22 06:58:50 PM PDT 24 |
38801656778 ps |
| T895 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2637707600 |
|
|
Jul 22 06:53:50 PM PDT 24 |
Jul 22 07:11:49 PM PDT 24 |
25648016185 ps |
| T896 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.476812950 |
|
|
Jul 22 06:53:57 PM PDT 24 |
Jul 22 06:55:13 PM PDT 24 |
49791303 ps |
| T897 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1029226235 |
|
|
Jul 22 06:54:21 PM PDT 24 |
Jul 22 07:01:54 PM PDT 24 |
7459271871 ps |
| T898 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1416660537 |
|
|
Jul 22 06:55:37 PM PDT 24 |
Jul 22 06:57:56 PM PDT 24 |
357488519 ps |
| T899 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1246134223 |
|
|
Jul 22 06:53:52 PM PDT 24 |
Jul 22 06:55:12 PM PDT 24 |
377530888 ps |
| T900 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3339781405 |
|
|
Jul 22 06:55:57 PM PDT 24 |
Jul 22 07:00:15 PM PDT 24 |
2338120547 ps |
| T901 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.845769885 |
|
|
Jul 22 06:52:33 PM PDT 24 |
Jul 22 06:56:08 PM PDT 24 |
11696904750 ps |
| T902 |
/workspace/coverage/default/48.sram_ctrl_smoke.2228825413 |
|
|
Jul 22 06:56:37 PM PDT 24 |
Jul 22 06:57:14 PM PDT 24 |
1288296789 ps |
| T903 |
/workspace/coverage/default/34.sram_ctrl_bijection.4064621083 |
|
|
Jul 22 06:54:24 PM PDT 24 |
Jul 22 06:56:41 PM PDT 24 |
10492910658 ps |
| T904 |
/workspace/coverage/default/25.sram_ctrl_smoke.1919000864 |
|
|
Jul 22 06:53:28 PM PDT 24 |
Jul 22 06:54:56 PM PDT 24 |
729136314 ps |
| T905 |
/workspace/coverage/default/46.sram_ctrl_smoke.148915731 |
|
|
Jul 22 06:56:01 PM PDT 24 |
Jul 22 06:56:50 PM PDT 24 |
82641004 ps |
| T906 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2181948225 |
|
|
Jul 22 06:50:48 PM PDT 24 |
Jul 22 06:51:33 PM PDT 24 |
141772586 ps |
| T907 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2529328270 |
|
|
Jul 22 06:54:50 PM PDT 24 |
Jul 22 06:56:08 PM PDT 24 |
683481562 ps |
| T908 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.979900346 |
|
|
Jul 22 06:55:55 PM PDT 24 |
Jul 22 06:56:46 PM PDT 24 |
143862262 ps |
| T909 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2710504186 |
|
|
Jul 22 06:53:10 PM PDT 24 |
Jul 22 06:54:30 PM PDT 24 |
675261823 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3776220613 |
|
|
Jul 22 06:56:00 PM PDT 24 |
Jul 22 06:57:47 PM PDT 24 |
137595850 ps |
| T118 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.347310443 |
|
|
Jul 22 06:52:52 PM PDT 24 |
Jul 22 06:54:30 PM PDT 24 |
1182771725 ps |
| T911 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1930418183 |
|
|
Jul 22 06:54:59 PM PDT 24 |
Jul 22 06:56:27 PM PDT 24 |
141871933 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2986029729 |
|
|
Jul 22 06:51:40 PM PDT 24 |
Jul 22 06:52:43 PM PDT 24 |
342375648 ps |
| T913 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4119290671 |
|
|
Jul 22 06:53:24 PM PDT 24 |
Jul 22 06:56:21 PM PDT 24 |
8286222815 ps |
| T914 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3496154892 |
|
|
Jul 22 06:57:23 PM PDT 24 |
Jul 22 06:57:29 PM PDT 24 |
26947882 ps |
| T915 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.78958232 |
|
|
Jul 22 06:52:35 PM PDT 24 |
Jul 22 06:53:40 PM PDT 24 |
657481215 ps |
| T916 |
/workspace/coverage/default/32.sram_ctrl_regwen.3279817421 |
|
|
Jul 22 06:54:10 PM PDT 24 |
Jul 22 06:58:16 PM PDT 24 |
7061821092 ps |
| T917 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1963455139 |
|
|
Jul 22 06:52:50 PM PDT 24 |
Jul 22 07:00:47 PM PDT 24 |
16282756609 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1026673775 |
|
|
Jul 22 06:51:24 PM PDT 24 |
Jul 22 06:52:17 PM PDT 24 |
29560717 ps |
| T919 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2582717647 |
|
|
Jul 22 06:53:24 PM PDT 24 |
Jul 22 07:01:51 PM PDT 24 |
1847800092 ps |
| T920 |
/workspace/coverage/default/45.sram_ctrl_regwen.560239156 |
|
|
Jul 22 06:55:44 PM PDT 24 |
Jul 22 06:57:03 PM PDT 24 |
879016831 ps |
| T921 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1404134593 |
|
|
Jul 22 06:53:14 PM PDT 24 |
Jul 22 06:56:48 PM PDT 24 |
710136407 ps |
| T922 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.494684309 |
|
|
Jul 22 06:53:27 PM PDT 24 |
Jul 22 06:54:47 PM PDT 24 |
244378555 ps |
| T923 |
/workspace/coverage/default/21.sram_ctrl_stress_all.540790363 |
|
|
Jul 22 06:53:24 PM PDT 24 |
Jul 22 07:36:05 PM PDT 24 |
9079263746 ps |
| T924 |
/workspace/coverage/default/9.sram_ctrl_partial_access.293745999 |
|
|
Jul 22 06:52:30 PM PDT 24 |
Jul 22 06:53:50 PM PDT 24 |
6526302989 ps |
| T925 |
/workspace/coverage/default/37.sram_ctrl_alert_test.2821049500 |
|
|
Jul 22 06:54:58 PM PDT 24 |
Jul 22 06:56:09 PM PDT 24 |
14771026 ps |
| T926 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1281855325 |
|
|
Jul 22 06:55:39 PM PDT 24 |
Jul 22 06:56:35 PM PDT 24 |
22296742 ps |
| T927 |
/workspace/coverage/default/20.sram_ctrl_smoke.2764395167 |
|
|
Jul 22 06:54:26 PM PDT 24 |
Jul 22 06:55:57 PM PDT 24 |
467522711 ps |
| T928 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2004185432 |
|
|
Jul 22 06:53:20 PM PDT 24 |
Jul 22 06:54:32 PM PDT 24 |
29320747 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3907810760 |
|
|
Jul 22 06:56:09 PM PDT 24 |
Jul 22 07:03:24 PM PDT 24 |
21523501529 ps |
| T74 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2366502587 |
|
|
Jul 22 06:20:33 PM PDT 24 |
Jul 22 06:20:36 PM PDT 24 |
28700950 ps |
| T930 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2441499979 |
|
|
Jul 22 06:20:38 PM PDT 24 |
Jul 22 06:20:40 PM PDT 24 |
31942372 ps |
| T931 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4232969533 |
|
|
Jul 22 06:20:34 PM PDT 24 |
Jul 22 06:20:41 PM PDT 24 |
140265693 ps |
| T75 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2756431820 |
|
|
Jul 22 06:20:32 PM PDT 24 |
Jul 22 06:20:36 PM PDT 24 |
206482566 ps |
| T76 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3709433844 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:33 PM PDT 24 |
16697137 ps |
| T83 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1239024611 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:33 PM PDT 24 |
13913308 ps |
| T932 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4167779070 |
|
|
Jul 22 06:20:33 PM PDT 24 |
Jul 22 06:20:39 PM PDT 24 |
244034616 ps |
| T933 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2156473294 |
|
|
Jul 22 06:20:22 PM PDT 24 |
Jul 22 06:20:24 PM PDT 24 |
32402305 ps |
| T66 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2804490303 |
|
|
Jul 22 06:20:45 PM PDT 24 |
Jul 22 06:20:46 PM PDT 24 |
213466059 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.648308040 |
|
|
Jul 22 06:21:06 PM PDT 24 |
Jul 22 06:21:07 PM PDT 24 |
57695545 ps |
| T85 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.731127803 |
|
|
Jul 22 06:20:30 PM PDT 24 |
Jul 22 06:20:33 PM PDT 24 |
831539034 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.777124423 |
|
|
Jul 22 06:20:18 PM PDT 24 |
Jul 22 06:20:22 PM PDT 24 |
206687398 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2608188623 |
|
|
Jul 22 06:20:16 PM PDT 24 |
Jul 22 06:20:19 PM PDT 24 |
86347551 ps |
| T86 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1275775891 |
|
|
Jul 22 06:20:38 PM PDT 24 |
Jul 22 06:20:40 PM PDT 24 |
43223542 ps |
| T131 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2382348005 |
|
|
Jul 22 06:20:24 PM PDT 24 |
Jul 22 06:20:27 PM PDT 24 |
580375160 ps |
| T133 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2793107586 |
|
|
Jul 22 06:20:33 PM PDT 24 |
Jul 22 06:20:36 PM PDT 24 |
79335738 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.16891392 |
|
|
Jul 22 06:22:12 PM PDT 24 |
Jul 22 06:22:16 PM PDT 24 |
377003612 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1820433017 |
|
|
Jul 22 06:22:38 PM PDT 24 |
Jul 22 06:22:40 PM PDT 24 |
44379524 ps |
| T88 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1272098470 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:31 PM PDT 24 |
79527214 ps |
| T934 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3486264203 |
|
|
Jul 22 06:20:35 PM PDT 24 |
Jul 22 06:20:38 PM PDT 24 |
56644425 ps |
| T935 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.959216362 |
|
|
Jul 22 06:20:25 PM PDT 24 |
Jul 22 06:20:27 PM PDT 24 |
58391236 ps |
| T128 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2653191576 |
|
|
Jul 22 06:20:23 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
300352198 ps |
| T936 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1287524347 |
|
|
Jul 22 06:20:32 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
71141050 ps |
| T937 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2870778080 |
|
|
Jul 22 06:20:30 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
104821339 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2925454333 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:33 PM PDT 24 |
397043796 ps |
| T938 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1934048003 |
|
|
Jul 22 06:20:17 PM PDT 24 |
Jul 22 06:20:20 PM PDT 24 |
34613593 ps |
| T939 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1676413926 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:36 PM PDT 24 |
161221720 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3031519744 |
|
|
Jul 22 06:20:22 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
232734778 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1143020404 |
|
|
Jul 22 06:20:15 PM PDT 24 |
Jul 22 06:20:18 PM PDT 24 |
28968916 ps |
| T941 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1078987186 |
|
|
Jul 22 06:21:58 PM PDT 24 |
Jul 22 06:22:00 PM PDT 24 |
13078717 ps |
| T138 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3001380458 |
|
|
Jul 22 06:20:26 PM PDT 24 |
Jul 22 06:20:28 PM PDT 24 |
107090857 ps |
| T942 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2294244828 |
|
|
Jul 22 06:20:22 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
312026752 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.83868483 |
|
|
Jul 22 06:20:14 PM PDT 24 |
Jul 22 06:20:17 PM PDT 24 |
18048081 ps |
| T943 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1292753014 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:30 PM PDT 24 |
18898469 ps |
| T944 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1391344619 |
|
|
Jul 22 06:20:14 PM PDT 24 |
Jul 22 06:20:18 PM PDT 24 |
72394774 ps |
| T945 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2497241446 |
|
|
Jul 22 06:20:34 PM PDT 24 |
Jul 22 06:20:38 PM PDT 24 |
93866635 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3742429542 |
|
|
Jul 22 06:22:38 PM PDT 24 |
Jul 22 06:22:42 PM PDT 24 |
391026995 ps |
| T91 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.894637507 |
|
|
Jul 22 06:20:18 PM PDT 24 |
Jul 22 06:20:23 PM PDT 24 |
1593654047 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1811272162 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:30 PM PDT 24 |
83184623 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2143953293 |
|
|
Jul 22 06:20:38 PM PDT 24 |
Jul 22 06:20:40 PM PDT 24 |
36202140 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3754466166 |
|
|
Jul 22 06:20:23 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
55828173 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.264901127 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:31 PM PDT 24 |
12321930 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.893026172 |
|
|
Jul 22 06:21:03 PM PDT 24 |
Jul 22 06:21:04 PM PDT 24 |
57552961 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2074248376 |
|
|
Jul 22 06:20:25 PM PDT 24 |
Jul 22 06:20:26 PM PDT 24 |
22952490 ps |
| T94 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.314296903 |
|
|
Jul 22 06:22:38 PM PDT 24 |
Jul 22 06:22:44 PM PDT 24 |
502138161 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.252924265 |
|
|
Jul 22 06:20:17 PM PDT 24 |
Jul 22 06:20:22 PM PDT 24 |
89740666 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.891025074 |
|
|
Jul 22 06:20:27 PM PDT 24 |
Jul 22 06:20:29 PM PDT 24 |
80418807 ps |
| T951 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1603096075 |
|
|
Jul 22 06:22:38 PM PDT 24 |
Jul 22 06:22:40 PM PDT 24 |
102687069 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3725732165 |
|
|
Jul 22 06:20:38 PM PDT 24 |
Jul 22 06:20:39 PM PDT 24 |
28569343 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2220519026 |
|
|
Jul 22 06:21:04 PM PDT 24 |
Jul 22 06:21:06 PM PDT 24 |
34779340 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.155526801 |
|
|
Jul 22 06:21:58 PM PDT 24 |
Jul 22 06:22:00 PM PDT 24 |
99668842 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.250083161 |
|
|
Jul 22 06:20:32 PM PDT 24 |
Jul 22 06:20:38 PM PDT 24 |
711375112 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2453461353 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:31 PM PDT 24 |
16261779 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1806367346 |
|
|
Jul 22 06:20:33 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
40373087 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3741185132 |
|
|
Jul 22 06:20:17 PM PDT 24 |
Jul 22 06:20:23 PM PDT 24 |
177248625 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4200210385 |
|
|
Jul 22 06:20:24 PM PDT 24 |
Jul 22 06:20:27 PM PDT 24 |
48865485 ps |
| T136 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4144776164 |
|
|
Jul 22 06:20:23 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
585313928 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2904546981 |
|
|
Jul 22 06:20:59 PM PDT 24 |
Jul 22 06:21:06 PM PDT 24 |
149206322 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.411046950 |
|
|
Jul 22 06:21:25 PM PDT 24 |
Jul 22 06:21:27 PM PDT 24 |
29048799 ps |
| T129 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2655510049 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:34 PM PDT 24 |
139809898 ps |
| T130 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2203278649 |
|
|
Jul 22 06:20:23 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
203103416 ps |
| T960 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1273816006 |
|
|
Jul 22 06:20:27 PM PDT 24 |
Jul 22 06:20:30 PM PDT 24 |
49308813 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3894552146 |
|
|
Jul 22 06:20:13 PM PDT 24 |
Jul 22 06:20:16 PM PDT 24 |
14290454 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2959157048 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
35409747 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.801171060 |
|
|
Jul 22 06:20:17 PM PDT 24 |
Jul 22 06:20:19 PM PDT 24 |
33168062 ps |
| T964 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3372921199 |
|
|
Jul 22 06:20:32 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
217334590 ps |
| T965 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2863022808 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
132061633 ps |
| T101 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2150668933 |
|
|
Jul 22 06:20:37 PM PDT 24 |
Jul 22 06:20:40 PM PDT 24 |
394175916 ps |
| T966 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2488591039 |
|
|
Jul 22 06:22:38 PM PDT 24 |
Jul 22 06:22:42 PM PDT 24 |
26509063 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4102733408 |
|
|
Jul 22 06:20:59 PM PDT 24 |
Jul 22 06:21:00 PM PDT 24 |
31114115 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1791612288 |
|
|
Jul 22 06:20:33 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
26623795 ps |
| T969 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2871239605 |
|
|
Jul 22 06:20:18 PM PDT 24 |
Jul 22 06:20:23 PM PDT 24 |
96968104 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.680928298 |
|
|
Jul 22 06:20:25 PM PDT 24 |
Jul 22 06:20:27 PM PDT 24 |
78737388 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1966005413 |
|
|
Jul 22 06:20:21 PM PDT 24 |
Jul 22 06:20:24 PM PDT 24 |
138738527 ps |
| T102 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2378478092 |
|
|
Jul 22 06:20:22 PM PDT 24 |
Jul 22 06:20:26 PM PDT 24 |
432504526 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1402809125 |
|
|
Jul 22 06:20:39 PM PDT 24 |
Jul 22 06:20:42 PM PDT 24 |
132426726 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1853134866 |
|
|
Jul 22 06:20:30 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
493876172 ps |
| T974 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.375287257 |
|
|
Jul 22 06:20:24 PM PDT 24 |
Jul 22 06:20:25 PM PDT 24 |
48382412 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2714217324 |
|
|
Jul 22 06:21:58 PM PDT 24 |
Jul 22 06:22:02 PM PDT 24 |
389931768 ps |
| T975 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.966070617 |
|
|
Jul 22 06:20:27 PM PDT 24 |
Jul 22 06:20:33 PM PDT 24 |
327407248 ps |
| T976 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.703331633 |
|
|
Jul 22 06:21:25 PM PDT 24 |
Jul 22 06:21:27 PM PDT 24 |
38949373 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2614721541 |
|
|
Jul 22 06:21:04 PM PDT 24 |
Jul 22 06:21:05 PM PDT 24 |
15194148 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.490568277 |
|
|
Jul 22 06:20:31 PM PDT 24 |
Jul 22 06:20:34 PM PDT 24 |
700383317 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1790820375 |
|
|
Jul 22 06:20:22 PM PDT 24 |
Jul 22 06:20:24 PM PDT 24 |
52309315 ps |
| T980 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1731277616 |
|
|
Jul 22 06:20:33 PM PDT 24 |
Jul 22 06:20:35 PM PDT 24 |
15682581 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.780061256 |
|
|
Jul 22 06:20:54 PM PDT 24 |
Jul 22 06:20:58 PM PDT 24 |
2191717033 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.691606656 |
|
|
Jul 22 06:20:15 PM PDT 24 |
Jul 22 06:20:18 PM PDT 24 |
30211809 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.148818563 |
|
|
Jul 22 06:20:25 PM PDT 24 |
Jul 22 06:20:26 PM PDT 24 |
83364468 ps |
| T984 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1383600454 |
|
|
Jul 22 06:20:24 PM PDT 24 |
Jul 22 06:20:27 PM PDT 24 |
893073649 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3951964181 |
|
|
Jul 22 06:21:04 PM PDT 24 |
Jul 22 06:21:08 PM PDT 24 |
442592001 ps |
| T986 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1101594007 |
|
|
Jul 22 06:20:24 PM PDT 24 |
Jul 22 06:20:27 PM PDT 24 |
279328002 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1880609129 |
|
|
Jul 22 06:20:28 PM PDT 24 |
Jul 22 06:20:29 PM PDT 24 |
31970637 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.938332998 |
|
|
Jul 22 06:20:21 PM PDT 24 |
Jul 22 06:20:22 PM PDT 24 |
13530507 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.386356677 |
|
|
Jul 22 06:20:24 PM PDT 24 |
Jul 22 06:20:26 PM PDT 24 |
22595475 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3667538742 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:31 PM PDT 24 |
358834831 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2210969689 |
|
|
Jul 22 06:20:37 PM PDT 24 |
Jul 22 06:20:39 PM PDT 24 |
48468242 ps |
| T134 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.848337679 |
|
|
Jul 22 06:21:04 PM PDT 24 |
Jul 22 06:21:06 PM PDT 24 |
97138688 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1074711881 |
|
|
Jul 22 06:20:18 PM PDT 24 |
Jul 22 06:20:21 PM PDT 24 |
156254187 ps |
| T992 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2007606658 |
|
|
Jul 22 06:21:06 PM PDT 24 |
Jul 22 06:21:08 PM PDT 24 |
42735330 ps |
| T137 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3485535670 |
|
|
Jul 22 06:20:35 PM PDT 24 |
Jul 22 06:20:37 PM PDT 24 |
107012950 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.58108564 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:32 PM PDT 24 |
1083589639 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2554325297 |
|
|
Jul 22 06:20:32 PM PDT 24 |
Jul 22 06:20:38 PM PDT 24 |
548890273 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2834042288 |
|
|
Jul 22 06:20:18 PM PDT 24 |
Jul 22 06:20:23 PM PDT 24 |
2355321178 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.427083872 |
|
|
Jul 22 06:20:26 PM PDT 24 |
Jul 22 06:20:29 PM PDT 24 |
607750098 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3754598185 |
|
|
Jul 22 06:20:39 PM PDT 24 |
Jul 22 06:20:41 PM PDT 24 |
12959187 ps |
| T135 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.171042021 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:32 PM PDT 24 |
662918415 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2519417184 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:31 PM PDT 24 |
155243564 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4221522856 |
|
|
Jul 22 06:20:22 PM PDT 24 |
Jul 22 06:20:24 PM PDT 24 |
209816413 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3210922533 |
|
|
Jul 22 06:20:29 PM PDT 24 |
Jul 22 06:20:32 PM PDT 24 |
43866502 ps |