Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	155024346	1			T1	440828		T3	257741		T4	35100
instr_valid_dis	119309008	1			T1	440828		T3	114613		T4	35100
instr_en	25504552	1			T3	504104		T10	481588		T5	186424

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13630389	1			T3	474956		T10	76332		T5	128392
sram_ifetch_valid_disable	116609829	1			T1	440828		T3	139472		T4	35100
sram_ifetch_enable	24784128	1			T3	707736		T10	182396		T5	324726

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	155024346	1			T1	440828		T3	257741		T4	35100
hw_debug_en_valid_off	118299968	1			T1	440828		T3	146668		T4	35100
hw_debug_en_on	24360524	1			T3	845058		T10	53008		T5	348324

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116609829	1			T1	440828		T3	139472		T4	35100
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102544682	1			T1	440828		T3	687888		T4	35100
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10273105	1			T3	227476		T10	222860		T5	71768
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6163603	1			T3	199412		T10	66336		T5	84990
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3254677	1			T3	56534		T5	43346		T75	30298
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2129884	1			T3	31326		T10	66336		T57	6394
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4936058	1			T3	180498		T5	33624		T75	41218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1999928	1			T3	82164		T5	3798		T75	41218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2227318	1			T3	64972		T5	29826		T56	44028
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9484179	1			T3	344546		T10	34476		T5	85026
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3647197	1			T3	44802		T5	39812		T57	79896
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4292510	1			T3	25314		T10	34476		T75	12884

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9729899	1			T3	132558		T10	182396		T5	84830
lc_exec_en	9940287	1			T3	320014		T10	18532		T5	229674
valid_exec_dis	113035415	1			T1	440828		T3	127533		T4	35100
invalid_exec_dis	38414517	1			T3	118269		T10	258728		T5	453118