Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total tests in report: 1031

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
83.60	83.60	95.51	95.51	80.09	80.09	94.11	94.11	61.90	61.90	85.27	85.27	94.25	94.25	74.04	74.04	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3106888699
89.42	5.82	97.20	1.69	87.91	7.82	95.56	1.46	71.43	9.52	91.55	6.28	95.43	1.18	86.84	12.80	/workspace/coverage/default/0.sram_ctrl_stress_all.2702530562
94.33	4.91	98.73	1.53	88.03	0.12	96.46	0.90	100.00	28.57	94.44	2.90	95.43	0.00	87.20	0.37	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.526821698
95.28	0.95	98.90	0.17	88.86	0.83	96.67	0.21	100.00	0.00	95.17	0.72	95.43	0.00	91.96	4.75	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3297579474
95.99	0.71	99.07	0.17	90.64	1.78	97.43	0.76	100.00	0.00	95.89	0.72	96.02	0.59	92.87	0.91	/workspace/coverage/default/0.sram_ctrl_sec_cm.3429234638
96.47	0.49	99.07	0.00	90.64	0.00	98.61	1.18	100.00	0.00	96.14	0.24	96.17	0.15	94.70	1.83	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1201909198
96.67	0.20	99.07	0.00	90.64	0.00	98.68	0.07	100.00	0.00	96.14	0.00	97.49	1.33	94.70	0.00	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2406652067
96.83	0.15	99.07	0.00	90.64	0.00	98.68	0.00	100.00	0.00	96.14	0.00	98.38	0.88	94.88	0.18	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.475394697
96.97	0.14	99.15	0.08	90.64	0.00	99.58	0.90	100.00	0.00	96.14	0.00	98.38	0.00	94.88	0.00	/workspace/coverage/default/22.sram_ctrl_ram_cfg.2525154655
97.08	0.12	99.15	0.00	90.64	0.00	99.58	0.00	100.00	0.00	96.14	0.00	98.82	0.44	95.25	0.37	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.290206652
97.19	0.10	99.15	0.00	90.64	0.00	99.58	0.00	100.00	0.00	96.14	0.00	98.82	0.00	95.98	0.73	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3957747140
97.28	0.09	99.15	0.00	90.64	0.00	99.65	0.07	100.00	0.00	96.14	0.00	98.82	0.00	96.53	0.55	/workspace/coverage/default/2.sram_ctrl_stress_all.584254300
97.34	0.06	99.15	0.00	91.00	0.36	99.72	0.07	100.00	0.00	96.14	0.00	98.82	0.00	96.53	0.00	/workspace/coverage/default/11.sram_ctrl_alert_test.822904370
97.39	0.05	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	98.82	0.00	96.89	0.37	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1442890284
97.43	0.04	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.29	96.89	0.00	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.757512598
97.46	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.07	0.18	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1229791008
97.48	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.26	0.18	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3950764997
97.51	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.44	0.18	/workspace/coverage/default/13.sram_ctrl_regwen.2055943990

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.810248837
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.38388654
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2635758137
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1908000710
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.845901777
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.591907458
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4182232100
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.920273451
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2907148989
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1665693417
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1128309622
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1248406424
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2377644913
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1864516968
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1019352697
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2801988516
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1235764551
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2617377081
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.625375174
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3873732687
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.572120788
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2192964116
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1105856460
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.633968031
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1625004402
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3763471008
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3608861419
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2098586443
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4156235938
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4050331044
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2139198852
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1352575165
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3558001365
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1120043236
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.16548510
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2334782247
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1890626143
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4004321302
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.960012739
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2215156393
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2138187854
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2732227902
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3376510742
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1652368528
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3082411443
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2701637453
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3623239133
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1495916303
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2324544316
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3204993110
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3700742292
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4021570497
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3087666698
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1598821393
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1861586317
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1944452057
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3895822520
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3281022268
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1322195346
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2021141304
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1143149296
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2275805609
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2854423950
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2976280634
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.15483626
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3179764241
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3924273003
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3137469724
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4085477587
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.281552221
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3727550505
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1745279195
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.556269342
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4185087961
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2760855906
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3173059415
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2911943420
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3704071593
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1142714913
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4178450924
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1484043587
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3232886935
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2003926244
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.54831520
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.268817722
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1510323167
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.980345377
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1296173053
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4215626288
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2374465098
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1556099553
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.837889608
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2715086617
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.640228922
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4032186387
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1211872072
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2153104255
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3345451913
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.870469956
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3284189509
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2199051420
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3599670316
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.141847467
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2876604150
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2657287820
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1998321389
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2083308024
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3794229970
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.758105914
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2971525527
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2674429423
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2547811694
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2473375458
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2815605140
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3510096156
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.110815301
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2974523835
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.207954201
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3868675484
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1296384456
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2566099161
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4013404969
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.794479912
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2131854352
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1353025043
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3739642224
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1039118369
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2872971185
/workspace/coverage/default/0.sram_ctrl_alert_test.3674505368
/workspace/coverage/default/0.sram_ctrl_bijection.2594221997
/workspace/coverage/default/0.sram_ctrl_executable.4247799049
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3543294603
/workspace/coverage/default/0.sram_ctrl_max_throughput.1160971917
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2895542761
/workspace/coverage/default/0.sram_ctrl_mem_walk.1704227090
/workspace/coverage/default/0.sram_ctrl_multiple_keys.228981556
/workspace/coverage/default/0.sram_ctrl_partial_access.153215657
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.767943135
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2027137430
/workspace/coverage/default/0.sram_ctrl_regwen.2644868465
/workspace/coverage/default/0.sram_ctrl_smoke.4054955514
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2468261215
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2385867279
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2062529043
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2959660041
/workspace/coverage/default/1.sram_ctrl_alert_test.746379816
/workspace/coverage/default/1.sram_ctrl_bijection.2165208392
/workspace/coverage/default/1.sram_ctrl_executable.2548908995
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1521422677
/workspace/coverage/default/1.sram_ctrl_max_throughput.2263084197
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3750491589
/workspace/coverage/default/1.sram_ctrl_mem_walk.1101169079
/workspace/coverage/default/1.sram_ctrl_multiple_keys.681197129
/workspace/coverage/default/1.sram_ctrl_partial_access.3697435060
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4233690217
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2172339422
/workspace/coverage/default/1.sram_ctrl_regwen.3018487251
/workspace/coverage/default/1.sram_ctrl_sec_cm.2909824266
/workspace/coverage/default/1.sram_ctrl_smoke.1875735820
/workspace/coverage/default/1.sram_ctrl_stress_all.411537842
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3344807768
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4009166990
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4036698184
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2001392451
/workspace/coverage/default/10.sram_ctrl_alert_test.1920913461
/workspace/coverage/default/10.sram_ctrl_bijection.2561940503
/workspace/coverage/default/10.sram_ctrl_executable.980277864
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2354128645
/workspace/coverage/default/10.sram_ctrl_max_throughput.1519396195
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.148905116
/workspace/coverage/default/10.sram_ctrl_mem_walk.4130984925
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1308872055
/workspace/coverage/default/10.sram_ctrl_partial_access.2165407068
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3998556984
/workspace/coverage/default/10.sram_ctrl_regwen.4025631791
/workspace/coverage/default/10.sram_ctrl_smoke.2740911902
/workspace/coverage/default/10.sram_ctrl_stress_all.2487040746
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2041932849
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3498887583
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4262468513
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3996162387
/workspace/coverage/default/11.sram_ctrl_bijection.931812008
/workspace/coverage/default/11.sram_ctrl_executable.530484292
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2785161677
/workspace/coverage/default/11.sram_ctrl_max_throughput.3779118126
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.124100840
/workspace/coverage/default/11.sram_ctrl_mem_walk.893945371
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3303836403
/workspace/coverage/default/11.sram_ctrl_partial_access.780063925
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3881330144
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2552838613
/workspace/coverage/default/11.sram_ctrl_regwen.1685633
/workspace/coverage/default/11.sram_ctrl_smoke.2006107891
/workspace/coverage/default/11.sram_ctrl_stress_all.4160370116
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3560941272
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3769940097
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.463549964
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/workspace/coverage/default/42.sram_ctrl_ram_cfg.1164390119
/workspace/coverage/default/42.sram_ctrl_regwen.675989404
/workspace/coverage/default/42.sram_ctrl_smoke.2187555253
/workspace/coverage/default/42.sram_ctrl_stress_all.2843954645
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1853495098
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.531459412
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3500414526
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2347880007
/workspace/coverage/default/43.sram_ctrl_alert_test.107313794
/workspace/coverage/default/43.sram_ctrl_bijection.4064808964
/workspace/coverage/default/43.sram_ctrl_executable.587364880
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1555871568
/workspace/coverage/default/43.sram_ctrl_max_throughput.2850196580
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.965952366
/workspace/coverage/default/43.sram_ctrl_mem_walk.2223800225
/workspace/coverage/default/43.sram_ctrl_partial_access.493042743
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3081442671
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3401802867
/workspace/coverage/default/43.sram_ctrl_regwen.2957232541
/workspace/coverage/default/43.sram_ctrl_smoke.2503215265
/workspace/coverage/default/43.sram_ctrl_stress_all.2180629632
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1170404610
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1407481517
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3826435154
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2057316673
/workspace/coverage/default/44.sram_ctrl_alert_test.915819189
/workspace/coverage/default/44.sram_ctrl_bijection.816244796
/workspace/coverage/default/44.sram_ctrl_executable.2728155357
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3550799750
/workspace/coverage/default/44.sram_ctrl_max_throughput.1853462594
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2755210151
/workspace/coverage/default/44.sram_ctrl_mem_walk.3130177181
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1269450407
/workspace/coverage/default/44.sram_ctrl_partial_access.763902408
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4014541604
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3711433240
/workspace/coverage/default/44.sram_ctrl_regwen.2506049907
/workspace/coverage/default/44.sram_ctrl_smoke.1943186201
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1299224812
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.770213765
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1967819547
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3709351855
/workspace/coverage/default/45.sram_ctrl_alert_test.594115201
/workspace/coverage/default/45.sram_ctrl_bijection.2901916487
/workspace/coverage/default/45.sram_ctrl_executable.3493438584
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1614646662
/workspace/coverage/default/45.sram_ctrl_max_throughput.3667277963
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1421482272
/workspace/coverage/default/45.sram_ctrl_mem_walk.2002006150
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3635565105
/workspace/coverage/default/45.sram_ctrl_partial_access.1375028210
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3609427538
/workspace/coverage/default/45.sram_ctrl_ram_cfg.205032405
/workspace/coverage/default/45.sram_ctrl_regwen.1793906838
/workspace/coverage/default/45.sram_ctrl_smoke.579213676
/workspace/coverage/default/45.sram_ctrl_stress_all.1488563272
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2192813579
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2712518733
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.87934781
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1371047986
/workspace/coverage/default/46.sram_ctrl_alert_test.3922702610
/workspace/coverage/default/46.sram_ctrl_bijection.936479611
/workspace/coverage/default/46.sram_ctrl_executable.3655166295
/workspace/coverage/default/46.sram_ctrl_lc_escalation.733926053
/workspace/coverage/default/46.sram_ctrl_max_throughput.1622912406
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.664337659
/workspace/coverage/default/46.sram_ctrl_mem_walk.3481729676
/workspace/coverage/default/46.sram_ctrl_multiple_keys.507418610
/workspace/coverage/default/46.sram_ctrl_partial_access.1914489864
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2329258214
/workspace/coverage/default/46.sram_ctrl_regwen.64613523
/workspace/coverage/default/46.sram_ctrl_smoke.3487904868
/workspace/coverage/default/46.sram_ctrl_stress_all.3302556344
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3365344283
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4128240777
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3532336338
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2468559926
/workspace/coverage/default/47.sram_ctrl_alert_test.658246343
/workspace/coverage/default/47.sram_ctrl_bijection.3589754328
/workspace/coverage/default/47.sram_ctrl_executable.3966253993
/workspace/coverage/default/47.sram_ctrl_lc_escalation.975680012
/workspace/coverage/default/47.sram_ctrl_max_throughput.336719821
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3371478826
/workspace/coverage/default/47.sram_ctrl_mem_walk.1596835101
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2374081680
/workspace/coverage/default/47.sram_ctrl_partial_access.2430048282
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2923345891
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1423948938
/workspace/coverage/default/47.sram_ctrl_regwen.2157446658
/workspace/coverage/default/47.sram_ctrl_smoke.495565289
/workspace/coverage/default/47.sram_ctrl_stress_all.2052037763
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.348711025
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.407948907
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3454073202
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.470354914
/workspace/coverage/default/48.sram_ctrl_alert_test.1930784345
/workspace/coverage/default/48.sram_ctrl_bijection.326436713
/workspace/coverage/default/48.sram_ctrl_executable.3683024683
/workspace/coverage/default/48.sram_ctrl_lc_escalation.676591918
/workspace/coverage/default/48.sram_ctrl_max_throughput.430776455
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3976755673
/workspace/coverage/default/48.sram_ctrl_mem_walk.4078949558
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1456130602
/workspace/coverage/default/48.sram_ctrl_partial_access.276846411
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1276137968
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2564444595
/workspace/coverage/default/48.sram_ctrl_regwen.952610338
/workspace/coverage/default/48.sram_ctrl_smoke.579086470
/workspace/coverage/default/48.sram_ctrl_stress_all.3918616814
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2605832778
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2641685140
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2907972
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1932941939
/workspace/coverage/default/49.sram_ctrl_alert_test.3949598006
/workspace/coverage/default/49.sram_ctrl_bijection.850210804
/workspace/coverage/default/49.sram_ctrl_executable.3320469094
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2304150696
/workspace/coverage/default/49.sram_ctrl_max_throughput.2465230264
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3134270386
/workspace/coverage/default/49.sram_ctrl_mem_walk.4027611509
/workspace/coverage/default/49.sram_ctrl_partial_access.1651175506
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.359458558
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2462332997
/workspace/coverage/default/49.sram_ctrl_regwen.2760072099
/workspace/coverage/default/49.sram_ctrl_smoke.3690637662
/workspace/coverage/default/49.sram_ctrl_stress_all.449586758
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.486431050
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2294514142
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1235915358
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1273939282
/workspace/coverage/default/5.sram_ctrl_alert_test.2624519332
/workspace/coverage/default/5.sram_ctrl_bijection.1603433179
/workspace/coverage/default/5.sram_ctrl_executable.1350110442
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1349866174
/workspace/coverage/default/5.sram_ctrl_max_throughput.730714714
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3640167198
/workspace/coverage/default/5.sram_ctrl_mem_walk.3044956000
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3666803059
/workspace/coverage/default/5.sram_ctrl_partial_access.3918910017
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4286509377
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1020187631
/workspace/coverage/default/5.sram_ctrl_regwen.2987683936
/workspace/coverage/default/5.sram_ctrl_smoke.1928443661
/workspace/coverage/default/5.sram_ctrl_stress_all.3145999662
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.456797992
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3931499752
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3505035526
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2278544594
/workspace/coverage/default/6.sram_ctrl_alert_test.3496332671
/workspace/coverage/default/6.sram_ctrl_bijection.1898933335
/workspace/coverage/default/6.sram_ctrl_executable.925744690
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2741631404
/workspace/coverage/default/6.sram_ctrl_max_throughput.2972237417
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1345033000
/workspace/coverage/default/6.sram_ctrl_mem_walk.3083513716
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1877310449
/workspace/coverage/default/6.sram_ctrl_partial_access.4068469933
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1294233741
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3040822947
/workspace/coverage/default/6.sram_ctrl_regwen.1670363372
/workspace/coverage/default/6.sram_ctrl_smoke.745061931
/workspace/coverage/default/6.sram_ctrl_stress_all.4150564158
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1074829226
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3332695027
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1959381865
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.902049391
/workspace/coverage/default/7.sram_ctrl_alert_test.3715489630
/workspace/coverage/default/7.sram_ctrl_bijection.4279530087
/workspace/coverage/default/7.sram_ctrl_executable.2791691302
/workspace/coverage/default/7.sram_ctrl_lc_escalation.4191642547
/workspace/coverage/default/7.sram_ctrl_max_throughput.2342450843
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2512181945
/workspace/coverage/default/7.sram_ctrl_mem_walk.3277185722
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1403128953
/workspace/coverage/default/7.sram_ctrl_partial_access.2296730523
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2445888229
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3559792772
/workspace/coverage/default/7.sram_ctrl_regwen.3884238799
/workspace/coverage/default/7.sram_ctrl_smoke.3279454467
/workspace/coverage/default/7.sram_ctrl_stress_all.1548736922
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3219684209
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1888850573
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.897429304
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2814850475
/workspace/coverage/default/8.sram_ctrl_alert_test.51219765
/workspace/coverage/default/8.sram_ctrl_bijection.3890716759
/workspace/coverage/default/8.sram_ctrl_executable.2189573125
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1616280806
/workspace/coverage/default/8.sram_ctrl_max_throughput.2943336418
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3808558328
/workspace/coverage/default/8.sram_ctrl_mem_walk.1194658326
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1290352708
/workspace/coverage/default/8.sram_ctrl_partial_access.1056867878
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1918532324
/workspace/coverage/default/8.sram_ctrl_ram_cfg.127886673
/workspace/coverage/default/8.sram_ctrl_regwen.3229021154
/workspace/coverage/default/8.sram_ctrl_smoke.3900886410
/workspace/coverage/default/8.sram_ctrl_stress_all.4286264650
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1196962325
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3087599475
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.256968965
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3455357457
/workspace/coverage/default/9.sram_ctrl_alert_test.3120035116
/workspace/coverage/default/9.sram_ctrl_bijection.3919634242
/workspace/coverage/default/9.sram_ctrl_executable.1810759904
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3861382047
/workspace/coverage/default/9.sram_ctrl_max_throughput.1910805331
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.948648051
/workspace/coverage/default/9.sram_ctrl_mem_walk.2599746237
/workspace/coverage/default/9.sram_ctrl_multiple_keys.701108004
/workspace/coverage/default/9.sram_ctrl_partial_access.2006302538
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2689445405
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1493160970
/workspace/coverage/default/9.sram_ctrl_regwen.3244487433
/workspace/coverage/default/9.sram_ctrl_smoke.4086220516
/workspace/coverage/default/9.sram_ctrl_stress_all.1141946297
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3916138865
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.234420167
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3179048040

Total test records in report: 1031

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1201909198	Jul 23 06:35:26 PM PDT 24	Jul 23 06:42:11 PM PDT 24	14933323971 ps
T2	/workspace/coverage/default/13.sram_ctrl_alert_test.723474303	Jul 23 06:32:14 PM PDT 24	Jul 23 06:32:25 PM PDT 24	11119672 ps
T3	/workspace/coverage/default/0.sram_ctrl_stress_all.2702530562	Jul 23 06:31:42 PM PDT 24	Jul 23 08:44:44 PM PDT 24	100212300330 ps
T4	/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3106888699	Jul 23 06:33:04 PM PDT 24	Jul 23 06:33:38 PM PDT 24	4781931176 ps
T7	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2959660041	Jul 23 06:31:41 PM PDT 24	Jul 23 06:33:11 PM PDT 24	397307728 ps
T8	/workspace/coverage/default/46.sram_ctrl_bijection.936479611	Jul 23 06:35:26 PM PDT 24	Jul 23 06:35:51 PM PDT 24	353941532 ps
T9	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3690745790	Jul 23 06:33:16 PM PDT 24	Jul 23 06:38:11 PM PDT 24	35438825350 ps
T10	/workspace/coverage/default/13.sram_ctrl_regwen.2055943990	Jul 23 06:32:15 PM PDT 24	Jul 23 06:51:11 PM PDT 24	44175945769 ps
T11	/workspace/coverage/default/39.sram_ctrl_ram_cfg.3593697861	Jul 23 06:34:36 PM PDT 24	Jul 23 06:34:38 PM PDT 24	146899529 ps
T12	/workspace/coverage/default/35.sram_ctrl_partial_access.3682833886	Jul 23 06:34:01 PM PDT 24	Jul 23 06:34:06 PM PDT 24	189482876 ps
T34	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2468559926	Jul 23 06:35:46 PM PDT 24	Jul 23 06:54:57 PM PDT 24	3192918471 ps
T35	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1932941939	Jul 23 06:36:00 PM PDT 24	Jul 23 07:06:43 PM PDT 24	14268720816 ps
T5	/workspace/coverage/default/47.sram_ctrl_stress_all.2052037763	Jul 23 06:35:45 PM PDT 24	Jul 23 07:34:25 PM PDT 24	86248344700 ps
T75	/workspace/coverage/default/38.sram_ctrl_executable.3361900736	Jul 23 06:34:26 PM PDT 24	Jul 23 06:46:13 PM PDT 24	5973024516 ps
T52	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.193390172	Jul 23 06:34:36 PM PDT 24	Jul 23 06:34:41 PM PDT 24	357764499 ps
T73	/workspace/coverage/default/3.sram_ctrl_multiple_keys.1682401632	Jul 23 06:31:49 PM PDT 24	Jul 23 06:58:50 PM PDT 24	51960470506 ps
T138	/workspace/coverage/default/31.sram_ctrl_smoke.2802355999	Jul 23 06:33:35 PM PDT 24	Jul 23 06:33:53 PM PDT 24	769318983 ps
T6	/workspace/coverage/default/2.sram_ctrl_lc_escalation.1476228305	Jul 23 06:31:41 PM PDT 24	Jul 23 06:31:55 PM PDT 24	859335822 ps
T56	/workspace/coverage/default/45.sram_ctrl_regwen.1793906838	Jul 23 06:35:20 PM PDT 24	Jul 23 06:48:04 PM PDT 24	12308870778 ps
T36	/workspace/coverage/default/16.sram_ctrl_mem_walk.2206638277	Jul 23 06:32:30 PM PDT 24	Jul 23 06:32:47 PM PDT 24	2323200562 ps
T37	/workspace/coverage/default/35.sram_ctrl_mem_walk.2391479740	Jul 23 06:34:12 PM PDT 24	Jul 23 06:34:18 PM PDT 24	96578450 ps
T53	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3952663826	Jul 23 06:33:39 PM PDT 24	Jul 23 06:47:49 PM PDT 24	5163425123 ps
T20	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3219684209	Jul 23 06:31:55 PM PDT 24	Jul 23 06:33:17 PM PDT 24	1586016642 ps
T136	/workspace/coverage/default/5.sram_ctrl_max_throughput.730714714	Jul 23 06:31:56 PM PDT 24	Jul 23 06:32:20 PM PDT 24	78904003 ps
T137	/workspace/coverage/default/18.sram_ctrl_bijection.3786182770	Jul 23 06:32:24 PM PDT 24	Jul 23 06:33:43 PM PDT 24	1262325926 ps
T139	/workspace/coverage/default/3.sram_ctrl_smoke.682906332	Jul 23 06:31:44 PM PDT 24	Jul 23 06:32:00 PM PDT 24	319065458 ps
T140	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3984854878	Jul 23 06:32:22 PM PDT 24	Jul 23 06:33:03 PM PDT 24	267417145 ps
T74	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.382039183	Jul 23 06:33:16 PM PDT 24	Jul 23 06:38:41 PM PDT 24	3329049688 ps
T21	/workspace/coverage/default/22.sram_ctrl_ram_cfg.2525154655	Jul 23 06:32:43 PM PDT 24	Jul 23 06:32:45 PM PDT 24	45401809 ps
T19	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1687051798	Jul 23 06:31:46 PM PDT 24	Jul 23 06:34:16 PM PDT 24	2677976245 ps
T81	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3618682414	Jul 23 06:33:12 PM PDT 24	Jul 23 06:33:19 PM PDT 24	409249735 ps
T43	/workspace/coverage/default/47.sram_ctrl_mem_walk.1596835101	Jul 23 06:35:44 PM PDT 24	Jul 23 06:35:57 PM PDT 24	1754049914 ps
T135	/workspace/coverage/default/32.sram_ctrl_multiple_keys.294045506	Jul 23 06:33:41 PM PDT 24	Jul 23 06:46:20 PM PDT 24	10765845690 ps
T22	/workspace/coverage/default/41.sram_ctrl_ram_cfg.3851669797	Jul 23 06:34:50 PM PDT 24	Jul 23 06:34:52 PM PDT 24	37435800 ps
T141	/workspace/coverage/default/15.sram_ctrl_smoke.773958877	Jul 23 06:32:17 PM PDT 24	Jul 23 06:34:25 PM PDT 24	7964735049 ps
T142	/workspace/coverage/default/26.sram_ctrl_smoke.678108709	Jul 23 06:33:15 PM PDT 24	Jul 23 06:33:40 PM PDT 24	362111083 ps
T94	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1117460291	Jul 23 06:33:32 PM PDT 24	Jul 23 06:39:54 PM PDT 24	10394218827 ps
T143	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1471846492	Jul 23 06:31:44 PM PDT 24	Jul 23 06:33:01 PM PDT 24	123947334 ps
T144	/workspace/coverage/default/27.sram_ctrl_ram_cfg.2631542713	Jul 23 06:33:18 PM PDT 24	Jul 23 06:33:21 PM PDT 24	76561901 ps
T57	/workspace/coverage/default/33.sram_ctrl_stress_all.2664626831	Jul 23 06:33:53 PM PDT 24	Jul 23 07:04:46 PM PDT 24	7079388840 ps
T41	/workspace/coverage/default/18.sram_ctrl_mem_walk.734288580	Jul 23 06:32:31 PM PDT 24	Jul 23 06:32:44 PM PDT 24	1333088122 ps
T18	/workspace/coverage/default/36.sram_ctrl_lc_escalation.1070514825	Jul 23 06:34:14 PM PDT 24	Jul 23 06:34:19 PM PDT 24	203305987 ps
T95	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.4117936108	Jul 23 06:33:40 PM PDT 24	Jul 23 06:39:19 PM PDT 24	24976109460 ps
T82	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.876302124	Jul 23 06:32:23 PM PDT 24	Jul 23 06:34:26 PM PDT 24	2030777384 ps
T145	/workspace/coverage/default/36.sram_ctrl_ram_cfg.3894957414	Jul 23 06:34:13 PM PDT 24	Jul 23 06:34:16 PM PDT 24	40330981 ps
T146	/workspace/coverage/default/26.sram_ctrl_ram_cfg.1764063933	Jul 23 06:33:11 PM PDT 24	Jul 23 06:33:13 PM PDT 24	33315826 ps
T13	/workspace/coverage/default/19.sram_ctrl_alert_test.561071779	Jul 23 06:32:38 PM PDT 24	Jul 23 06:32:41 PM PDT 24	32997269 ps
T38	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.562401460	Jul 23 06:34:01 PM PDT 24	Jul 23 06:35:27 PM PDT 24	1005982829 ps
T60	/workspace/coverage/default/10.sram_ctrl_lc_escalation.2354128645	Jul 23 06:32:06 PM PDT 24	Jul 23 06:32:22 PM PDT 24	1767926115 ps
T42	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.456797992	Jul 23 06:31:54 PM PDT 24	Jul 23 06:33:44 PM PDT 24	1076741122 ps
T147	/workspace/coverage/default/34.sram_ctrl_multiple_keys.2426482007	Jul 23 06:33:56 PM PDT 24	Jul 23 06:53:28 PM PDT 24	24574295603 ps
T148	/workspace/coverage/default/34.sram_ctrl_bijection.1238245868	Jul 23 06:33:56 PM PDT 24	Jul 23 06:34:20 PM PDT 24	1385413581 ps
T149	/workspace/coverage/default/2.sram_ctrl_partial_access.3816032484	Jul 23 06:31:47 PM PDT 24	Jul 23 06:31:59 PM PDT 24	50616477 ps
T61	/workspace/coverage/default/32.sram_ctrl_stress_all.2603306020	Jul 23 06:33:52 PM PDT 24	Jul 23 06:57:44 PM PDT 24	22699424998 ps
T14	/workspace/coverage/default/16.sram_ctrl_alert_test.472926641	Jul 23 06:32:25 PM PDT 24	Jul 23 06:32:34 PM PDT 24	24836687 ps
T150	/workspace/coverage/default/8.sram_ctrl_partial_access.1056867878	Jul 23 06:32:02 PM PDT 24	Jul 23 06:34:09 PM PDT 24	2550206880 ps
T62	/workspace/coverage/default/43.sram_ctrl_regwen.2957232541	Jul 23 06:35:05 PM PDT 24	Jul 23 06:53:18 PM PDT 24	1644950477 ps
T151	/workspace/coverage/default/26.sram_ctrl_alert_test.1128027205	Jul 23 06:33:12 PM PDT 24	Jul 23 06:33:14 PM PDT 24	23845505 ps
T120	/workspace/coverage/default/15.sram_ctrl_lc_escalation.3038049263	Jul 23 06:32:20 PM PDT 24	Jul 23 06:32:32 PM PDT 24	198346050 ps
T152	/workspace/coverage/default/45.sram_ctrl_max_throughput.3667277963	Jul 23 06:35:21 PM PDT 24	Jul 23 06:35:24 PM PDT 24	170071336 ps
T96	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2930187642	Jul 23 06:33:39 PM PDT 24	Jul 23 06:39:55 PM PDT 24	16116079972 ps
T153	/workspace/coverage/default/24.sram_ctrl_ram_cfg.1398701454	Jul 23 06:33:00 PM PDT 24	Jul 23 06:33:03 PM PDT 24	28104621 ps
T154	/workspace/coverage/default/11.sram_ctrl_ram_cfg.2552838613	Jul 23 06:32:11 PM PDT 24	Jul 23 06:32:23 PM PDT 24	85141251 ps
T134	/workspace/coverage/default/31.sram_ctrl_stress_all.1299957039	Jul 23 06:33:42 PM PDT 24	Jul 23 07:14:29 PM PDT 24	20496929006 ps
T155	/workspace/coverage/default/43.sram_ctrl_bijection.4064808964	Jul 23 06:35:01 PM PDT 24	Jul 23 06:35:41 PM PDT 24	16663969740 ps
T156	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3826435154	Jul 23 06:35:04 PM PDT 24	Jul 23 06:35:52 PM PDT 24	129106215 ps
T157	/workspace/coverage/default/31.sram_ctrl_ram_cfg.1326747364	Jul 23 06:33:31 PM PDT 24	Jul 23 06:33:33 PM PDT 24	43818746 ps
T158	/workspace/coverage/default/20.sram_ctrl_max_throughput.37072049	Jul 23 06:32:39 PM PDT 24	Jul 23 06:33:20 PM PDT 24	344032802 ps
T44	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.139510087	Jul 23 06:33:06 PM PDT 24	Jul 23 06:33:14 PM PDT 24	256916454 ps
T159	/workspace/coverage/default/0.sram_ctrl_bijection.2594221997	Jul 23 06:31:47 PM PDT 24	Jul 23 06:32:50 PM PDT 24	874676049 ps
T160	/workspace/coverage/default/14.sram_ctrl_bijection.690890242	Jul 23 06:32:13 PM PDT 24	Jul 23 06:33:26 PM PDT 24	2912875474 ps
T161	/workspace/coverage/default/30.sram_ctrl_lc_escalation.2377225298	Jul 23 06:33:27 PM PDT 24	Jul 23 06:33:38 PM PDT 24	10854604089 ps
T97	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2676732031	Jul 23 06:32:15 PM PDT 24	Jul 23 06:36:29 PM PDT 24	2454092282 ps
T162	/workspace/coverage/default/40.sram_ctrl_stress_all.2569524483	Jul 23 06:34:42 PM PDT 24	Jul 23 07:06:29 PM PDT 24	26275469370 ps
T163	/workspace/coverage/default/44.sram_ctrl_mem_walk.3130177181	Jul 23 06:35:17 PM PDT 24	Jul 23 06:35:29 PM PDT 24	2646535176 ps
T164	/workspace/coverage/default/6.sram_ctrl_ram_cfg.3040822947	Jul 23 06:31:49 PM PDT 24	Jul 23 06:32:01 PM PDT 24	66962028 ps
T165	/workspace/coverage/default/34.sram_ctrl_max_throughput.2181871741	Jul 23 06:33:54 PM PDT 24	Jul 23 06:34:48 PM PDT 24	359116105 ps
T166	/workspace/coverage/default/11.sram_ctrl_alert_test.822904370	Jul 23 06:32:09 PM PDT 24	Jul 23 06:32:21 PM PDT 24	16152510 ps
T167	/workspace/coverage/default/24.sram_ctrl_regwen.1166518942	Jul 23 06:32:59 PM PDT 24	Jul 23 06:56:42 PM PDT 24	51625654617 ps
T168	/workspace/coverage/default/46.sram_ctrl_mem_walk.3481729676	Jul 23 06:35:31 PM PDT 24	Jul 23 06:35:37 PM PDT 24	965369043 ps
T98	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1683065201	Jul 23 06:33:00 PM PDT 24	Jul 23 06:39:42 PM PDT 24	15650925997 ps
T169	/workspace/coverage/default/39.sram_ctrl_max_throughput.3310743873	Jul 23 06:34:29 PM PDT 24	Jul 23 06:34:33 PM PDT 24	70753211 ps
T83	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.475394697	Jul 23 06:33:34 PM PDT 24	Jul 23 06:40:15 PM PDT 24	5538122253 ps
T45	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2041932849	Jul 23 06:32:09 PM PDT 24	Jul 23 06:37:47 PM PDT 24	7711300712 ps
T170	/workspace/coverage/default/25.sram_ctrl_partial_access.3410913769	Jul 23 06:33:01 PM PDT 24	Jul 23 06:33:50 PM PDT 24	141054356 ps
T171	/workspace/coverage/default/23.sram_ctrl_alert_test.3701221026	Jul 23 06:32:53 PM PDT 24	Jul 23 06:32:57 PM PDT 24	19761505 ps
T172	/workspace/coverage/default/11.sram_ctrl_lc_escalation.2785161677	Jul 23 06:32:08 PM PDT 24	Jul 23 06:32:26 PM PDT 24	4229591915 ps
T173	/workspace/coverage/default/31.sram_ctrl_regwen.4089351087	Jul 23 06:33:38 PM PDT 24	Jul 23 06:39:58 PM PDT 24	9297390799 ps
T174	/workspace/coverage/default/40.sram_ctrl_max_throughput.3120718494	Jul 23 06:34:41 PM PDT 24	Jul 23 06:36:35 PM PDT 24	504565916 ps
T175	/workspace/coverage/default/45.sram_ctrl_smoke.579213676	Jul 23 06:35:16 PM PDT 24	Jul 23 06:37:24 PM PDT 24	786938071 ps
T176	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2940600138	Jul 23 06:33:17 PM PDT 24	Jul 23 06:35:56 PM PDT 24	159689365 ps
T177	/workspace/coverage/default/8.sram_ctrl_smoke.3900886410	Jul 23 06:31:57 PM PDT 24	Jul 23 06:32:51 PM PDT 24	2028848755 ps
T99	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.770213765	Jul 23 06:35:09 PM PDT 24	Jul 23 06:37:35 PM PDT 24	6571197709 ps
T84	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.576032818	Jul 23 06:32:25 PM PDT 24	Jul 23 06:40:16 PM PDT 24	10787769430 ps
T100	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4128240777	Jul 23 06:35:29 PM PDT 24	Jul 23 06:40:37 PM PDT 24	3819765224 ps
T178	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1888850573	Jul 23 06:31:52 PM PDT 24	Jul 23 06:34:34 PM PDT 24	6289562479 ps
T179	/workspace/coverage/default/39.sram_ctrl_mem_walk.3165405841	Jul 23 06:34:36 PM PDT 24	Jul 23 06:34:43 PM PDT 24	100539220 ps
T46	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1070174784	Jul 23 06:34:41 PM PDT 24	Jul 23 06:34:50 PM PDT 24	1142838714 ps
T180	/workspace/coverage/default/41.sram_ctrl_bijection.1033997605	Jul 23 06:34:51 PM PDT 24	Jul 23 06:36:02 PM PDT 24	3919454566 ps
T181	/workspace/coverage/default/4.sram_ctrl_max_throughput.1208681931	Jul 23 06:31:46 PM PDT 24	Jul 23 06:32:02 PM PDT 24	205393508 ps
T182	/workspace/coverage/default/42.sram_ctrl_lc_escalation.4107808413	Jul 23 06:34:54 PM PDT 24	Jul 23 06:35:02 PM PDT 24	1728426985 ps
T183	/workspace/coverage/default/35.sram_ctrl_multiple_keys.1503207436	Jul 23 06:34:03 PM PDT 24	Jul 23 06:52:06 PM PDT 24	27971714046 ps
T184	/workspace/coverage/default/15.sram_ctrl_ram_cfg.3983881439	Jul 23 06:32:24 PM PDT 24	Jul 23 06:32:33 PM PDT 24	93874999 ps
T185	/workspace/coverage/default/44.sram_ctrl_lc_escalation.3550799750	Jul 23 06:35:11 PM PDT 24	Jul 23 06:35:17 PM PDT 24	554703556 ps
T186	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.810644455	Jul 23 06:32:50 PM PDT 24	Jul 23 06:33:00 PM PDT 24	232295429 ps
T187	/workspace/coverage/default/23.sram_ctrl_lc_escalation.959694039	Jul 23 06:32:49 PM PDT 24	Jul 23 06:32:55 PM PDT 24	357852758 ps
T188	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3323989267	Jul 23 06:33:33 PM PDT 24	Jul 23 06:37:07 PM PDT 24	2316842698 ps
T189	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4014541604	Jul 23 06:35:10 PM PDT 24	Jul 23 06:41:52 PM PDT 24	20056128941 ps
T190	/workspace/coverage/default/13.sram_ctrl_multiple_keys.3946481796	Jul 23 06:32:10 PM PDT 24	Jul 23 06:37:42 PM PDT 24	2339203720 ps
T191	/workspace/coverage/default/24.sram_ctrl_lc_escalation.2512213620	Jul 23 06:32:59 PM PDT 24	Jul 23 06:33:10 PM PDT 24	6496221817 ps
T192	/workspace/coverage/default/2.sram_ctrl_stress_all.584254300	Jul 23 06:31:48 PM PDT 24	Jul 23 06:56:59 PM PDT 24	28500230179 ps
T193	/workspace/coverage/default/32.sram_ctrl_alert_test.4099013658	Jul 23 06:33:44 PM PDT 24	Jul 23 06:33:46 PM PDT 24	28544845 ps
T194	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2080120697	Jul 23 06:32:48 PM PDT 24	Jul 23 06:53:07 PM PDT 24	9708048194 ps
T195	/workspace/coverage/default/7.sram_ctrl_executable.2791691302	Jul 23 06:31:59 PM PDT 24	Jul 23 07:10:32 PM PDT 24	29471429326 ps
T196	/workspace/coverage/default/47.sram_ctrl_multiple_keys.2374081680	Jul 23 06:35:44 PM PDT 24	Jul 23 06:56:58 PM PDT 24	57982816477 ps
T47	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.948648051	Jul 23 06:32:09 PM PDT 24	Jul 23 06:32:23 PM PDT 24	109060887 ps
T197	/workspace/coverage/default/30.sram_ctrl_alert_test.818963155	Jul 23 06:33:35 PM PDT 24	Jul 23 06:33:37 PM PDT 24	12684958 ps
T198	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1354906086	Jul 23 06:32:50 PM PDT 24	Jul 23 06:32:58 PM PDT 24	216179563 ps
T199	/workspace/coverage/default/37.sram_ctrl_smoke.529489706	Jul 23 06:34:21 PM PDT 24	Jul 23 06:34:29 PM PDT 24	165859335 ps
T200	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3532336338	Jul 23 06:35:27 PM PDT 24	Jul 23 06:36:00 PM PDT 24	204912498 ps
T201	/workspace/coverage/default/45.sram_ctrl_alert_test.594115201	Jul 23 06:35:26 PM PDT 24	Jul 23 06:35:28 PM PDT 24	16414166 ps
T202	/workspace/coverage/default/23.sram_ctrl_mem_walk.673023215	Jul 23 06:32:50 PM PDT 24	Jul 23 06:32:58 PM PDT 24	240348050 ps
T203	/workspace/coverage/default/17.sram_ctrl_executable.805143044	Jul 23 06:32:23 PM PDT 24	Jul 23 06:44:53 PM PDT 24	9903835265 ps
T204	/workspace/coverage/default/37.sram_ctrl_mem_walk.880337130	Jul 23 06:34:19 PM PDT 24	Jul 23 06:34:31 PM PDT 24	821297585 ps
T205	/workspace/coverage/default/16.sram_ctrl_max_throughput.3582410810	Jul 23 06:32:25 PM PDT 24	Jul 23 06:32:38 PM PDT 24	102271664 ps
T133	/workspace/coverage/default/31.sram_ctrl_executable.86668563	Jul 23 06:33:34 PM PDT 24	Jul 23 07:01:58 PM PDT 24	14552211303 ps
T206	/workspace/coverage/default/3.sram_ctrl_stress_all.776404559	Jul 23 06:31:46 PM PDT 24	Jul 23 07:09:54 PM PDT 24	25824883295 ps
T207	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1206402664	Jul 23 06:34:55 PM PDT 24	Jul 23 06:57:37 PM PDT 24	12447189835 ps
T208	/workspace/coverage/default/48.sram_ctrl_multiple_keys.1456130602	Jul 23 06:35:47 PM PDT 24	Jul 23 06:45:16 PM PDT 24	2059628480 ps
T209	/workspace/coverage/default/35.sram_ctrl_executable.1943081126	Jul 23 06:34:12 PM PDT 24	Jul 23 06:47:00 PM PDT 24	19519708390 ps
T210	/workspace/coverage/default/1.sram_ctrl_lc_escalation.1521422677	Jul 23 06:31:39 PM PDT 24	Jul 23 06:31:57 PM PDT 24	1490101109 ps
T211	/workspace/coverage/default/8.sram_ctrl_lc_escalation.1616280806	Jul 23 06:32:01 PM PDT 24	Jul 23 06:32:13 PM PDT 24	324728766 ps
T212	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2854333905	Jul 23 06:32:31 PM PDT 24	Jul 23 06:37:56 PM PDT 24	6651870952 ps
T213	/workspace/coverage/default/33.sram_ctrl_bijection.3681835658	Jul 23 06:33:45 PM PDT 24	Jul 23 06:34:26 PM PDT 24	2492303158 ps
T48	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3916138865	Jul 23 06:32:03 PM PDT 24	Jul 23 06:32:21 PM PDT 24	345185033 ps
T214	/workspace/coverage/default/48.sram_ctrl_stress_all.3918616814	Jul 23 06:35:56 PM PDT 24	Jul 23 06:59:59 PM PDT 24	137618631864 ps
T215	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2712518733	Jul 23 06:35:21 PM PDT 24	Jul 23 06:37:30 PM PDT 24	5589602740 ps
T216	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1537886702	Jul 23 06:33:55 PM PDT 24	Jul 23 06:37:59 PM PDT 24	6133135379 ps
T217	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1558028662	Jul 23 06:32:23 PM PDT 24	Jul 23 06:36:31 PM PDT 24	4915988568 ps
T218	/workspace/coverage/default/8.sram_ctrl_max_throughput.2943336418	Jul 23 06:31:57 PM PDT 24	Jul 23 06:32:06 PM PDT 24	73256770 ps
T219	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.227237491	Jul 23 06:32:30 PM PDT 24	Jul 23 06:52:49 PM PDT 24	6210611158 ps
T39	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.526821698	Jul 23 06:33:11 PM PDT 24	Jul 23 06:34:04 PM PDT 24	1278280705 ps
T220	/workspace/coverage/default/30.sram_ctrl_bijection.2621715604	Jul 23 06:33:29 PM PDT 24	Jul 23 06:34:02 PM PDT 24	3913044868 ps
T221	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2268420516	Jul 23 06:33:43 PM PDT 24	Jul 23 06:33:47 PM PDT 24	331857340 ps
T222	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3562311095	Jul 23 06:33:55 PM PDT 24	Jul 23 06:41:53 PM PDT 24	92886413769 ps
T223	/workspace/coverage/default/19.sram_ctrl_partial_access.3958360582	Jul 23 06:32:31 PM PDT 24	Jul 23 06:32:38 PM PDT 24	65987870 ps
T224	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3213091238	Jul 23 06:32:14 PM PDT 24	Jul 23 06:56:58 PM PDT 24	4787094426 ps
T225	/workspace/coverage/default/36.sram_ctrl_max_throughput.2186110235	Jul 23 06:34:13 PM PDT 24	Jul 23 06:35:53 PM PDT 24	444520475 ps
T226	/workspace/coverage/default/13.sram_ctrl_smoke.3926709753	Jul 23 06:32:15 PM PDT 24	Jul 23 06:35:17 PM PDT 24	3178731652 ps
T227	/workspace/coverage/default/14.sram_ctrl_lc_escalation.2353177326	Jul 23 06:32:15 PM PDT 24	Jul 23 06:32:32 PM PDT 24	1821591248 ps
T228	/workspace/coverage/default/12.sram_ctrl_lc_escalation.522702325	Jul 23 06:32:10 PM PDT 24	Jul 23 06:32:23 PM PDT 24	228784855 ps
T229	/workspace/coverage/default/37.sram_ctrl_executable.2400773369	Jul 23 06:34:20 PM PDT 24	Jul 23 06:57:38 PM PDT 24	6169288641 ps
T230	/workspace/coverage/default/7.sram_ctrl_bijection.4279530087	Jul 23 06:31:56 PM PDT 24	Jul 23 06:32:50 PM PDT 24	679311514 ps
T231	/workspace/coverage/default/16.sram_ctrl_regwen.896307518	Jul 23 06:32:23 PM PDT 24	Jul 23 06:34:37 PM PDT 24	1041978514 ps
T232	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2907972	Jul 23 06:35:48 PM PDT 24	Jul 23 06:37:53 PM PDT 24	816819563 ps
T233	/workspace/coverage/default/38.sram_ctrl_partial_access.1703496408	Jul 23 06:34:25 PM PDT 24	Jul 23 06:34:31 PM PDT 24	269801400 ps
T234	/workspace/coverage/default/35.sram_ctrl_lc_escalation.1699728661	Jul 23 06:34:12 PM PDT 24	Jul 23 06:34:18 PM PDT 24	1774381036 ps
T235	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3323407407	Jul 23 06:32:30 PM PDT 24	Jul 23 06:32:41 PM PDT 24	156667750 ps
T236	/workspace/coverage/default/12.sram_ctrl_regwen.2987436970	Jul 23 06:32:15 PM PDT 24	Jul 23 06:55:16 PM PDT 24	13653452131 ps
T237	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.87934781	Jul 23 06:35:20 PM PDT 24	Jul 23 06:38:28 PM PDT 24	303966287 ps
T238	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1288307048	Jul 23 06:33:27 PM PDT 24	Jul 23 06:33:30 PM PDT 24	41999678 ps
T58	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3560941272	Jul 23 06:32:09 PM PDT 24	Jul 23 06:38:27 PM PDT 24	3693173253 ps
T239	/workspace/coverage/default/33.sram_ctrl_ram_cfg.3720584481	Jul 23 06:33:49 PM PDT 24	Jul 23 06:33:51 PM PDT 24	125641963 ps
T240	/workspace/coverage/default/15.sram_ctrl_partial_access.645639835	Jul 23 06:32:24 PM PDT 24	Jul 23 06:32:35 PM PDT 24	155119083 ps
T241	/workspace/coverage/default/46.sram_ctrl_executable.3655166295	Jul 23 06:35:32 PM PDT 24	Jul 23 06:58:03 PM PDT 24	24585619028 ps
T15	/workspace/coverage/default/0.sram_ctrl_sec_cm.3429234638	Jul 23 06:31:43 PM PDT 24	Jul 23 06:31:57 PM PDT 24	1633655500 ps
T25	/workspace/coverage/default/34.sram_ctrl_lc_escalation.116461586	Jul 23 06:33:55 PM PDT 24	Jul 23 06:34:02 PM PDT 24	830354161 ps
T26	/workspace/coverage/default/9.sram_ctrl_partial_access.2006302538	Jul 23 06:32:06 PM PDT 24	Jul 23 06:34:44 PM PDT 24	263057659 ps
T27	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.45614283	Jul 23 06:32:22 PM PDT 24	Jul 23 06:40:16 PM PDT 24	18230574843 ps
T28	/workspace/coverage/default/5.sram_ctrl_partial_access.3918910017	Jul 23 06:31:51 PM PDT 24	Jul 23 06:32:05 PM PDT 24	686292700 ps
T29	/workspace/coverage/default/16.sram_ctrl_multiple_keys.430377868	Jul 23 06:32:24 PM PDT 24	Jul 23 06:54:33 PM PDT 24	6134110329 ps
T30	/workspace/coverage/default/46.sram_ctrl_alert_test.3922702610	Jul 23 06:35:32 PM PDT 24	Jul 23 06:35:33 PM PDT 24	17621642 ps
T31	/workspace/coverage/default/34.sram_ctrl_smoke.4043498091	Jul 23 06:33:55 PM PDT 24	Jul 23 06:34:11 PM PDT 24	823160607 ps
T32	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3808558328	Jul 23 06:31:56 PM PDT 24	Jul 23 06:32:09 PM PDT 24	92472368 ps
T33	/workspace/coverage/default/0.sram_ctrl_mem_walk.1704227090	Jul 23 06:31:35 PM PDT 24	Jul 23 06:31:52 PM PDT 24	291928078 ps
T242	/workspace/coverage/default/41.sram_ctrl_stress_all.1619465431	Jul 23 06:34:53 PM PDT 24	Jul 23 06:59:41 PM PDT 24	97260125019 ps
T243	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1809850565	Jul 23 06:31:44 PM PDT 24	Jul 23 06:32:01 PM PDT 24	364538026 ps
T244	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.664337659	Jul 23 06:35:31 PM PDT 24	Jul 23 06:35:37 PM PDT 24	1093843584 ps
T245	/workspace/coverage/default/47.sram_ctrl_smoke.495565289	Jul 23 06:35:32 PM PDT 24	Jul 23 06:38:02 PM PDT 24	753526815 ps
T246	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.289279220	Jul 23 06:32:24 PM PDT 24	Jul 23 06:32:51 PM PDT 24	606133584 ps
T59	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1533359130	Jul 23 06:33:06 PM PDT 24	Jul 23 06:33:15 PM PDT 24	960071912 ps
T110	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3498887583	Jul 23 06:32:03 PM PDT 24	Jul 23 06:34:17 PM PDT 24	1370818429 ps
T111	/workspace/coverage/default/12.sram_ctrl_alert_test.2944419168	Jul 23 06:32:11 PM PDT 24	Jul 23 06:32:23 PM PDT 24	24558103 ps
T112	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4286509377	Jul 23 06:31:50 PM PDT 24	Jul 23 06:38:06 PM PDT 24	19833112162 ps
T113	/workspace/coverage/default/40.sram_ctrl_mem_walk.3495046619	Jul 23 06:34:43 PM PDT 24	Jul 23 06:34:52 PM PDT 24	300105554 ps
T114	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1469891798	Jul 23 06:33:10 PM PDT 24	Jul 23 06:33:16 PM PDT 24	525720422 ps
T115	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.995095224	Jul 23 06:32:16 PM PDT 24	Jul 23 06:35:06 PM PDT 24	2644353537 ps
T116	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2475470966	Jul 23 06:33:33 PM PDT 24	Jul 23 06:36:00 PM PDT 24	585800961 ps
T117	/workspace/coverage/default/40.sram_ctrl_ram_cfg.1637687199	Jul 23 06:34:41 PM PDT 24	Jul 23 06:34:44 PM PDT 24	79328049 ps
T118	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2776101982	Jul 23 06:32:47 PM PDT 24	Jul 23 06:35:56 PM PDT 24	7963465181 ps
T247	/workspace/coverage/default/39.sram_ctrl_smoke.1172360178	Jul 23 06:34:30 PM PDT 24	Jul 23 06:34:34 PM PDT 24	82307455 ps
T248	/workspace/coverage/default/0.sram_ctrl_partial_access.153215657	Jul 23 06:31:47 PM PDT 24	Jul 23 06:32:11 PM PDT 24	3033295729 ps
T249	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.234420167	Jul 23 06:32:02 PM PDT 24	Jul 23 06:34:03 PM PDT 24	5561308560 ps
T250	/workspace/coverage/default/14.sram_ctrl_partial_access.1313668380	Jul 23 06:32:18 PM PDT 24	Jul 23 06:32:32 PM PDT 24	2386195051 ps
T251	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.194729496	Jul 23 06:34:13 PM PDT 24	Jul 23 06:48:40 PM PDT 24	3244362598 ps
T252	/workspace/coverage/default/29.sram_ctrl_bijection.1878320527	Jul 23 06:33:23 PM PDT 24	Jul 23 06:34:01 PM PDT 24	598520965 ps
T253	/workspace/coverage/default/12.sram_ctrl_bijection.3336601	Jul 23 06:32:09 PM PDT 24	Jul 23 06:33:13 PM PDT 24	2989570008 ps
T254	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3931499752	Jul 23 06:31:50 PM PDT 24	Jul 23 06:37:23 PM PDT 24	38048833151 ps
T255	/workspace/coverage/default/25.sram_ctrl_alert_test.298696241	Jul 23 06:33:12 PM PDT 24	Jul 23 06:33:14 PM PDT 24	14105092 ps
T256	/workspace/coverage/default/26.sram_ctrl_multiple_keys.617290707	Jul 23 06:33:11 PM PDT 24	Jul 23 06:40:33 PM PDT 24	35549141690 ps
T257	/workspace/coverage/default/6.sram_ctrl_stress_all.4150564158	Jul 23 06:31:51 PM PDT 24	Jul 23 07:02:40 PM PDT 24	25943587959 ps
T258	/workspace/coverage/default/33.sram_ctrl_smoke.4192208903	Jul 23 06:33:44 PM PDT 24	Jul 23 06:33:56 PM PDT 24	637540776 ps
T259	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.375902674	Jul 23 06:33:23 PM PDT 24	Jul 23 06:33:29 PM PDT 24	214740551 ps
T260	/workspace/coverage/default/30.sram_ctrl_mem_walk.2799574465	Jul 23 06:33:31 PM PDT 24	Jul 23 06:33:38 PM PDT 24	997874592 ps
T261	/workspace/coverage/default/6.sram_ctrl_multiple_keys.1877310449	Jul 23 06:31:55 PM PDT 24	Jul 23 06:48:42 PM PDT 24	47767216175 ps
T262	/workspace/coverage/default/28.sram_ctrl_partial_access.2614879414	Jul 23 06:33:17 PM PDT 24	Jul 23 06:33:25 PM PDT 24	150180293 ps
T263	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.241184271	Jul 23 06:32:15 PM PDT 24	Jul 23 06:36:14 PM PDT 24	2362947770 ps
T264	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1421482272	Jul 23 06:35:20 PM PDT 24	Jul 23 06:35:25 PM PDT 24	64640200 ps
T265	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2427893998	Jul 23 06:34:49 PM PDT 24	Jul 23 06:40:50 PM PDT 24	58709531055 ps
T266	/workspace/coverage/default/48.sram_ctrl_executable.3683024683	Jul 23 06:35:48 PM PDT 24	Jul 23 06:44:14 PM PDT 24	2251286600 ps
T267	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2632508911	Jul 23 06:33:07 PM PDT 24	Jul 23 06:33:53 PM PDT 24	129281697 ps
T268	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2483185487	Jul 23 06:34:48 PM PDT 24	Jul 23 06:43:16 PM PDT 24	39103974086 ps
T269	/workspace/coverage/default/0.sram_ctrl_executable.4247799049	Jul 23 06:31:35 PM PDT 24	Jul 23 06:39:21 PM PDT 24	8103414906 ps
T270	/workspace/coverage/default/48.sram_ctrl_mem_walk.4078949558	Jul 23 06:35:54 PM PDT 24	Jul 23 06:36:01 PM PDT 24	1494142262 ps
T271	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.682652576	Jul 23 06:31:52 PM PDT 24	Jul 23 06:46:09 PM PDT 24	4188777454 ps
T272	/workspace/coverage/default/7.sram_ctrl_multiple_keys.1403128953	Jul 23 06:31:57 PM PDT 24	Jul 23 06:40:38 PM PDT 24	3097700280 ps
T273	/workspace/coverage/default/40.sram_ctrl_regwen.2230400260	Jul 23 06:34:41 PM PDT 24	Jul 23 07:00:49 PM PDT 24	18897953349 ps
T274	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1293964388	Jul 23 06:32:45 PM PDT 24	Jul 23 06:38:12 PM PDT 24	1665518463 ps
T275	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2124158689	Jul 23 06:32:39 PM PDT 24	Jul 23 07:00:24 PM PDT 24	22002564208 ps
T276	/workspace/coverage/default/7.sram_ctrl_stress_all.1548736922	Jul 23 06:31:57 PM PDT 24	Jul 23 06:48:15 PM PDT 24	42658139737 ps
T277	/workspace/coverage/default/17.sram_ctrl_bijection.2897210137	Jul 23 06:32:23 PM PDT 24	Jul 23 06:33:53 PM PDT 24	3994687332 ps
T278	/workspace/coverage/default/39.sram_ctrl_stress_all.1881985906	Jul 23 06:34:36 PM PDT 24	Jul 23 06:57:58 PM PDT 24	69756308925 ps
T279	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2386577013	Jul 23 06:32:24 PM PDT 24	Jul 23 06:32:37 PM PDT 24	95867826 ps
T280	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3541059374	Jul 23 06:33:41 PM PDT 24	Jul 23 06:34:28 PM PDT 24	121305932 ps
T281	/workspace/coverage/default/30.sram_ctrl_ram_cfg.507838400	Jul 23 06:33:28 PM PDT 24	Jul 23 06:33:31 PM PDT 24	32210035 ps
T282	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.202803825	Jul 23 06:34:48 PM PDT 24	Jul 23 06:36:38 PM PDT 24	192258148 ps
T283	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1140701189	Jul 23 06:31:52 PM PDT 24	Jul 23 06:35:58 PM PDT 24	36679493220 ps
T284	/workspace/coverage/default/20.sram_ctrl_regwen.1502716195	Jul 23 06:32:38 PM PDT 24	Jul 23 06:50:56 PM PDT 24	4410656808 ps
T285	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2041934327	Jul 23 06:32:08 PM PDT 24	Jul 23 06:32:21 PM PDT 24	217986945 ps
T286	/workspace/coverage/default/28.sram_ctrl_bijection.4173104000	Jul 23 06:33:20 PM PDT 24	Jul 23 06:34:28 PM PDT 24	2165217679 ps
T287	/workspace/coverage/default/34.sram_ctrl_ram_cfg.3026176409	Jul 23 06:34:01 PM PDT 24	Jul 23 06:34:04 PM PDT 24	32311177 ps
T288	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1959381865	Jul 23 06:31:51 PM PDT 24	Jul 23 06:34:04 PM PDT 24	218586772 ps
T289	/workspace/coverage/default/2.sram_ctrl_multiple_keys.3689951075	Jul 23 06:31:42 PM PDT 24	Jul 23 06:48:02 PM PDT 24	27075344441 ps
T290	/workspace/coverage/default/28.sram_ctrl_ram_cfg.4209296463	Jul 23 06:33:16 PM PDT 24	Jul 23 06:33:18 PM PDT 24	28708207 ps
T291	/workspace/coverage/default/47.sram_ctrl_max_throughput.336719821	Jul 23 06:35:44 PM PDT 24	Jul 23 06:36:01 PM PDT 24	113453590 ps
T292	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3204048592	Jul 23 06:32:58 PM PDT 24	Jul 23 06:39:58 PM PDT 24	17894080065 ps
T293	/workspace/coverage/default/21.sram_ctrl_mem_walk.1764997463	Jul 23 06:32:42 PM PDT 24	Jul 23 06:32:48 PM PDT 24	491452503 ps
T294	/workspace/coverage/default/7.sram_ctrl_ram_cfg.3559792772	Jul 23 06:31:58 PM PDT 24	Jul 23 06:32:07 PM PDT 24	29634268 ps
T295	/workspace/coverage/default/49.sram_ctrl_executable.3320469094	Jul 23 06:35:59 PM PDT 24	Jul 23 06:36:34 PM PDT 24	866983811 ps
T296	/workspace/coverage/default/13.sram_ctrl_executable.2306736563	Jul 23 06:32:16 PM PDT 24	Jul 23 06:43:35 PM PDT 24	79933832904 ps
T297	/workspace/coverage/default/7.sram_ctrl_max_throughput.2342450843	Jul 23 06:31:52 PM PDT 24	Jul 23 06:32:19 PM PDT 24	300648598 ps
T298	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1074829226	Jul 23 06:31:51 PM PDT 24	Jul 23 06:35:42 PM PDT 24	1044338079 ps
T40	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3365344283	Jul 23 06:35:33 PM PDT 24	Jul 23 06:38:10 PM PDT 24	4024095569 ps
T299	/workspace/coverage/default/1.sram_ctrl_alert_test.746379816	Jul 23 06:31:44 PM PDT 24	Jul 23 06:31:55 PM PDT 24	17538403 ps
T300	/workspace/coverage/default/0.sram_ctrl_ram_cfg.2027137430	Jul 23 06:31:47 PM PDT 24	Jul 23 06:31:58 PM PDT 24	27054692 ps
T301	/workspace/coverage/default/10.sram_ctrl_ram_cfg.3998556984	Jul 23 06:32:06 PM PDT 24	Jul 23 06:32:15 PM PDT 24	190197311 ps
T302	/workspace/coverage/default/16.sram_ctrl_executable.3372539804	Jul 23 06:32:24 PM PDT 24	Jul 23 06:48:36 PM PDT 24	3305498101 ps
T303	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3709351855	Jul 23 06:35:24 PM PDT 24	Jul 23 06:44:18 PM PDT 24	22411509972 ps
T304	/workspace/coverage/default/49.sram_ctrl_lc_escalation.2304150696	Jul 23 06:35:58 PM PDT 24	Jul 23 06:36:02 PM PDT 24	540432554 ps
T103	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1299224812	Jul 23 06:35:17 PM PDT 24	Jul 23 06:37:58 PM PDT 24	3204160249 ps