Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45535696	1			T1	40071		T3	583819		T4	10889
triple_byte_access	2570552	1			T1	36148		T3	11728		T4	225
halfword_access	3856213	1			T1	53975		T3	17657		T4	324
byte_access	5151837	1			T1	72292		T3	23519		T4	466
zero_access	1298310	1			T1	17928		T3	5760		T4	116

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29152884

1

T1

110079

T3

321854

T4

5969

auto[1]

29259724

1

T1

110335

T3

320629

T4

6051

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22719501	1			T1	20069		T3	292597		T4	5402
auto[0]	triple_byte_access	1281749	1			T1	18095		T3	5874		T4	107
auto[0]	halfword_access	1924844	1			T1	27015		T3	8739		T4	171
auto[0]	byte_access	2573371	1			T1	35946		T3	11726		T4	231
auto[0]	zero_access	653419	1			T1	8954		T3	2918		T4	58
auto[1]	word_access	22816195	1			T1	20002		T3	291222		T4	5487
auto[1]	triple_byte_access	1288803	1			T1	18053		T3	5854		T4	118
auto[1]	halfword_access	1931369	1			T1	26960		T3	8918		T4	153
auto[1]	byte_access	2578466	1			T1	36346		T3	11793		T4	235
auto[1]	zero_access	644891	1			T1	8974		T3	2842		T4	58