Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146231678	1			T1	395010		T2	14930		T3	216664
instr_valid_dis	113597554	1			T1	395010		T2	14930		T3	199433
instr_en	21715276	1			T3	17231		T6	246656		T22	392090

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10325050	1			T11	82138		T6	144638		T19	10228
sram_ifetch_valid_disable	114332673	1			T1	395010		T2	14930		T3	199437
sram_ifetch_enable	21573955	1			T3	17227		T10	92566		T11	95360

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146231678	1			T1	395010		T2	14930		T3	216664
hw_debug_en_valid_off	114744127	1			T1	395010		T2	14930		T3	214422
hw_debug_en_on	21174150	1			T3	2242		T10	10994		T11	154924

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114332673	1			T1	395010		T2	14930		T3	199437
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101565927	1			T1	395010		T2	14930		T3	199433
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8242138	1			T3	4		T6	86772		T22	189436
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4111936	1			T11	27570		T6	37578		T19	10228
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1196864	1			T6	7730		T141	43288		T138	19198
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2323042	1			T6	196		T22	7002		T64	814
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4765732	1			T11	38174		T6	83138		T22	38766
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	959654	1			T64	33216		T138	19790		T120	10480
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2591088	1			T6	83138		T22	38766		T64	32972
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8012878	1			T11	80194		T6	185246		T19	17118
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3202324	1			T6	42908		T64	104586		T140	1056
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3264950	1			T6	51520		T22	77326		T141	102028

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7972531	1			T3	17227		T6	76550		T22	142644
lc_exec_en	8395540	1			T3	2242		T10	10994		T11	36556
valid_exec_dis	111322454	1			T1	395010		T2	14930		T3	199437
invalid_exec_dis	31899005	1			T3	17227		T10	92566		T11	177498