Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44569515	1			T1	36090		T2	1398		T3	63844
triple_byte_access	2510219	1			T1	32594		T2	1125		T3	529
halfword_access	3768395	1			T1	48336		T2	1838		T3	848
byte_access	5028027	1			T1	64410		T2	2469		T3	1145
zero_access	1265322	1			T1	16075		T2	635		T3	287

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28516355

1

T1

98975

T2

3789

T3

33281

auto[1]

28625123

1

T1

98530

T2

3676

T3

33372

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22234009	1			T1	18013		T2	714		T3	31865
auto[0]	triple_byte_access	1251784	1			T1	16293		T2	553		T3	280
auto[0]	halfword_access	1880995	1			T1	24222		T2	960		T3	429
auto[0]	byte_access	2513864	1			T1	32407		T2	1245		T3	574
auto[0]	zero_access	635703	1			T1	8040		T2	317		T3	133
auto[1]	word_access	22335506	1			T1	18077		T2	684		T3	31979
auto[1]	triple_byte_access	1258435	1			T1	16301		T2	572		T3	249
auto[1]	halfword_access	1887400	1			T1	24114		T2	878		T3	419
auto[1]	byte_access	2514163	1			T1	32003		T2	1224		T3	571
auto[1]	zero_access	629619	1			T1	8035		T2	318		T3	154