| T793 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1487381467 |
|
|
Jul 24 06:38:05 PM PDT 24 |
Jul 24 07:06:30 PM PDT 24 |
5053398116 ps |
| T794 |
/workspace/coverage/default/44.sram_ctrl_regwen.33127119 |
|
|
Jul 24 06:49:03 PM PDT 24 |
Jul 24 07:07:06 PM PDT 24 |
10825982031 ps |
| T795 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3047137761 |
|
|
Jul 24 06:47:40 PM PDT 24 |
Jul 24 06:47:43 PM PDT 24 |
87189094 ps |
| T796 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3312775308 |
|
|
Jul 24 06:44:56 PM PDT 24 |
Jul 24 06:45:24 PM PDT 24 |
104144100 ps |
| T797 |
/workspace/coverage/default/43.sram_ctrl_stress_all.190439230 |
|
|
Jul 24 06:48:59 PM PDT 24 |
Jul 24 07:16:36 PM PDT 24 |
94062092088 ps |
| T798 |
/workspace/coverage/default/41.sram_ctrl_alert_test.365135824 |
|
|
Jul 24 06:48:30 PM PDT 24 |
Jul 24 06:48:30 PM PDT 24 |
14760103 ps |
| T799 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1732007751 |
|
|
Jul 24 06:41:00 PM PDT 24 |
Jul 24 06:41:03 PM PDT 24 |
320665852 ps |
| T800 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3976034402 |
|
|
Jul 24 06:42:42 PM PDT 24 |
Jul 24 06:47:13 PM PDT 24 |
22517840832 ps |
| T801 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2634634312 |
|
|
Jul 24 06:41:52 PM PDT 24 |
Jul 24 06:42:04 PM PDT 24 |
1622827643 ps |
| T802 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2652758934 |
|
|
Jul 24 06:38:19 PM PDT 24 |
Jul 24 06:45:52 PM PDT 24 |
17002974601 ps |
| T803 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1926272880 |
|
|
Jul 24 06:46:57 PM PDT 24 |
Jul 24 06:47:00 PM PDT 24 |
84923887 ps |
| T804 |
/workspace/coverage/default/49.sram_ctrl_regwen.1070352750 |
|
|
Jul 24 06:50:45 PM PDT 24 |
Jul 24 07:26:20 PM PDT 24 |
67690105653 ps |
| T805 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2263628190 |
|
|
Jul 24 06:48:23 PM PDT 24 |
Jul 24 06:48:24 PM PDT 24 |
114254469 ps |
| T806 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1419065511 |
|
|
Jul 24 06:49:11 PM PDT 24 |
Jul 24 06:54:55 PM PDT 24 |
13815665543 ps |
| T807 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3192385401 |
|
|
Jul 24 06:38:18 PM PDT 24 |
Jul 24 06:57:05 PM PDT 24 |
26341020407 ps |
| T808 |
/workspace/coverage/default/35.sram_ctrl_smoke.3260384064 |
|
|
Jul 24 06:46:45 PM PDT 24 |
Jul 24 06:46:48 PM PDT 24 |
158534889 ps |
| T809 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.1529973920 |
|
|
Jul 24 06:47:05 PM PDT 24 |
Jul 24 06:49:23 PM PDT 24 |
214264221 ps |
| T810 |
/workspace/coverage/default/38.sram_ctrl_alert_test.566507303 |
|
|
Jul 24 06:47:45 PM PDT 24 |
Jul 24 06:47:46 PM PDT 24 |
18216589 ps |
| T811 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.495975805 |
|
|
Jul 24 06:39:30 PM PDT 24 |
Jul 24 06:52:58 PM PDT 24 |
1932486382 ps |
| T812 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4169191210 |
|
|
Jul 24 06:48:51 PM PDT 24 |
Jul 24 06:55:09 PM PDT 24 |
14226989727 ps |
| T813 |
/workspace/coverage/default/30.sram_ctrl_bijection.75703575 |
|
|
Jul 24 06:45:29 PM PDT 24 |
Jul 24 06:46:28 PM PDT 24 |
4699378033 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2391863825 |
|
|
Jul 24 06:37:29 PM PDT 24 |
Jul 24 06:52:33 PM PDT 24 |
11068728309 ps |
| T815 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2063153045 |
|
|
Jul 24 06:41:13 PM PDT 24 |
Jul 24 06:41:37 PM PDT 24 |
89120950 ps |
| T816 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.2040664152 |
|
|
Jul 24 06:47:23 PM PDT 24 |
Jul 24 06:47:35 PM PDT 24 |
1781450046 ps |
| T817 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1281924971 |
|
|
Jul 24 06:39:22 PM PDT 24 |
Jul 24 06:39:39 PM PDT 24 |
95555367 ps |
| T818 |
/workspace/coverage/default/31.sram_ctrl_bijection.1231234064 |
|
|
Jul 24 06:45:41 PM PDT 24 |
Jul 24 06:46:12 PM PDT 24 |
5289513163 ps |
| T819 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1617723983 |
|
|
Jul 24 06:48:41 PM PDT 24 |
Jul 24 06:50:31 PM PDT 24 |
296469119 ps |
| T820 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3353385079 |
|
|
Jul 24 06:42:24 PM PDT 24 |
Jul 24 07:02:15 PM PDT 24 |
4162858862 ps |
| T821 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1767638661 |
|
|
Jul 24 06:41:28 PM PDT 24 |
Jul 24 06:52:16 PM PDT 24 |
10295482018 ps |
| T822 |
/workspace/coverage/default/45.sram_ctrl_regwen.943148246 |
|
|
Jul 24 06:49:19 PM PDT 24 |
Jul 24 06:55:00 PM PDT 24 |
2299088299 ps |
| T823 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3043081585 |
|
|
Jul 24 06:46:25 PM PDT 24 |
Jul 24 06:55:08 PM PDT 24 |
1496331419 ps |
| T824 |
/workspace/coverage/default/29.sram_ctrl_regwen.1368164569 |
|
|
Jul 24 06:45:19 PM PDT 24 |
Jul 24 06:53:34 PM PDT 24 |
3057899417 ps |
| T825 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1263840976 |
|
|
Jul 24 06:48:52 PM PDT 24 |
Jul 24 06:48:52 PM PDT 24 |
184805461 ps |
| T826 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1150574861 |
|
|
Jul 24 06:44:36 PM PDT 24 |
Jul 24 06:44:44 PM PDT 24 |
2407926851 ps |
| T827 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.147792342 |
|
|
Jul 24 06:48:45 PM PDT 24 |
Jul 24 06:57:09 PM PDT 24 |
7466870013 ps |
| T828 |
/workspace/coverage/default/16.sram_ctrl_regwen.964051900 |
|
|
Jul 24 06:41:52 PM PDT 24 |
Jul 24 06:59:00 PM PDT 24 |
40697395065 ps |
| T829 |
/workspace/coverage/default/32.sram_ctrl_smoke.3396363425 |
|
|
Jul 24 06:46:00 PM PDT 24 |
Jul 24 06:46:19 PM PDT 24 |
10863422103 ps |
| T830 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3961585317 |
|
|
Jul 24 06:50:46 PM PDT 24 |
Jul 24 06:50:47 PM PDT 24 |
83058291 ps |
| T831 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3595795954 |
|
|
Jul 24 06:42:21 PM PDT 24 |
Jul 24 07:14:37 PM PDT 24 |
23946086574 ps |
| T832 |
/workspace/coverage/default/41.sram_ctrl_stress_all.25820081 |
|
|
Jul 24 06:48:29 PM PDT 24 |
Jul 24 07:04:45 PM PDT 24 |
15385225687 ps |
| T833 |
/workspace/coverage/default/7.sram_ctrl_bijection.3351125445 |
|
|
Jul 24 06:39:07 PM PDT 24 |
Jul 24 06:39:29 PM PDT 24 |
5314510831 ps |
| T834 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1967145841 |
|
|
Jul 24 06:47:04 PM PDT 24 |
Jul 24 06:47:16 PM PDT 24 |
233564152 ps |
| T835 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1588714212 |
|
|
Jul 24 06:50:52 PM PDT 24 |
Jul 24 06:50:58 PM PDT 24 |
701632659 ps |
| T836 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3490846466 |
|
|
Jul 24 06:43:17 PM PDT 24 |
Jul 24 06:43:23 PM PDT 24 |
383543426 ps |
| T837 |
/workspace/coverage/default/27.sram_ctrl_alert_test.2457475158 |
|
|
Jul 24 06:44:43 PM PDT 24 |
Jul 24 06:44:43 PM PDT 24 |
24613954 ps |
| T838 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2510766572 |
|
|
Jul 24 06:42:48 PM PDT 24 |
Jul 24 06:57:00 PM PDT 24 |
4967085259 ps |
| T839 |
/workspace/coverage/default/1.sram_ctrl_bijection.2227731737 |
|
|
Jul 24 06:37:01 PM PDT 24 |
Jul 24 06:37:49 PM PDT 24 |
1774496760 ps |
| T840 |
/workspace/coverage/default/21.sram_ctrl_smoke.7479866 |
|
|
Jul 24 06:42:48 PM PDT 24 |
Jul 24 06:42:50 PM PDT 24 |
75600636 ps |
| T841 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.4134873852 |
|
|
Jul 24 06:47:22 PM PDT 24 |
Jul 24 06:47:26 PM PDT 24 |
247476412 ps |
| T842 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.302916012 |
|
|
Jul 24 06:43:16 PM PDT 24 |
Jul 24 06:44:24 PM PDT 24 |
533260229 ps |
| T843 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2443410503 |
|
|
Jul 24 06:42:48 PM PDT 24 |
Jul 24 07:17:21 PM PDT 24 |
31145894313 ps |
| T844 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3001181784 |
|
|
Jul 24 06:49:31 PM PDT 24 |
Jul 24 06:49:40 PM PDT 24 |
595701268 ps |
| T845 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3734541090 |
|
|
Jul 24 06:40:39 PM PDT 24 |
Jul 24 06:40:45 PM PDT 24 |
368127974 ps |
| T846 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1955394306 |
|
|
Jul 24 06:42:22 PM PDT 24 |
Jul 24 06:42:31 PM PDT 24 |
362604882 ps |
| T847 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.4073379501 |
|
|
Jul 24 06:48:05 PM PDT 24 |
Jul 24 06:48:10 PM PDT 24 |
251014397 ps |
| T848 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.4176644460 |
|
|
Jul 24 06:40:36 PM PDT 24 |
Jul 24 06:44:47 PM PDT 24 |
2493928148 ps |
| T849 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3025236306 |
|
|
Jul 24 06:49:03 PM PDT 24 |
Jul 24 06:49:09 PM PDT 24 |
309486754 ps |
| T850 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2985590145 |
|
|
Jul 24 06:42:44 PM PDT 24 |
Jul 24 06:42:53 PM PDT 24 |
776618957 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_executable.1067935229 |
|
|
Jul 24 06:36:44 PM PDT 24 |
Jul 24 06:56:29 PM PDT 24 |
54924278351 ps |
| T852 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3125504256 |
|
|
Jul 24 06:42:23 PM PDT 24 |
Jul 24 06:47:43 PM PDT 24 |
3339007346 ps |
| T853 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3400985046 |
|
|
Jul 24 06:49:21 PM PDT 24 |
Jul 24 07:04:50 PM PDT 24 |
46694772182 ps |
| T854 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2926422266 |
|
|
Jul 24 06:41:48 PM PDT 24 |
Jul 24 06:50:02 PM PDT 24 |
4585467865 ps |
| T855 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1537315182 |
|
|
Jul 24 06:41:00 PM PDT 24 |
Jul 24 07:29:59 PM PDT 24 |
208950458124 ps |
| T856 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1214009829 |
|
|
Jul 24 06:38:50 PM PDT 24 |
Jul 24 06:41:28 PM PDT 24 |
1308408538 ps |
| T857 |
/workspace/coverage/default/5.sram_ctrl_smoke.904827817 |
|
|
Jul 24 06:38:26 PM PDT 24 |
Jul 24 06:38:28 PM PDT 24 |
198278689 ps |
| T858 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.603550913 |
|
|
Jul 24 06:49:21 PM PDT 24 |
Jul 24 06:49:33 PM PDT 24 |
1821025382 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_alert_test.3777554136 |
|
|
Jul 24 06:48:47 PM PDT 24 |
Jul 24 06:48:47 PM PDT 24 |
44415805 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3182888809 |
|
|
Jul 24 06:42:23 PM PDT 24 |
Jul 24 06:43:06 PM PDT 24 |
183008176 ps |
| T861 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.316070432 |
|
|
Jul 24 06:41:45 PM PDT 24 |
Jul 24 06:42:50 PM PDT 24 |
112004698 ps |
| T862 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.345247709 |
|
|
Jul 24 06:40:36 PM PDT 24 |
Jul 24 06:40:43 PM PDT 24 |
75775921 ps |
| T863 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.590386091 |
|
|
Jul 24 06:43:59 PM PDT 24 |
Jul 24 06:44:00 PM PDT 24 |
49358853 ps |
| T864 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1738666086 |
|
|
Jul 24 06:48:57 PM PDT 24 |
Jul 24 06:52:23 PM PDT 24 |
9723151669 ps |
| T865 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2306567310 |
|
|
Jul 24 06:49:03 PM PDT 24 |
Jul 24 06:50:20 PM PDT 24 |
201382640 ps |
| T866 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1614130149 |
|
|
Jul 24 06:47:22 PM PDT 24 |
Jul 24 06:52:42 PM PDT 24 |
1933336822 ps |
| T867 |
/workspace/coverage/default/47.sram_ctrl_smoke.3700511665 |
|
|
Jul 24 06:49:37 PM PDT 24 |
Jul 24 06:49:48 PM PDT 24 |
1180539401 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2042698963 |
|
|
Jul 24 06:50:44 PM PDT 24 |
Jul 24 06:52:32 PM PDT 24 |
129871209 ps |
| T869 |
/workspace/coverage/default/17.sram_ctrl_bijection.3575988352 |
|
|
Jul 24 06:42:04 PM PDT 24 |
Jul 24 06:42:44 PM PDT 24 |
642813957 ps |
| T870 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.11046890 |
|
|
Jul 24 06:45:47 PM PDT 24 |
Jul 24 06:45:56 PM PDT 24 |
690573862 ps |
| T871 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4250139235 |
|
|
Jul 24 06:36:51 PM PDT 24 |
Jul 24 06:39:08 PM PDT 24 |
6335245487 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_bijection.2421136403 |
|
|
Jul 24 06:49:26 PM PDT 24 |
Jul 24 06:50:02 PM PDT 24 |
2468296071 ps |
| T873 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3480319233 |
|
|
Jul 24 06:47:52 PM PDT 24 |
Jul 24 06:52:57 PM PDT 24 |
3046227901 ps |
| T874 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3938934690 |
|
|
Jul 24 06:47:45 PM PDT 24 |
Jul 24 07:14:42 PM PDT 24 |
22481680280 ps |
| T875 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1353625684 |
|
|
Jul 24 06:49:26 PM PDT 24 |
Jul 24 06:52:03 PM PDT 24 |
1628568231 ps |
| T876 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.260624557 |
|
|
Jul 24 06:50:44 PM PDT 24 |
Jul 24 06:50:47 PM PDT 24 |
351347683 ps |
| T877 |
/workspace/coverage/default/37.sram_ctrl_smoke.2894387390 |
|
|
Jul 24 06:47:17 PM PDT 24 |
Jul 24 06:47:44 PM PDT 24 |
1320385993 ps |
| T878 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.4132374141 |
|
|
Jul 24 06:36:43 PM PDT 24 |
Jul 24 06:36:51 PM PDT 24 |
1927472378 ps |
| T879 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.82837831 |
|
|
Jul 24 06:44:31 PM PDT 24 |
Jul 24 06:46:23 PM PDT 24 |
470109588 ps |
| T880 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2934688683 |
|
|
Jul 24 06:49:33 PM PDT 24 |
Jul 24 06:57:29 PM PDT 24 |
1531172345 ps |
| T881 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2137908188 |
|
|
Jul 24 06:46:36 PM PDT 24 |
Jul 24 06:46:42 PM PDT 24 |
346035808 ps |
| T882 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2835329166 |
|
|
Jul 24 06:38:51 PM PDT 24 |
Jul 24 06:39:00 PM PDT 24 |
6211241420 ps |
| T883 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.891591897 |
|
|
Jul 24 06:43:13 PM PDT 24 |
Jul 24 06:44:45 PM PDT 24 |
137546628 ps |
| T884 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1779271590 |
|
|
Jul 24 06:44:38 PM PDT 24 |
Jul 24 06:44:51 PM PDT 24 |
1833816320 ps |
| T885 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3302966138 |
|
|
Jul 24 06:41:19 PM PDT 24 |
Jul 24 06:41:28 PM PDT 24 |
414623149 ps |
| T886 |
/workspace/coverage/default/2.sram_ctrl_executable.1945936405 |
|
|
Jul 24 06:37:30 PM PDT 24 |
Jul 24 07:04:43 PM PDT 24 |
26962349918 ps |
| T887 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3986374805 |
|
|
Jul 24 06:41:20 PM PDT 24 |
Jul 24 07:37:50 PM PDT 24 |
130880876169 ps |
| T888 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4185454541 |
|
|
Jul 24 06:48:05 PM PDT 24 |
Jul 24 06:50:11 PM PDT 24 |
145156941 ps |
| T889 |
/workspace/coverage/default/20.sram_ctrl_partial_access.995572720 |
|
|
Jul 24 06:42:37 PM PDT 24 |
Jul 24 06:43:17 PM PDT 24 |
146156836 ps |
| T890 |
/workspace/coverage/default/10.sram_ctrl_regwen.1594345090 |
|
|
Jul 24 06:40:00 PM PDT 24 |
Jul 24 06:43:10 PM PDT 24 |
354058146 ps |
| T891 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2903801898 |
|
|
Jul 24 06:39:02 PM PDT 24 |
Jul 24 06:39:03 PM PDT 24 |
17852660 ps |
| T892 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3019546241 |
|
|
Jul 24 06:44:04 PM PDT 24 |
Jul 24 06:48:37 PM PDT 24 |
14477436207 ps |
| T893 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3292225376 |
|
|
Jul 24 06:44:57 PM PDT 24 |
Jul 24 06:50:12 PM PDT 24 |
8390217303 ps |
| T894 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1547614739 |
|
|
Jul 24 06:46:30 PM PDT 24 |
Jul 24 06:52:25 PM PDT 24 |
65337670175 ps |
| T895 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3371711739 |
|
|
Jul 24 06:49:43 PM PDT 24 |
Jul 24 06:51:31 PM PDT 24 |
825106488 ps |
| T896 |
/workspace/coverage/default/35.sram_ctrl_executable.3925202194 |
|
|
Jul 24 06:46:52 PM PDT 24 |
Jul 24 07:09:14 PM PDT 24 |
42528350811 ps |
| T897 |
/workspace/coverage/default/1.sram_ctrl_smoke.1677962360 |
|
|
Jul 24 06:37:00 PM PDT 24 |
Jul 24 06:37:52 PM PDT 24 |
108013156 ps |
| T898 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1867500463 |
|
|
Jul 24 06:42:43 PM PDT 24 |
Jul 24 06:43:09 PM PDT 24 |
170758573 ps |
| T899 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1465188311 |
|
|
Jul 24 06:49:27 PM PDT 24 |
Jul 24 06:52:38 PM PDT 24 |
5317429205 ps |
| T900 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4253198558 |
|
|
Jul 24 06:38:43 PM PDT 24 |
Jul 24 06:43:07 PM PDT 24 |
21655287105 ps |
| T901 |
/workspace/coverage/default/44.sram_ctrl_smoke.3220095481 |
|
|
Jul 24 06:48:57 PM PDT 24 |
Jul 24 06:49:38 PM PDT 24 |
2422058895 ps |
| T902 |
/workspace/coverage/default/33.sram_ctrl_bijection.1707653555 |
|
|
Jul 24 06:46:14 PM PDT 24 |
Jul 24 06:46:45 PM PDT 24 |
1772244583 ps |
| T903 |
/workspace/coverage/default/32.sram_ctrl_stress_all.3598690076 |
|
|
Jul 24 06:46:16 PM PDT 24 |
Jul 24 07:05:29 PM PDT 24 |
2884304435 ps |
| T904 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1656003524 |
|
|
Jul 24 06:50:44 PM PDT 24 |
Jul 24 06:53:21 PM PDT 24 |
224194277 ps |
| T905 |
/workspace/coverage/default/40.sram_ctrl_regwen.72901134 |
|
|
Jul 24 06:48:12 PM PDT 24 |
Jul 24 07:07:35 PM PDT 24 |
1318652742 ps |
| T906 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1126162148 |
|
|
Jul 24 06:50:30 PM PDT 24 |
Jul 24 06:51:04 PM PDT 24 |
92229117 ps |
| T907 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.456742101 |
|
|
Jul 24 06:48:15 PM PDT 24 |
Jul 24 06:57:12 PM PDT 24 |
7627648178 ps |
| T908 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2119168902 |
|
|
Jul 24 06:46:57 PM PDT 24 |
Jul 24 06:47:04 PM PDT 24 |
681326051 ps |
| T909 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1662290573 |
|
|
Jul 24 06:49:51 PM PDT 24 |
Jul 24 06:49:52 PM PDT 24 |
148248774 ps |
| T910 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1967733023 |
|
|
Jul 24 06:44:40 PM PDT 24 |
Jul 24 06:44:53 PM PDT 24 |
135628005 ps |
| T911 |
/workspace/coverage/default/28.sram_ctrl_stress_all.787778268 |
|
|
Jul 24 06:45:05 PM PDT 24 |
Jul 24 07:35:12 PM PDT 24 |
42566944968 ps |
| T912 |
/workspace/coverage/default/33.sram_ctrl_smoke.3383476785 |
|
|
Jul 24 06:46:16 PM PDT 24 |
Jul 24 06:46:18 PM PDT 24 |
175694581 ps |
| T913 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3018270720 |
|
|
Jul 24 06:50:12 PM PDT 24 |
Jul 24 06:51:59 PM PDT 24 |
1205342786 ps |
| T914 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.89139288 |
|
|
Jul 24 06:46:36 PM PDT 24 |
Jul 24 06:46:37 PM PDT 24 |
319133810 ps |
| T915 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1482926954 |
|
|
Jul 24 06:44:36 PM PDT 24 |
Jul 24 06:46:59 PM PDT 24 |
581842993 ps |
| T916 |
/workspace/coverage/default/8.sram_ctrl_executable.3786278965 |
|
|
Jul 24 06:39:35 PM PDT 24 |
Jul 24 06:43:33 PM PDT 24 |
19412694522 ps |
| T917 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1918405712 |
|
|
Jul 24 06:42:43 PM PDT 24 |
Jul 24 06:42:50 PM PDT 24 |
58819711 ps |
| T918 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3300382108 |
|
|
Jul 24 06:42:30 PM PDT 24 |
Jul 24 06:42:30 PM PDT 24 |
24296866 ps |
| T919 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3806441820 |
|
|
Jul 24 06:48:40 PM PDT 24 |
Jul 24 06:48:43 PM PDT 24 |
87793230 ps |
| T920 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3401931432 |
|
|
Jul 24 06:43:29 PM PDT 24 |
Jul 24 06:45:15 PM PDT 24 |
290315071 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2043769284 |
|
|
Jul 24 06:37:07 PM PDT 24 |
Jul 24 06:37:42 PM PDT 24 |
331097388 ps |
| T922 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1781487336 |
|
|
Jul 24 06:48:51 PM PDT 24 |
Jul 24 06:48:54 PM PDT 24 |
546166693 ps |
| T923 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.721981062 |
|
|
Jul 24 06:47:57 PM PDT 24 |
Jul 24 06:59:29 PM PDT 24 |
9569360237 ps |
| T924 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.651244952 |
|
|
Jul 24 06:45:03 PM PDT 24 |
Jul 24 06:45:10 PM PDT 24 |
348479707 ps |
| T925 |
/workspace/coverage/default/35.sram_ctrl_bijection.3388858459 |
|
|
Jul 24 06:46:45 PM PDT 24 |
Jul 24 06:47:10 PM PDT 24 |
2670635619 ps |
| T926 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.44965249 |
|
|
Jul 24 06:49:03 PM PDT 24 |
Jul 24 06:49:07 PM PDT 24 |
2176725502 ps |
| T927 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2098143350 |
|
|
Jul 24 06:42:21 PM PDT 24 |
Jul 24 07:19:41 PM PDT 24 |
68479464748 ps |
| T928 |
/workspace/coverage/default/34.sram_ctrl_regwen.60878670 |
|
|
Jul 24 06:46:37 PM PDT 24 |
Jul 24 06:52:26 PM PDT 24 |
1017184454 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4193590205 |
|
|
Jul 24 06:47:52 PM PDT 24 |
Jul 24 06:50:06 PM PDT 24 |
376749453 ps |
| T930 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.946770261 |
|
|
Jul 24 06:40:53 PM PDT 24 |
Jul 24 06:41:55 PM PDT 24 |
117808424 ps |
| T931 |
/workspace/coverage/default/48.sram_ctrl_executable.269665556 |
|
|
Jul 24 06:50:45 PM PDT 24 |
Jul 24 07:04:45 PM PDT 24 |
48486262641 ps |
| T932 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.4130334687 |
|
|
Jul 24 06:49:32 PM PDT 24 |
Jul 24 06:49:34 PM PDT 24 |
43893219 ps |
| T933 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1965728273 |
|
|
Jul 24 06:45:53 PM PDT 24 |
Jul 24 07:06:10 PM PDT 24 |
4920441915 ps |
| T934 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.918380372 |
|
|
Jul 24 06:50:46 PM PDT 24 |
Jul 24 07:05:02 PM PDT 24 |
3454503388 ps |
| T935 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2501177561 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:55 PM PDT 24 |
311591390 ps |
| T54 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1130415508 |
|
|
Jul 24 07:17:55 PM PDT 24 |
Jul 24 07:17:57 PM PDT 24 |
151519266 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1268405669 |
|
|
Jul 24 07:16:47 PM PDT 24 |
Jul 24 07:16:50 PM PDT 24 |
795871428 ps |
| T61 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3760305415 |
|
|
Jul 24 07:18:00 PM PDT 24 |
Jul 24 07:18:01 PM PDT 24 |
106799919 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3657980093 |
|
|
Jul 24 07:16:56 PM PDT 24 |
Jul 24 07:16:57 PM PDT 24 |
19168810 ps |
| T936 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3933812906 |
|
|
Jul 24 07:17:46 PM PDT 24 |
Jul 24 07:17:47 PM PDT 24 |
218436608 ps |
| T937 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.525188443 |
|
|
Jul 24 07:17:35 PM PDT 24 |
Jul 24 07:17:38 PM PDT 24 |
40080594 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2475454784 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:54 PM PDT 24 |
394065981 ps |
| T938 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2701787125 |
|
|
Jul 24 07:17:55 PM PDT 24 |
Jul 24 07:17:58 PM PDT 24 |
187755025 ps |
| T939 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.69928380 |
|
|
Jul 24 07:17:35 PM PDT 24 |
Jul 24 07:17:38 PM PDT 24 |
78851411 ps |
| T55 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1458288864 |
|
|
Jul 24 07:17:10 PM PDT 24 |
Jul 24 07:17:12 PM PDT 24 |
564340926 ps |
| T940 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3303005549 |
|
|
Jul 24 07:17:45 PM PDT 24 |
Jul 24 07:17:48 PM PDT 24 |
78528592 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1444958547 |
|
|
Jul 24 07:17:14 PM PDT 24 |
Jul 24 07:17:15 PM PDT 24 |
18995034 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2221841738 |
|
|
Jul 24 07:16:50 PM PDT 24 |
Jul 24 07:16:54 PM PDT 24 |
1647875453 ps |
| T93 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4077480066 |
|
|
Jul 24 07:17:23 PM PDT 24 |
Jul 24 07:17:23 PM PDT 24 |
14287204 ps |
| T66 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.673399618 |
|
|
Jul 24 07:16:56 PM PDT 24 |
Jul 24 07:16:57 PM PDT 24 |
45757445 ps |
| T941 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1839767252 |
|
|
Jul 24 07:17:56 PM PDT 24 |
Jul 24 07:17:57 PM PDT 24 |
30390815 ps |
| T67 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1847846850 |
|
|
Jul 24 07:17:22 PM PDT 24 |
Jul 24 07:17:25 PM PDT 24 |
429555734 ps |
| T942 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1233515743 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:18:02 PM PDT 24 |
33110428 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2040294181 |
|
|
Jul 24 07:17:28 PM PDT 24 |
Jul 24 07:17:29 PM PDT 24 |
80258083 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.217461826 |
|
|
Jul 24 07:17:34 PM PDT 24 |
Jul 24 07:17:38 PM PDT 24 |
135897380 ps |
| T69 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2231038713 |
|
|
Jul 24 07:17:38 PM PDT 24 |
Jul 24 07:17:39 PM PDT 24 |
33319878 ps |
| T56 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1629564509 |
|
|
Jul 24 07:17:58 PM PDT 24 |
Jul 24 07:18:00 PM PDT 24 |
837452655 ps |
| T944 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.881164715 |
|
|
Jul 24 07:17:42 PM PDT 24 |
Jul 24 07:17:44 PM PDT 24 |
25698418 ps |
| T945 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1076061692 |
|
|
Jul 24 07:17:41 PM PDT 24 |
Jul 24 07:17:43 PM PDT 24 |
101446996 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.558693366 |
|
|
Jul 24 07:17:11 PM PDT 24 |
Jul 24 07:17:14 PM PDT 24 |
129640570 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.480054754 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:51 PM PDT 24 |
15829876 ps |
| T94 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3667479240 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:17:59 PM PDT 24 |
15711233 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3430431416 |
|
|
Jul 24 07:17:09 PM PDT 24 |
Jul 24 07:17:11 PM PDT 24 |
394358331 ps |
| T948 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1801100895 |
|
|
Jul 24 07:17:35 PM PDT 24 |
Jul 24 07:17:35 PM PDT 24 |
20965274 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1812780747 |
|
|
Jul 24 07:17:42 PM PDT 24 |
Jul 24 07:17:43 PM PDT 24 |
34998748 ps |
| T950 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2278902397 |
|
|
Jul 24 07:17:57 PM PDT 24 |
Jul 24 07:17:58 PM PDT 24 |
122773163 ps |
| T71 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3653642344 |
|
|
Jul 24 07:17:44 PM PDT 24 |
Jul 24 07:17:48 PM PDT 24 |
1531482561 ps |
| T124 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1128206288 |
|
|
Jul 24 07:16:59 PM PDT 24 |
Jul 24 07:17:00 PM PDT 24 |
114713644 ps |
| T72 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2050533095 |
|
|
Jul 24 07:17:28 PM PDT 24 |
Jul 24 07:17:30 PM PDT 24 |
1805817096 ps |
| T951 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1044162850 |
|
|
Jul 24 07:17:56 PM PDT 24 |
Jul 24 07:17:58 PM PDT 24 |
36090489 ps |
| T952 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2917212288 |
|
|
Jul 24 07:17:56 PM PDT 24 |
Jul 24 07:17:58 PM PDT 24 |
46383726 ps |
| T121 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2828978890 |
|
|
Jul 24 07:16:54 PM PDT 24 |
Jul 24 07:16:56 PM PDT 24 |
341233651 ps |
| T953 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.227967735 |
|
|
Jul 24 07:17:24 PM PDT 24 |
Jul 24 07:17:27 PM PDT 24 |
33286792 ps |
| T125 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.937752553 |
|
|
Jul 24 07:17:45 PM PDT 24 |
Jul 24 07:17:46 PM PDT 24 |
1149080825 ps |
| T128 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3452072007 |
|
|
Jul 24 07:17:23 PM PDT 24 |
Jul 24 07:17:25 PM PDT 24 |
256391960 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.332647282 |
|
|
Jul 24 07:17:29 PM PDT 24 |
Jul 24 07:17:30 PM PDT 24 |
31531206 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1788517565 |
|
|
Jul 24 07:17:36 PM PDT 24 |
Jul 24 07:17:37 PM PDT 24 |
744308700 ps |
| T955 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4060194161 |
|
|
Jul 24 07:17:02 PM PDT 24 |
Jul 24 07:17:03 PM PDT 24 |
28449873 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.689823727 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:18:01 PM PDT 24 |
35508262 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3229182127 |
|
|
Jul 24 07:17:09 PM PDT 24 |
Jul 24 07:17:11 PM PDT 24 |
194210400 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.41119395 |
|
|
Jul 24 07:17:45 PM PDT 24 |
Jul 24 07:17:47 PM PDT 24 |
111430605 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3121034874 |
|
|
Jul 24 07:17:34 PM PDT 24 |
Jul 24 07:17:38 PM PDT 24 |
8011685885 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3016176318 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:18:02 PM PDT 24 |
272725874 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.442175663 |
|
|
Jul 24 07:17:23 PM PDT 24 |
Jul 24 07:17:28 PM PDT 24 |
129452055 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2064647713 |
|
|
Jul 24 07:17:17 PM PDT 24 |
Jul 24 07:17:19 PM PDT 24 |
46603422 ps |
| T133 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2016798267 |
|
|
Jul 24 07:17:39 PM PDT 24 |
Jul 24 07:17:40 PM PDT 24 |
123116222 ps |
| T962 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3788246816 |
|
|
Jul 24 07:18:00 PM PDT 24 |
Jul 24 07:18:00 PM PDT 24 |
35616791 ps |
| T963 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2916012743 |
|
|
Jul 24 07:17:45 PM PDT 24 |
Jul 24 07:17:46 PM PDT 24 |
62774386 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1893096862 |
|
|
Jul 24 07:17:23 PM PDT 24 |
Jul 24 07:17:25 PM PDT 24 |
233770662 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3779493355 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:52 PM PDT 24 |
58782457 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1038726605 |
|
|
Jul 24 07:17:46 PM PDT 24 |
Jul 24 07:17:48 PM PDT 24 |
260609653 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2285180866 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:18:00 PM PDT 24 |
61386422 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1319017855 |
|
|
Jul 24 07:17:09 PM PDT 24 |
Jul 24 07:17:14 PM PDT 24 |
571894578 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2410262316 |
|
|
Jul 24 07:17:36 PM PDT 24 |
Jul 24 07:17:37 PM PDT 24 |
15647259 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3794550497 |
|
|
Jul 24 07:17:40 PM PDT 24 |
Jul 24 07:17:41 PM PDT 24 |
22299779 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1627056703 |
|
|
Jul 24 07:17:04 PM PDT 24 |
Jul 24 07:17:06 PM PDT 24 |
1215590373 ps |
| T130 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.48188371 |
|
|
Jul 24 07:17:37 PM PDT 24 |
Jul 24 07:17:39 PM PDT 24 |
824240339 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2548016700 |
|
|
Jul 24 07:17:35 PM PDT 24 |
Jul 24 07:17:36 PM PDT 24 |
38598761 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2628293211 |
|
|
Jul 24 07:17:28 PM PDT 24 |
Jul 24 07:17:29 PM PDT 24 |
17678817 ps |
| T973 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3383424817 |
|
|
Jul 24 07:17:42 PM PDT 24 |
Jul 24 07:17:42 PM PDT 24 |
41685768 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3332365402 |
|
|
Jul 24 07:17:50 PM PDT 24 |
Jul 24 07:17:51 PM PDT 24 |
38991934 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.873516110 |
|
|
Jul 24 07:16:52 PM PDT 24 |
Jul 24 07:16:53 PM PDT 24 |
23623346 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1915369780 |
|
|
Jul 24 07:17:03 PM PDT 24 |
Jul 24 07:17:06 PM PDT 24 |
43278541 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4195569530 |
|
|
Jul 24 07:17:34 PM PDT 24 |
Jul 24 07:17:35 PM PDT 24 |
51530533 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1168052936 |
|
|
Jul 24 07:17:42 PM PDT 24 |
Jul 24 07:17:43 PM PDT 24 |
15146117 ps |
| T131 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2802561087 |
|
|
Jul 24 07:17:56 PM PDT 24 |
Jul 24 07:17:58 PM PDT 24 |
182527428 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2024456841 |
|
|
Jul 24 07:17:50 PM PDT 24 |
Jul 24 07:17:52 PM PDT 24 |
204552034 ps |
| T979 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4009001130 |
|
|
Jul 24 07:17:57 PM PDT 24 |
Jul 24 07:17:58 PM PDT 24 |
24115184 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2840360796 |
|
|
Jul 24 07:17:09 PM PDT 24 |
Jul 24 07:17:10 PM PDT 24 |
29709801 ps |
| T980 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3735090496 |
|
|
Jul 24 07:17:29 PM PDT 24 |
Jul 24 07:17:29 PM PDT 24 |
22444224 ps |
| T123 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4273731774 |
|
|
Jul 24 07:17:35 PM PDT 24 |
Jul 24 07:17:38 PM PDT 24 |
225998878 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1704335716 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:18:04 PM PDT 24 |
220717765 ps |
| T982 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.594255474 |
|
|
Jul 24 07:17:23 PM PDT 24 |
Jul 24 07:17:23 PM PDT 24 |
12981096 ps |
| T983 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1956031948 |
|
|
Jul 24 07:17:44 PM PDT 24 |
Jul 24 07:17:46 PM PDT 24 |
36643292 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1187026231 |
|
|
Jul 24 07:16:58 PM PDT 24 |
Jul 24 07:17:01 PM PDT 24 |
306318200 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1579986495 |
|
|
Jul 24 07:17:02 PM PDT 24 |
Jul 24 07:17:03 PM PDT 24 |
25054353 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1643372174 |
|
|
Jul 24 07:17:41 PM PDT 24 |
Jul 24 07:17:42 PM PDT 24 |
13066642 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1119847103 |
|
|
Jul 24 07:17:56 PM PDT 24 |
Jul 24 07:17:59 PM PDT 24 |
825749779 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.971186483 |
|
|
Jul 24 07:16:57 PM PDT 24 |
Jul 24 07:17:00 PM PDT 24 |
602428193 ps |
| T129 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2178480046 |
|
|
Jul 24 07:17:49 PM PDT 24 |
Jul 24 07:17:51 PM PDT 24 |
137477940 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3404978339 |
|
|
Jul 24 07:16:50 PM PDT 24 |
Jul 24 07:16:51 PM PDT 24 |
30273060 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1429190336 |
|
|
Jul 24 07:17:34 PM PDT 24 |
Jul 24 07:17:37 PM PDT 24 |
2209643094 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3249596139 |
|
|
Jul 24 07:17:04 PM PDT 24 |
Jul 24 07:17:06 PM PDT 24 |
184682371 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3130823356 |
|
|
Jul 24 07:17:09 PM PDT 24 |
Jul 24 07:17:10 PM PDT 24 |
15186632 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3410466238 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:52 PM PDT 24 |
171818685 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4119693609 |
|
|
Jul 24 07:17:16 PM PDT 24 |
Jul 24 07:17:16 PM PDT 24 |
34850273 ps |
| T992 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.934897807 |
|
|
Jul 24 07:16:55 PM PDT 24 |
Jul 24 07:16:55 PM PDT 24 |
15223636 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2906466695 |
|
|
Jul 24 07:17:16 PM PDT 24 |
Jul 24 07:17:17 PM PDT 24 |
22904335 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1093689750 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:18:02 PM PDT 24 |
466468633 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1538858322 |
|
|
Jul 24 07:16:58 PM PDT 24 |
Jul 24 07:16:59 PM PDT 24 |
22586449 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1363228495 |
|
|
Jul 24 07:17:28 PM PDT 24 |
Jul 24 07:17:31 PM PDT 24 |
95269474 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3833596488 |
|
|
Jul 24 07:17:28 PM PDT 24 |
Jul 24 07:17:32 PM PDT 24 |
356443116 ps |
| T90 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2921433258 |
|
|
Jul 24 07:17:42 PM PDT 24 |
Jul 24 07:17:45 PM PDT 24 |
401709097 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.279273878 |
|
|
Jul 24 07:17:25 PM PDT 24 |
Jul 24 07:17:26 PM PDT 24 |
117942273 ps |
| T86 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4269508322 |
|
|
Jul 24 07:17:56 PM PDT 24 |
Jul 24 07:17:57 PM PDT 24 |
55483665 ps |
| T87 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.950059782 |
|
|
Jul 24 07:17:28 PM PDT 24 |
Jul 24 07:17:32 PM PDT 24 |
3512727496 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1043188003 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:52 PM PDT 24 |
109780005 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1785248842 |
|
|
Jul 24 07:17:22 PM PDT 24 |
Jul 24 07:17:25 PM PDT 24 |
904983464 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3712342488 |
|
|
Jul 24 07:18:00 PM PDT 24 |
Jul 24 07:18:02 PM PDT 24 |
763691931 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3145867098 |
|
|
Jul 24 07:16:51 PM PDT 24 |
Jul 24 07:16:52 PM PDT 24 |
16928371 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1255550847 |
|
|
Jul 24 07:17:58 PM PDT 24 |
Jul 24 07:17:59 PM PDT 24 |
20511679 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2740223252 |
|
|
Jul 24 07:17:09 PM PDT 24 |
Jul 24 07:17:10 PM PDT 24 |
33799930 ps |