Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14541712	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62320469

1

T1

1099

T2

7114

T3

23124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38320795	1			T1	614		T2	3994		T3	12777
values[0x0]	17804975	1			T1	291		T2	1827		T3	6211
values[0x1]	20736411	1			T1	327		T2	2008		T3	6521

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7245564	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

69616617

1

T1

1164

T2

7482

T3

24305

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	349382	1			T1	3		T2	21		T3	102
valid_sources[0x01]	286956	1			T1	8		T2	31		T3	93
valid_sources[0x02]	302697	1			T1	9		T2	32		T3	104
valid_sources[0x03]	271954	1			T1	5		T2	20		T3	102
valid_sources[0x04]	305258	1			T1	1		T2	41		T3	90
valid_sources[0x05]	275768	1			T1	3		T2	17		T3	100
valid_sources[0x06]	269557	1			T1	4		T2	29		T3	101
valid_sources[0x07]	274635	1			T1	5		T2	32		T3	93
valid_sources[0x08]	313993	1			T1	4		T2	31		T3	96
valid_sources[0x09]	278252	1			T1	4		T2	45		T3	96
valid_sources[0x0a]	314394	1			T1	4		T2	45		T3	111
valid_sources[0x0b]	293007	1			T1	2		T2	29		T3	92
valid_sources[0x0c]	268433	1			T2	34		T3	114		T8	356
valid_sources[0x0d]	312296	1			T1	13		T2	45		T3	97
valid_sources[0x0e]	278825	1			T1	8		T2	29		T3	97
valid_sources[0x0f]	330653	1			T1	4		T2	31		T3	90
valid_sources[0x10]	328142	1			T1	1		T2	23		T3	92
valid_sources[0x11]	269306	1			T2	33		T3	92		T8	364
valid_sources[0x12]	311012	1			T1	2		T2	28		T3	93
valid_sources[0x13]	286961	1			T1	7		T2	32		T3	99
valid_sources[0x14]	296737	1			T1	3		T2	34		T3	95
valid_sources[0x15]	281013	1			T1	2		T2	20		T3	106
valid_sources[0x16]	309712	1			T1	1		T2	32		T3	105
valid_sources[0x17]	294896	1			T1	1		T2	25		T3	73
valid_sources[0x18]	310694	1			T1	5		T2	38		T3	107
valid_sources[0x19]	280418	1			T1	7		T2	26		T3	110
valid_sources[0x1a]	273218	1			T1	3		T2	35		T3	94
valid_sources[0x1b]	289366	1			T1	12		T2	42		T3	102
valid_sources[0x1c]	280682	1			T1	7		T2	27		T3	119
valid_sources[0x1d]	363198	1			T1	7		T2	26		T3	109
valid_sources[0x1e]	321024	1			T1	2		T2	40		T3	98
valid_sources[0x1f]	277145	1			T1	2		T2	26		T3	97
valid_sources[0x20]	299896	1			T2	37		T3	83		T8	382
valid_sources[0x21]	277917	1			T1	2		T2	39		T3	96
valid_sources[0x22]	301286	1			T1	2		T2	26		T3	107
valid_sources[0x23]	356530	1			T1	5		T2	43		T3	99
valid_sources[0x24]	289611	1			T1	3		T2	39		T3	99
valid_sources[0x25]	279667	1			T1	2		T2	32		T3	93
valid_sources[0x26]	269827	1			T2	18		T3	102		T8	403
valid_sources[0x27]	291239	1			T1	1		T2	29		T3	96
valid_sources[0x28]	278801	1			T2	38		T3	107		T8	352
valid_sources[0x29]	274661	1			T2	25		T3	97		T8	390
valid_sources[0x2a]	286351	1			T1	7		T2	29		T3	101
valid_sources[0x2b]	298312	1			T1	3		T2	22		T3	98
valid_sources[0x2c]	298226	1			T1	3		T2	24		T3	94
valid_sources[0x2d]	317860	1			T1	2		T2	21		T3	115
valid_sources[0x2e]	278284	1			T1	6		T2	39		T3	88
valid_sources[0x2f]	327640	1			T1	2		T2	21		T3	97
valid_sources[0x30]	313606	1			T1	7		T2	41		T3	81
valid_sources[0x31]	284617	1			T1	1		T2	15		T3	114
valid_sources[0x32]	296933	1			T2	33		T3	91		T8	408
valid_sources[0x33]	276553	1			T1	3		T2	42		T3	87
valid_sources[0x34]	274650	1			T1	10		T2	34		T3	129
valid_sources[0x35]	290995	1			T1	7		T2	38		T3	108
valid_sources[0x36]	336428	1			T1	2		T2	26		T3	95
valid_sources[0x37]	279148	1			T1	2		T2	19		T3	88
valid_sources[0x38]	300704	1			T1	10		T2	17		T3	107
valid_sources[0x39]	313494	1			T1	5		T2	27		T3	100
valid_sources[0x3a]	287599	1			T1	9		T2	42		T3	116
valid_sources[0x3b]	277716	1			T2	26		T3	95		T8	383
valid_sources[0x3c]	265077	1			T1	2		T2	30		T3	85
valid_sources[0x3d]	301682	1			T1	8		T2	34		T3	101
valid_sources[0x3e]	293406	1			T1	1		T2	43		T3	109
valid_sources[0x3f]	295669	1			T1	9		T2	38		T3	100
valid_sources[0x40]	283795	1			T1	1		T2	18		T3	97
valid_sources[0x41]	266117	1			T1	5		T2	32		T3	93
valid_sources[0x42]	278071	1			T1	9		T2	45		T3	102
valid_sources[0x43]	306572	1			T1	2		T2	25		T3	83
valid_sources[0x44]	336669	1			T1	9		T2	30		T3	104
valid_sources[0x45]	270922	1			T1	2		T2	31		T3	98
valid_sources[0x46]	301261	1			T2	24		T3	107		T7	10
valid_sources[0x47]	293974	1			T2	36		T3	100		T8	397
valid_sources[0x48]	271712	1			T1	7		T2	36		T3	106
valid_sources[0x49]	305708	1			T1	9		T2	14		T3	101
valid_sources[0x4a]	315167	1			T1	9		T2	41		T3	116
valid_sources[0x4b]	275249	1			T1	9		T2	23		T3	104
valid_sources[0x4c]	322713	1			T1	7		T2	33		T3	111
valid_sources[0x4d]	295095	1			T1	7		T2	27		T3	107
valid_sources[0x4e]	296064	1			T1	2		T2	27		T3	106
valid_sources[0x4f]	268219	1			T1	6		T2	26		T3	111
valid_sources[0x50]	276821	1			T1	3		T2	28		T3	109
valid_sources[0x51]	306794	1			T1	10		T2	38		T3	110
valid_sources[0x52]	285145	1			T2	31		T3	105		T8	369
valid_sources[0x53]	294007	1			T1	2		T2	35		T3	89
valid_sources[0x54]	308222	1			T1	5		T2	22		T3	90
valid_sources[0x55]	326673	1			T1	6		T2	17		T3	106
valid_sources[0x56]	295229	1			T1	7		T2	31		T3	80
valid_sources[0x57]	418716	1			T2	40		T3	118		T8	383
valid_sources[0x58]	274167	1			T2	17		T3	85		T8	394
valid_sources[0x59]	269338	1			T2	18		T3	102		T8	427
valid_sources[0x5a]	283937	1			T1	1		T2	31		T3	103
valid_sources[0x5b]	278291	1			T2	19		T3	107		T8	385
valid_sources[0x5c]	305984	1			T2	42		T3	102		T8	426
valid_sources[0x5d]	265627	1			T1	1		T2	34		T3	102
valid_sources[0x5e]	318478	1			T2	31		T3	97		T8	429
valid_sources[0x5f]	275055	1			T1	1		T2	28		T3	97
valid_sources[0x60]	368057	1			T1	5		T2	34		T3	97
valid_sources[0x61]	291827	1			T1	7		T2	25		T3	96
valid_sources[0x62]	275724	1			T1	4		T2	43		T3	94
valid_sources[0x63]	286771	1			T1	9		T2	22		T3	115
valid_sources[0x64]	336709	1			T1	4		T2	38		T3	120
valid_sources[0x65]	291698	1			T1	3		T2	39		T3	97
valid_sources[0x66]	338557	1			T1	2		T2	27		T3	94
valid_sources[0x67]	288243	1			T2	28		T3	112		T8	370
valid_sources[0x68]	294668	1			T1	11		T2	20		T3	116
valid_sources[0x69]	286084	1			T1	2		T2	35		T3	94
valid_sources[0x6a]	316393	1			T2	29		T3	105		T8	394
valid_sources[0x6b]	285699	1			T1	4		T2	30		T3	110
valid_sources[0x6c]	419218	1			T1	4		T2	29		T3	105
valid_sources[0x6d]	309826	1			T1	3		T2	32		T3	94
valid_sources[0x6e]	282697	1			T2	33		T3	135		T8	372
valid_sources[0x6f]	273564	1			T1	5		T2	28		T3	99
valid_sources[0x70]	319467	1			T1	14		T2	35		T3	91
valid_sources[0x71]	276074	1			T1	18		T2	33		T3	110
valid_sources[0x72]	351019	1			T1	5		T2	43		T3	88
valid_sources[0x73]	290243	1			T1	9		T2	43		T3	95
valid_sources[0x74]	312018	1			T1	20		T2	31		T3	85
valid_sources[0x75]	281294	1			T1	2		T2	29		T3	107
valid_sources[0x76]	284010	1			T1	2		T2	29		T3	106
valid_sources[0x77]	276115	1			T1	9		T2	26		T3	76
valid_sources[0x78]	294899	1			T1	12		T2	32		T3	111
valid_sources[0x79]	287846	1			T1	20		T2	36		T3	97
valid_sources[0x7a]	298804	1			T1	3		T2	40		T3	109
valid_sources[0x7b]	388955	1			T1	13		T2	24		T3	95
valid_sources[0x7c]	317472	1			T2	27		T3	118		T8	376
valid_sources[0x7d]	271390	1			T1	1		T2	23		T3	96
valid_sources[0x7e]	357793	1			T1	10		T2	28		T3	101
valid_sources[0x7f]	274499	1			T2	30		T3	94		T8	340
valid_sources[0x80]	294391	1			T1	6		T2	17		T3	108

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31054834

1

T1

548

T2

3627

T3

11586

values[0x0]

all_enables

biggest_size

15623548

1

T1

268

T2

1723

T3

5833

values[0x1]

all_enables

biggest_size

15642087

1

T1

283

T2

1764

T3

5705

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

135695

1

T1

1

T2

1

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49605	1			T3	4		T7	2		T8	1322
values[0x0]	59184	1			T2	1		T3	11		T7	2
values[0x1]	63706	1			T1	2		T2	1		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27716	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144779

1

T1

1

T2

1

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	522	1			T8	2		T18	1		T64	1
valid_sources[0x01]	744	1			T142	1		T18	10		T21	21
valid_sources[0x02]	595	1			T11	1		T64	1		T20	1
valid_sources[0x03]	821	1			T8	5		T18	73		T143	2
valid_sources[0x04]	537	1			T13	1		T18	12		T21	2
valid_sources[0x05]	543	1			T144	5		T21	6		T65	3
valid_sources[0x06]	682	1			T8	1		T18	21		T19	1
valid_sources[0x07]	570	1			T11	2		T142	1		T18	3
valid_sources[0x08]	632	1			T8	1		T11	3		T18	20
valid_sources[0x09]	534	1			T7	1		T8	4		T19	1
valid_sources[0x0a]	470	1			T11	1		T21	7		T47	7
valid_sources[0x0b]	578	1			T18	1		T64	1		T145	1
valid_sources[0x0c]	498	1			T8	2		T11	2		T64	1
valid_sources[0x0d]	811	1			T8	1		T80	1		T18	59
valid_sources[0x0e]	859	1			T18	70		T21	4		T146	4
valid_sources[0x0f]	662	1			T8	79		T18	46		T19	2
valid_sources[0x10]	546	1			T8	4		T9	3		T18	4
valid_sources[0x11]	932	1			T8	62		T51	1		T64	1
valid_sources[0x12]	696	1			T10	1		T18	41		T147	1
valid_sources[0x13]	460	1			T8	1		T18	1		T64	1
valid_sources[0x14]	825	1			T18	37		T20	4		T148	4
valid_sources[0x15]	1074	1			T3	21		T8	315		T142	1
valid_sources[0x16]	874	1			T8	130		T149	1		T18	2
valid_sources[0x17]	695	1			T8	1		T18	11		T21	7
valid_sources[0x18]	593	1			T11	4		T19	1		T21	13
valid_sources[0x19]	684	1			T8	114		T10	1		T18	13
valid_sources[0x1a]	588	1			T18	2		T150	1		T120	5
valid_sources[0x1b]	741	1			T8	111		T10	2		T18	3
valid_sources[0x1c]	596	1			T11	2		T18	6		T14	2
valid_sources[0x1d]	948	1			T8	146		T80	1		T18	15
valid_sources[0x1e]	579	1			T8	3		T18	1		T19	1
valid_sources[0x1f]	670	1			T64	1		T20	1		T21	25
valid_sources[0x20]	653	1			T39	1		T135	5		T20	5
valid_sources[0x21]	584	1			T8	1		T18	22		T20	2
valid_sources[0x22]	755	1			T8	16		T18	23		T19	3
valid_sources[0x23]	608	1			T8	87		T142	1		T18	5
valid_sources[0x24]	626	1			T8	4		T80	3		T60	24
valid_sources[0x25]	626	1			T8	1		T18	16		T5	1
valid_sources[0x26]	995	1			T8	2		T36	47		T18	16
valid_sources[0x27]	687	1			T10	1		T80	1		T142	1
valid_sources[0x28]	632	1			T11	2		T142	1		T18	20
valid_sources[0x29]	493	1			T64	1		T20	4		T21	4
valid_sources[0x2a]	704	1			T52	120		T61	5		T64	1
valid_sources[0x2b]	641	1			T8	2		T80	1		T20	7
valid_sources[0x2c]	880	1			T18	6		T64	1		T5	3
valid_sources[0x2d]	585	1			T8	1		T18	9		T5	1
valid_sources[0x2e]	633	1			T8	3		T18	6		T19	1
valid_sources[0x2f]	810	1			T8	4		T59	6		T18	29
valid_sources[0x30]	552	1			T8	2		T18	12		T151	4
valid_sources[0x31]	776	1			T147	1		T20	4		T21	8
valid_sources[0x32]	585	1			T11	4		T80	1		T141	2
valid_sources[0x33]	770	1			T8	123		T118	1		T21	26
valid_sources[0x34]	679	1			T8	1		T11	1		T18	1
valid_sources[0x35]	626	1			T8	1		T18	18		T5	9
valid_sources[0x36]	575	1			T20	3		T21	4		T45	1
valid_sources[0x37]	536	1			T13	3		T18	1		T64	1
valid_sources[0x38]	630	1			T8	6		T10	1		T18	1
valid_sources[0x39]	687	1			T9	5		T18	19		T19	1
valid_sources[0x3a]	739	1			T8	47		T11	1		T21	1
valid_sources[0x3b]	546	1			T8	2		T18	18		T21	1
valid_sources[0x3c]	676	1			T18	18		T20	2		T21	1
valid_sources[0x3d]	595	1			T8	48		T11	3		T18	23
valid_sources[0x3e]	559	1			T20	6		T21	1		T152	1
valid_sources[0x3f]	535	1			T11	1		T18	52		T21	10
valid_sources[0x40]	795	1			T8	157		T142	1		T118	3
valid_sources[0x41]	887	1			T8	1		T18	1		T64	1
valid_sources[0x42]	611	1			T8	2		T18	9		T64	1
valid_sources[0x43]	646	1			T8	1		T64	2		T21	2
valid_sources[0x44]	514	1			T8	2		T11	5		T64	1
valid_sources[0x45]	647	1			T8	86		T18	13		T153	1
valid_sources[0x46]	686	1			T142	1		T85	2		T18	1
valid_sources[0x47]	529	1			T18	15		T64	1		T20	2
valid_sources[0x48]	689	1			T8	126		T104	1		T18	35
valid_sources[0x49]	885	1			T8	2		T18	56		T64	1
valid_sources[0x4a]	621	1			T2	1		T19	1		T20	4
valid_sources[0x4b]	597	1			T8	1		T5	6		T14	1
valid_sources[0x4c]	580	1			T8	4		T149	1		T19	1
valid_sources[0x4d]	792	1			T8	1		T10	1		T80	1
valid_sources[0x4e]	485	1			T11	1		T18	1		T20	4
valid_sources[0x4f]	752	1			T8	177		T11	1		T18	19
valid_sources[0x50]	887	1			T8	3		T11	9		T80	1
valid_sources[0x51]	795	1			T37	1		T18	1		T118	1
valid_sources[0x52]	518	1			T8	50		T11	1		T48	1
valid_sources[0x53]	601	1			T98	15		T18	4		T64	1
valid_sources[0x54]	587	1			T8	1		T142	1		T18	4
valid_sources[0x55]	663	1			T18	11		T64	1		T19	1
valid_sources[0x56]	740	1			T8	1		T142	1		T19	1
valid_sources[0x57]	540	1			T8	2		T64	1		T5	2
valid_sources[0x58]	789	1			T10	1		T98	6		T18	2
valid_sources[0x59]	630	1			T8	110		T18	1		T20	2
valid_sources[0x5a]	735	1			T10	1		T18	14		T118	1
valid_sources[0x5b]	775	1			T11	1		T142	1		T18	6
valid_sources[0x5c]	666	1			T18	24		T64	2		T19	1
valid_sources[0x5d]	780	1			T8	1		T18	1		T20	1
valid_sources[0x5e]	696	1			T8	2		T18	1		T19	1
valid_sources[0x5f]	508	1			T8	3		T80	1		T18	37
valid_sources[0x60]	623	1			T142	1		T18	53		T19	1
valid_sources[0x61]	635	1			T8	95		T18	3		T64	1
valid_sources[0x62]	667	1			T8	8		T18	15		T64	1
valid_sources[0x63]	716	1			T8	1		T18	11		T20	1
valid_sources[0x64]	567	1			T8	2		T142	1		T18	2
valid_sources[0x65]	537	1			T8	3		T18	2		T19	1
valid_sources[0x66]	819	1			T8	143		T18	5		T19	2
valid_sources[0x67]	539	1			T8	3		T11	1		T142	1
valid_sources[0x68]	475	1			T8	1		T80	1		T142	1
valid_sources[0x69]	610	1			T8	1		T18	20		T64	1
valid_sources[0x6a]	590	1			T11	5		T18	32		T64	1
valid_sources[0x6b]	845	1			T8	133		T80	1		T104	1
valid_sources[0x6c]	772	1			T104	1		T18	112		T21	23
valid_sources[0x6d]	735	1			T8	25		T18	15		T64	5
valid_sources[0x6e]	801	1			T10	1		T142	1		T18	1
valid_sources[0x6f]	669	1			T8	3		T154	2		T18	8
valid_sources[0x70]	612	1			T8	29		T18	34		T19	1
valid_sources[0x71]	845	1			T8	5		T142	1		T18	38
valid_sources[0x72]	678	1			T61	1		T142	1		T18	2
valid_sources[0x73]	513	1			T8	1		T18	1		T48	2
valid_sources[0x74]	518	1			T104	1		T64	1		T21	4
valid_sources[0x75]	525	1			T8	2		T18	3		T20	3
valid_sources[0x76]	581	1			T18	24		T118	2		T20	1
valid_sources[0x77]	637	1			T18	2		T118	1		T20	3
valid_sources[0x78]	611	1			T8	1		T140	22		T18	1
valid_sources[0x79]	835	1			T8	338		T10	1		T11	4
valid_sources[0x7a]	783	1			T4	67		T18	2		T5	2
valid_sources[0x7b]	762	1			T18	42		T64	1		T151	2
valid_sources[0x7c]	629	1			T8	4		T80	1		T18	1
valid_sources[0x7d]	739	1			T8	3		T18	139		T20	2
valid_sources[0x7e]	663	1			T8	101		T18	26		T155	1
valid_sources[0x7f]	862	1			T8	115		T37	1		T18	16
valid_sources[0x80]	534	1			T8	3		T80	1		T18	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36748

1

T3

2

T7

1

T8

1217

values[0x0]

all_enables

biggest_size

50579

1

T2

1

T3

1

T8

1832

values[0x1]

all_enables

biggest_size

48368

1

T1

1

T8

1862

T9

1