Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14179683

1

T1

133

T2

715

T3

1911

full_word

56753990

1

T1

1099

T2

7114

T3

18479

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	70933363	1			T1	1232		T2	7829		T3	20390
auto[TlIntgErrCmd]	106	1			T56	7		T57	2		T58	6
auto[TlIntgErrData]	95	1			T56	6		T57	3		T58	5
auto[TlIntgErrBoth]	109	1			T56	7		T57	5		T58	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32324181

1

T1

614

T2

3994

T3

7658

auto[1]

38609492

1

T1

618

T2

3835

T3

12732

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6756292	1			T1	66		T2	367		T3	717
auto[TlIntgErrNone]	partial	auto[1]	7423110	1			T1	67		T2	348		T3	1194
auto[TlIntgErrNone]	full_word	auto[0]	25567749	1			T1	548		T2	3627		T3	6941
auto[TlIntgErrNone]	full_word	auto[1]	31186212	1			T1	551		T2	3487		T3	11538
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T56	4		T57	1		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T56	3		T57	1		T58	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T130	1		T131	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T58	1		T124	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T56	2		T57	1		T58	2
auto[TlIntgErrData]	partial	auto[1]	35	1			T56	3		T57	1		T58	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T56	1		T126	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T57	1		T127	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T56	4		T57	2		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T56	3		T57	3		T58	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T58	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T123	1		T131	1		T134	1