Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	810318	1			T1	7		T2	1016		T3	169
auto[1]	10146929	1			T1	30		T2	275		T3	145
auto[2]	671842	1			T1	4		T2	940		T3	110
auto[3]	10019562	1			T1	31		T2	134		T3	59

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14278893	1			T1	51		T2	1847		T3	364
auto[1]	2030587	1			T1	9		T2	274		T3	56
auto[2]	2048161	1			T1	8		T2	213		T3	56
auto[3]	3291010	1			T1	4		T2	31		T3	7

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8112883

1

T1

72

T2

2364

T3

482

auto[1]

13535768

1

T2

1

T3

1

T8

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	281645	1			T1	6		T2	842		T3	132
auto[0]	auto[0]	auto[1]	28893	1			T1	1		T2	97		T3	19
auto[0]	auto[0]	auto[2]	28889	1			T2	69		T3	17		T11	155
auto[0]	auto[0]	auto[3]	7249	1			T2	8		T11	20		T12	9
auto[0]	auto[1]	auto[0]	3036706	1			T1	22		T2	162		T3	111
auto[0]	auto[1]	auto[1]	321889	1			T1	6		T2	84		T3	24
auto[0]	auto[1]	auto[2]	308959	1			T1	1		T2	21		T3	8
auto[0]	auto[1]	auto[3]	87097	1			T1	1		T2	8		T3	2
auto[0]	auto[2]	auto[0]	240819	1			T2	776		T3	85		T11	1327
auto[0]	auto[2]	auto[1]	24726	1			T2	89		T3	9		T11	140
auto[0]	auto[2]	auto[2]	27347	1			T1	3		T2	67		T3	14
auto[0]	auto[2]	auto[3]	6512	1			T1	1		T2	7		T3	2
auto[0]	auto[3]	auto[0]	2996846	1			T1	23		T2	66		T3	35
auto[0]	auto[3]	auto[1]	305252	1			T1	2		T2	4		T3	4
auto[0]	auto[3]	auto[2]	321401	1			T1	4		T2	56		T3	17
auto[0]	auto[3]	auto[3]	88653	1			T1	2		T2	8		T3	3
auto[1]	auto[0]	auto[0]	15572	1			T3	1		T11	2		T12	1027
auto[1]	auto[0]	auto[1]	69030	1			T12	4793		T80	1		T108	4305
auto[1]	auto[0]	auto[2]	68596	1			T12	4808		T80	1		T108	4238
auto[1]	auto[0]	auto[3]	310444	1			T12	21540		T108	19145		T138	3177
auto[1]	auto[1]	auto[0]	3848714	1			T10	35		T4	1		T12	167
auto[1]	auto[1]	auto[1]	643754	1			T10	1		T12	4772		T36	6
auto[1]	auto[1]	auto[2]	605280	1			T10	7		T12	738		T36	4
auto[1]	auto[1]	auto[3]	1294530	1			T10	1		T12	21712		T36	1
auto[1]	auto[2]	auto[0]	11411	1			T2	1		T12	982		T80	2
auto[1]	auto[2]	auto[1]	50370	1			T12	4539		T108	4065		T139	4421
auto[1]	auto[2]	auto[2]	56997	1			T12	4014		T140	1		T108	2831
auto[1]	auto[2]	auto[3]	253660	1			T12	18322		T108	12850		T138	2890
auto[1]	auto[3]	auto[0]	3847180	1			T8	2		T10	39		T4	1
auto[1]	auto[3]	auto[1]	586673	1			T10	5		T12	390		T36	6
auto[1]	auto[3]	auto[2]	630692	1			T10	2		T12	4161		T36	12
auto[1]	auto[3]	auto[3]	1242865	1			T12	18477		T99	768		T141	6