Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	349512819	205437	0	0
ctrl_regwen_rd_A	349512819	3903	0	0
exec_rd_A	349512819	3656	0	0
exec_regwen_rd_A	349512819	4119	0	0
readback_rd_A	349512819	2425	0	0
readback_regwen_rd_A	349512819	2051	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349512819	205437	0	0
T4	55205	0	0	0
T8	200932	8398	0	0
T9	1254	0	0	0
T10	319453	0	0	0
T11	162526	0	0	0
T12	194849	0	0	0
T18	0	5714	0	0
T21	0	2820	0	0
T36	456623	0	0	0
T38	113589	0	0	0
T47	0	5495	0	0
T51	8156	0	0	0
T52	413348	0	0	0
T65	0	1299	0	0
T66	0	8725	0	0
T67	0	4373	0	0
T68	0	9244	0	0
T69	0	9469	0	0
T70	0	4311	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349512819	3903	0	0
T18	184605	386	0	0
T19	281045	0	0	0
T22	2068	0	0	0
T39	11977	0	0	0
T40	0	512	0	0
T41	0	276	0	0
T48	17401	0	0	0
T64	340493	0	0	0
T65	0	46	0	0
T110	0	93	0	0
T111	0	82	0	0
T112	0	200	0	0
T113	0	92	0	0
T114	0	180	0	0
T115	0	312	0	0
T116	294314	0	0	0
T117	6564	0	0	0
T118	118455	0	0	0
T119	37908	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349512819	3656	0	0
T18	184605	340	0	0
T19	281045	0	0	0
T22	2068	0	0	0
T39	11977	0	0	0
T40	0	288	0	0
T41	0	248	0	0
T48	17401	0	0	0
T64	340493	0	0	0
T65	0	79	0	0
T110	0	60	0	0
T111	0	98	0	0
T112	0	262	0	0
T113	0	83	0	0
T114	0	119	0	0
T115	0	274	0	0
T116	294314	0	0	0
T117	6564	0	0	0
T118	118455	0	0	0
T119	37908	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349512819	4119	0	0
T18	184605	422	0	0
T19	281045	0	0	0
T22	2068	0	0	0
T39	11977	0	0	0
T40	0	416	0	0
T41	0	252	0	0
T48	17401	0	0	0
T64	340493	0	0	0
T65	0	48	0	0
T110	0	120	0	0
T111	0	83	0	0
T112	0	281	0	0
T113	0	79	0	0
T114	0	129	0	0
T115	0	297	0	0
T116	294314	0	0	0
T117	6564	0	0	0
T118	118455	0	0	0
T119	37908	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349512819	2425	0	0
T18	184605	359	0	0
T19	281045	0	0	0
T22	2068	0	0	0
T39	11977	0	0	0
T40	0	387	0	0
T41	0	333	0	0
T48	17401	0	0	0
T64	340493	0	0	0
T65	0	41	0	0
T110	0	55	0	0
T111	0	69	0	0
T112	0	302	0	0
T113	0	79	0	0
T114	0	138	0	0
T115	0	305	0	0
T116	294314	0	0	0
T117	6564	0	0	0
T118	118455	0	0	0
T119	37908	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349512819	2051	0	0
T18	184605	306	0	0
T19	281045	0	0	0
T22	2068	0	0	0
T39	11977	0	0	0
T40	0	312	0	0
T41	0	196	0	0
T48	17401	0	0	0
T64	340493	0	0	0
T65	0	44	0	0
T110	0	108	0	0
T111	0	82	0	0
T112	0	260	0	0
T113	0	38	0	0
T114	0	111	0	0
T115	0	247	0	0
T116	294314	0	0	0
T117	6564	0	0	0
T118	118455	0	0	0
T119	37908	0	0	0