| T796 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1386213686 |
|
|
Jul 25 06:07:57 PM PDT 24 |
Jul 25 06:12:53 PM PDT 24 |
21298148935 ps |
| T797 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2647489769 |
|
|
Jul 25 06:12:07 PM PDT 24 |
Jul 25 06:13:04 PM PDT 24 |
103552175 ps |
| T798 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2754953567 |
|
|
Jul 25 06:12:13 PM PDT 24 |
Jul 25 06:12:24 PM PDT 24 |
295203691 ps |
| T799 |
/workspace/coverage/default/33.sram_ctrl_regwen.63000376 |
|
|
Jul 25 06:10:13 PM PDT 24 |
Jul 25 06:45:44 PM PDT 24 |
17939924956 ps |
| T800 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2601238620 |
|
|
Jul 25 06:08:40 PM PDT 24 |
Jul 25 06:08:46 PM PDT 24 |
1578821814 ps |
| T801 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3769292167 |
|
|
Jul 25 06:07:25 PM PDT 24 |
Jul 25 06:09:39 PM PDT 24 |
434371412 ps |
| T802 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.4101570513 |
|
|
Jul 25 06:07:43 PM PDT 24 |
Jul 25 06:07:47 PM PDT 24 |
107285277 ps |
| T803 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1798807634 |
|
|
Jul 25 06:07:43 PM PDT 24 |
Jul 25 06:07:48 PM PDT 24 |
204244190 ps |
| T804 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.403783384 |
|
|
Jul 25 06:10:05 PM PDT 24 |
Jul 25 06:10:06 PM PDT 24 |
120885407 ps |
| T805 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.616682100 |
|
|
Jul 25 06:06:58 PM PDT 24 |
Jul 25 06:07:01 PM PDT 24 |
113680447 ps |
| T806 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4239851473 |
|
|
Jul 25 06:08:19 PM PDT 24 |
Jul 25 06:27:53 PM PDT 24 |
7025795319 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2326567783 |
|
|
Jul 25 06:10:17 PM PDT 24 |
Jul 25 06:10:34 PM PDT 24 |
420363739 ps |
| T808 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1040148257 |
|
|
Jul 25 06:08:47 PM PDT 24 |
Jul 25 06:08:55 PM PDT 24 |
2631653845 ps |
| T809 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.4000132240 |
|
|
Jul 25 06:07:32 PM PDT 24 |
Jul 25 06:20:21 PM PDT 24 |
1192146423 ps |
| T810 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2188396621 |
|
|
Jul 25 06:07:36 PM PDT 24 |
Jul 25 06:30:47 PM PDT 24 |
58719326899 ps |
| T811 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.664129584 |
|
|
Jul 25 06:08:05 PM PDT 24 |
Jul 25 06:08:11 PM PDT 24 |
348695806 ps |
| T812 |
/workspace/coverage/default/23.sram_ctrl_smoke.2855582590 |
|
|
Jul 25 06:08:32 PM PDT 24 |
Jul 25 06:08:36 PM PDT 24 |
841902867 ps |
| T813 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2526598957 |
|
|
Jul 25 06:12:00 PM PDT 24 |
Jul 25 06:14:09 PM PDT 24 |
164966097 ps |
| T814 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.3818497327 |
|
|
Jul 25 06:10:32 PM PDT 24 |
Jul 25 06:10:33 PM PDT 24 |
86636069 ps |
| T815 |
/workspace/coverage/default/27.sram_ctrl_regwen.2311126023 |
|
|
Jul 25 06:09:18 PM PDT 24 |
Jul 25 06:17:44 PM PDT 24 |
7415510160 ps |
| T816 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1042254060 |
|
|
Jul 25 06:07:58 PM PDT 24 |
Jul 25 06:08:10 PM PDT 24 |
681088623 ps |
| T817 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3838109203 |
|
|
Jul 25 06:07:01 PM PDT 24 |
Jul 25 06:11:32 PM PDT 24 |
895844236 ps |
| T818 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2346671428 |
|
|
Jul 25 06:08:18 PM PDT 24 |
Jul 25 06:08:20 PM PDT 24 |
205725894 ps |
| T819 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.237398001 |
|
|
Jul 25 06:06:57 PM PDT 24 |
Jul 25 06:07:02 PM PDT 24 |
72351471 ps |
| T820 |
/workspace/coverage/default/16.sram_ctrl_smoke.1654760688 |
|
|
Jul 25 06:07:46 PM PDT 24 |
Jul 25 06:08:04 PM PDT 24 |
1155412509 ps |
| T821 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.17176038 |
|
|
Jul 25 06:11:40 PM PDT 24 |
Jul 25 06:14:15 PM PDT 24 |
158808384 ps |
| T822 |
/workspace/coverage/default/12.sram_ctrl_smoke.1565785515 |
|
|
Jul 25 06:07:30 PM PDT 24 |
Jul 25 06:08:40 PM PDT 24 |
1817502569 ps |
| T823 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.59305322 |
|
|
Jul 25 06:12:07 PM PDT 24 |
Jul 25 06:12:14 PM PDT 24 |
1317825037 ps |
| T824 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3201579160 |
|
|
Jul 25 06:08:18 PM PDT 24 |
Jul 25 06:16:03 PM PDT 24 |
39281630912 ps |
| T825 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.434428699 |
|
|
Jul 25 06:10:22 PM PDT 24 |
Jul 25 06:10:28 PM PDT 24 |
374719323 ps |
| T826 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.183349066 |
|
|
Jul 25 06:12:54 PM PDT 24 |
Jul 25 06:17:12 PM PDT 24 |
3365377423 ps |
| T827 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3022620070 |
|
|
Jul 25 06:07:18 PM PDT 24 |
Jul 25 06:34:10 PM PDT 24 |
44671724822 ps |
| T828 |
/workspace/coverage/default/7.sram_ctrl_smoke.4287782227 |
|
|
Jul 25 06:07:24 PM PDT 24 |
Jul 25 06:07:28 PM PDT 24 |
1483522701 ps |
| T829 |
/workspace/coverage/default/32.sram_ctrl_smoke.2041140839 |
|
|
Jul 25 06:10:06 PM PDT 24 |
Jul 25 06:10:42 PM PDT 24 |
1625097166 ps |
| T830 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1863816188 |
|
|
Jul 25 06:07:38 PM PDT 24 |
Jul 25 06:24:35 PM PDT 24 |
54704973797 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1745743476 |
|
|
Jul 25 06:07:55 PM PDT 24 |
Jul 25 06:08:04 PM PDT 24 |
4257548377 ps |
| T832 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3455556571 |
|
|
Jul 25 06:13:03 PM PDT 24 |
Jul 25 06:18:31 PM PDT 24 |
3421535370 ps |
| T833 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.692608935 |
|
|
Jul 25 06:07:34 PM PDT 24 |
Jul 25 06:08:13 PM PDT 24 |
195503869 ps |
| T834 |
/workspace/coverage/default/17.sram_ctrl_bijection.2674637943 |
|
|
Jul 25 06:08:02 PM PDT 24 |
Jul 25 06:09:00 PM PDT 24 |
11945190549 ps |
| T835 |
/workspace/coverage/default/45.sram_ctrl_bijection.1043330002 |
|
|
Jul 25 06:12:29 PM PDT 24 |
Jul 25 06:13:03 PM PDT 24 |
1490485977 ps |
| T836 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1156947178 |
|
|
Jul 25 06:07:37 PM PDT 24 |
Jul 25 06:13:27 PM PDT 24 |
19272188142 ps |
| T837 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.76746579 |
|
|
Jul 25 06:09:14 PM PDT 24 |
Jul 25 06:19:10 PM PDT 24 |
61182847745 ps |
| T838 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3283047405 |
|
|
Jul 25 06:07:37 PM PDT 24 |
Jul 25 06:12:32 PM PDT 24 |
37048200868 ps |
| T839 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3786005454 |
|
|
Jul 25 06:07:37 PM PDT 24 |
Jul 25 06:45:46 PM PDT 24 |
134559034625 ps |
| T840 |
/workspace/coverage/default/22.sram_ctrl_partial_access.475950252 |
|
|
Jul 25 06:08:25 PM PDT 24 |
Jul 25 06:08:42 PM PDT 24 |
3954218231 ps |
| T841 |
/workspace/coverage/default/4.sram_ctrl_executable.84723411 |
|
|
Jul 25 06:07:24 PM PDT 24 |
Jul 25 06:23:29 PM PDT 24 |
11851644988 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3583640182 |
|
|
Jul 25 06:07:48 PM PDT 24 |
Jul 25 06:15:11 PM PDT 24 |
61570926432 ps |
| T843 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.1265668194 |
|
|
Jul 25 06:08:18 PM PDT 24 |
Jul 25 06:34:36 PM PDT 24 |
80668253255 ps |
| T844 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3391364580 |
|
|
Jul 25 06:10:18 PM PDT 24 |
Jul 25 06:17:07 PM PDT 24 |
77308672910 ps |
| T845 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.602808046 |
|
|
Jul 25 06:07:33 PM PDT 24 |
Jul 25 06:08:21 PM PDT 24 |
209870490 ps |
| T846 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1638009615 |
|
|
Jul 25 06:07:34 PM PDT 24 |
Jul 25 06:07:35 PM PDT 24 |
90221844 ps |
| T847 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2893175469 |
|
|
Jul 25 06:07:34 PM PDT 24 |
Jul 25 06:44:30 PM PDT 24 |
161592206317 ps |
| T848 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1635490513 |
|
|
Jul 25 06:11:50 PM PDT 24 |
Jul 25 06:11:51 PM PDT 24 |
296982144 ps |
| T849 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1116390779 |
|
|
Jul 25 06:07:27 PM PDT 24 |
Jul 25 06:47:41 PM PDT 24 |
18437763799 ps |
| T850 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1392693749 |
|
|
Jul 25 06:10:51 PM PDT 24 |
Jul 25 06:15:49 PM PDT 24 |
58256593330 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3024653377 |
|
|
Jul 25 06:07:50 PM PDT 24 |
Jul 25 06:07:55 PM PDT 24 |
365441812 ps |
| T852 |
/workspace/coverage/default/20.sram_ctrl_smoke.3960069712 |
|
|
Jul 25 06:08:11 PM PDT 24 |
Jul 25 06:09:06 PM PDT 24 |
1979750430 ps |
| T853 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2937055755 |
|
|
Jul 25 06:07:03 PM PDT 24 |
Jul 25 06:16:19 PM PDT 24 |
21115068988 ps |
| T854 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.413610118 |
|
|
Jul 25 06:09:21 PM PDT 24 |
Jul 25 06:25:53 PM PDT 24 |
3318086180 ps |
| T855 |
/workspace/coverage/default/34.sram_ctrl_executable.1960736331 |
|
|
Jul 25 06:10:21 PM PDT 24 |
Jul 25 06:29:35 PM PDT 24 |
40026136012 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1501589227 |
|
|
Jul 25 06:08:15 PM PDT 24 |
Jul 25 06:37:02 PM PDT 24 |
44993155063 ps |
| T857 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4166778896 |
|
|
Jul 25 06:13:24 PM PDT 24 |
Jul 25 06:13:25 PM PDT 24 |
20544280 ps |
| T858 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1361444561 |
|
|
Jul 25 06:09:11 PM PDT 24 |
Jul 25 06:55:12 PM PDT 24 |
43420383641 ps |
| T859 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1992647020 |
|
|
Jul 25 06:07:03 PM PDT 24 |
Jul 25 06:07:09 PM PDT 24 |
232977505 ps |
| T860 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.3332689182 |
|
|
Jul 25 06:08:40 PM PDT 24 |
Jul 25 06:16:56 PM PDT 24 |
2228078158 ps |
| T861 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3800113514 |
|
|
Jul 25 06:09:53 PM PDT 24 |
Jul 25 06:18:57 PM PDT 24 |
277449406311 ps |
| T862 |
/workspace/coverage/default/35.sram_ctrl_bijection.4008698779 |
|
|
Jul 25 06:10:25 PM PDT 24 |
Jul 25 06:11:41 PM PDT 24 |
3557928011 ps |
| T863 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3126791738 |
|
|
Jul 25 06:11:32 PM PDT 24 |
Jul 25 06:29:00 PM PDT 24 |
1942397076 ps |
| T864 |
/workspace/coverage/default/48.sram_ctrl_smoke.100984412 |
|
|
Jul 25 06:13:10 PM PDT 24 |
Jul 25 06:13:19 PM PDT 24 |
248515038 ps |
| T865 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2974650735 |
|
|
Jul 25 06:07:29 PM PDT 24 |
Jul 25 06:07:31 PM PDT 24 |
47196946 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_alert_test.172536277 |
|
|
Jul 25 06:08:46 PM PDT 24 |
Jul 25 06:08:47 PM PDT 24 |
11005157 ps |
| T867 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3455718690 |
|
|
Jul 25 06:08:58 PM PDT 24 |
Jul 25 06:09:03 PM PDT 24 |
2075551045 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1109005685 |
|
|
Jul 25 06:07:23 PM PDT 24 |
Jul 25 06:07:26 PM PDT 24 |
901900467 ps |
| T868 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1936167298 |
|
|
Jul 25 06:07:41 PM PDT 24 |
Jul 25 06:08:50 PM PDT 24 |
2216423541 ps |
| T869 |
/workspace/coverage/default/16.sram_ctrl_bijection.1503905645 |
|
|
Jul 25 06:07:59 PM PDT 24 |
Jul 25 06:08:55 PM PDT 24 |
4528124387 ps |
| T870 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1984493926 |
|
|
Jul 25 06:10:21 PM PDT 24 |
Jul 25 06:11:52 PM PDT 24 |
134945226 ps |
| T871 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2534525761 |
|
|
Jul 25 06:13:07 PM PDT 24 |
Jul 25 06:31:23 PM PDT 24 |
13241339438 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.195150069 |
|
|
Jul 25 06:12:52 PM PDT 24 |
Jul 25 06:17:57 PM PDT 24 |
2783220901 ps |
| T873 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2902043226 |
|
|
Jul 25 06:10:13 PM PDT 24 |
Jul 25 06:10:19 PM PDT 24 |
347318498 ps |
| T874 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.4069441953 |
|
|
Jul 25 06:09:53 PM PDT 24 |
Jul 25 06:16:05 PM PDT 24 |
4196931809 ps |
| T875 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3674768141 |
|
|
Jul 25 06:08:05 PM PDT 24 |
Jul 25 06:17:20 PM PDT 24 |
245525679607 ps |
| T876 |
/workspace/coverage/default/29.sram_ctrl_smoke.914938785 |
|
|
Jul 25 06:09:29 PM PDT 24 |
Jul 25 06:10:35 PM PDT 24 |
549304206 ps |
| T877 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2663987558 |
|
|
Jul 25 06:12:04 PM PDT 24 |
Jul 25 06:12:19 PM PDT 24 |
1328001846 ps |
| T878 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3540068221 |
|
|
Jul 25 06:07:48 PM PDT 24 |
Jul 25 06:10:49 PM PDT 24 |
8772688519 ps |
| T879 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3620227928 |
|
|
Jul 25 06:11:39 PM PDT 24 |
Jul 25 06:19:17 PM PDT 24 |
33586405963 ps |
| T880 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3161573121 |
|
|
Jul 25 06:07:33 PM PDT 24 |
Jul 25 06:07:41 PM PDT 24 |
2829985023 ps |
| T881 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2913840349 |
|
|
Jul 25 06:10:51 PM PDT 24 |
Jul 25 07:18:11 PM PDT 24 |
54182764650 ps |
| T882 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.342031200 |
|
|
Jul 25 06:08:56 PM PDT 24 |
Jul 25 06:15:35 PM PDT 24 |
32233068578 ps |
| T883 |
/workspace/coverage/default/23.sram_ctrl_bijection.305215911 |
|
|
Jul 25 06:08:29 PM PDT 24 |
Jul 25 06:08:59 PM PDT 24 |
1727495096 ps |
| T884 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2215734932 |
|
|
Jul 25 06:11:36 PM PDT 24 |
Jul 25 06:11:47 PM PDT 24 |
460965645 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.2887557819 |
|
|
Jul 25 06:07:56 PM PDT 24 |
Jul 25 06:07:57 PM PDT 24 |
83934811 ps |
| T886 |
/workspace/coverage/default/3.sram_ctrl_regwen.1638951437 |
|
|
Jul 25 06:07:15 PM PDT 24 |
Jul 25 06:32:18 PM PDT 24 |
2993706218 ps |
| T887 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2999196271 |
|
|
Jul 25 06:07:22 PM PDT 24 |
Jul 25 06:07:23 PM PDT 24 |
140461826 ps |
| T888 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2253573035 |
|
|
Jul 25 06:08:20 PM PDT 24 |
Jul 25 06:15:08 PM PDT 24 |
10980033729 ps |
| T889 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.550944391 |
|
|
Jul 25 06:07:15 PM PDT 24 |
Jul 25 06:07:16 PM PDT 24 |
44058177 ps |
| T890 |
/workspace/coverage/default/17.sram_ctrl_partial_access.4124759755 |
|
|
Jul 25 06:08:03 PM PDT 24 |
Jul 25 06:10:00 PM PDT 24 |
201675803 ps |
| T891 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.734772347 |
|
|
Jul 25 06:11:39 PM PDT 24 |
Jul 25 06:11:40 PM PDT 24 |
80628501 ps |
| T892 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3068921405 |
|
|
Jul 25 06:09:07 PM PDT 24 |
Jul 25 06:25:56 PM PDT 24 |
7369468213 ps |
| T893 |
/workspace/coverage/default/17.sram_ctrl_executable.980998326 |
|
|
Jul 25 06:08:07 PM PDT 24 |
Jul 25 06:25:10 PM PDT 24 |
3703420047 ps |
| T894 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.812589924 |
|
|
Jul 25 06:09:54 PM PDT 24 |
Jul 25 06:12:51 PM PDT 24 |
9670869634 ps |
| T895 |
/workspace/coverage/default/30.sram_ctrl_regwen.2238764541 |
|
|
Jul 25 06:09:47 PM PDT 24 |
Jul 25 06:27:25 PM PDT 24 |
20877737019 ps |
| T896 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.78109731 |
|
|
Jul 25 06:10:02 PM PDT 24 |
Jul 25 06:26:04 PM PDT 24 |
32585584634 ps |
| T897 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2526375916 |
|
|
Jul 25 06:08:28 PM PDT 24 |
Jul 25 06:08:33 PM PDT 24 |
137315646 ps |
| T898 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2590160086 |
|
|
Jul 25 06:10:05 PM PDT 24 |
Jul 25 06:10:06 PM PDT 24 |
210536723 ps |
| T899 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.4134955070 |
|
|
Jul 25 06:11:41 PM PDT 24 |
Jul 25 06:11:47 PM PDT 24 |
605938331 ps |
| T900 |
/workspace/coverage/default/15.sram_ctrl_bijection.530524487 |
|
|
Jul 25 06:07:52 PM PDT 24 |
Jul 25 06:08:28 PM PDT 24 |
1346237163 ps |
| T114 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1124252610 |
|
|
Jul 25 06:11:02 PM PDT 24 |
Jul 25 06:13:12 PM PDT 24 |
3395199351 ps |
| T901 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.650429222 |
|
|
Jul 25 06:09:48 PM PDT 24 |
Jul 25 06:09:54 PM PDT 24 |
1833792075 ps |
| T902 |
/workspace/coverage/default/38.sram_ctrl_partial_access.335245220 |
|
|
Jul 25 06:11:00 PM PDT 24 |
Jul 25 06:13:29 PM PDT 24 |
3598703307 ps |
| T903 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.633484667 |
|
|
Jul 25 06:08:19 PM PDT 24 |
Jul 25 06:09:50 PM PDT 24 |
269141858 ps |
| T904 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.309503531 |
|
|
Jul 25 06:09:27 PM PDT 24 |
Jul 25 06:09:33 PM PDT 24 |
250526141 ps |
| T905 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1105773152 |
|
|
Jul 25 06:12:19 PM PDT 24 |
Jul 25 06:12:28 PM PDT 24 |
710175900 ps |
| T906 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2601977517 |
|
|
Jul 25 06:07:32 PM PDT 24 |
Jul 25 06:11:35 PM PDT 24 |
4064365376 ps |
| T907 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1331172568 |
|
|
Jul 25 06:13:08 PM PDT 24 |
Jul 25 06:13:53 PM PDT 24 |
396033150 ps |
| T908 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.1526908826 |
|
|
Jul 25 06:12:46 PM PDT 24 |
Jul 25 06:13:00 PM PDT 24 |
2729406181 ps |
| T909 |
/workspace/coverage/default/9.sram_ctrl_alert_test.746406428 |
|
|
Jul 25 06:07:32 PM PDT 24 |
Jul 25 06:07:33 PM PDT 24 |
29952538 ps |
| T115 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3210526656 |
|
|
Jul 25 06:08:23 PM PDT 24 |
Jul 25 06:09:10 PM PDT 24 |
15200487035 ps |
| T910 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3041005492 |
|
|
Jul 25 06:07:27 PM PDT 24 |
Jul 25 06:07:28 PM PDT 24 |
64928067 ps |
| T911 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3538012414 |
|
|
Jul 25 06:09:33 PM PDT 24 |
Jul 25 06:09:45 PM PDT 24 |
71312849 ps |
| T912 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3561959671 |
|
|
Jul 25 06:13:05 PM PDT 24 |
Jul 25 06:21:43 PM PDT 24 |
2037213254 ps |
| T913 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3801085840 |
|
|
Jul 25 06:07:20 PM PDT 24 |
Jul 25 06:16:20 PM PDT 24 |
20976835741 ps |
| T914 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1825427891 |
|
|
Jul 25 06:09:34 PM PDT 24 |
Jul 25 06:09:35 PM PDT 24 |
27282940 ps |
| T915 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1799341444 |
|
|
Jul 25 06:08:17 PM PDT 24 |
Jul 25 07:01:57 PM PDT 24 |
86866736983 ps |
| T916 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1190051476 |
|
|
Jul 25 06:07:06 PM PDT 24 |
Jul 25 06:13:48 PM PDT 24 |
14914552589 ps |
| T917 |
/workspace/coverage/default/26.sram_ctrl_regwen.420912721 |
|
|
Jul 25 06:09:10 PM PDT 24 |
Jul 25 06:27:35 PM PDT 24 |
13368373412 ps |
| T918 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.683827005 |
|
|
Jul 25 06:11:37 PM PDT 24 |
Jul 25 06:12:11 PM PDT 24 |
363321355 ps |
| T919 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3281656364 |
|
|
Jul 25 06:07:43 PM PDT 24 |
Jul 25 06:07:44 PM PDT 24 |
26854282 ps |
| T920 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3338860727 |
|
|
Jul 25 06:12:29 PM PDT 24 |
Jul 25 06:13:51 PM PDT 24 |
3152222858 ps |
| T921 |
/workspace/coverage/default/6.sram_ctrl_smoke.1226177702 |
|
|
Jul 25 06:07:20 PM PDT 24 |
Jul 25 06:07:30 PM PDT 24 |
469838514 ps |
| T922 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.295007946 |
|
|
Jul 25 06:12:13 PM PDT 24 |
Jul 25 06:12:17 PM PDT 24 |
361974371 ps |
| T923 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2293896473 |
|
|
Jul 25 06:10:51 PM PDT 24 |
Jul 25 06:13:22 PM PDT 24 |
530160366 ps |
| T924 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.45665485 |
|
|
Jul 25 06:13:17 PM PDT 24 |
Jul 25 06:14:58 PM PDT 24 |
504369454 ps |
| T925 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.3276902069 |
|
|
Jul 25 06:12:53 PM PDT 24 |
Jul 25 06:13:42 PM PDT 24 |
118894014 ps |
| T926 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2995466090 |
|
|
Jul 25 06:08:06 PM PDT 24 |
Jul 25 06:10:22 PM PDT 24 |
1370525502 ps |
| T927 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3992187353 |
|
|
Jul 25 06:13:07 PM PDT 24 |
Jul 25 06:43:04 PM PDT 24 |
24816475931 ps |
| T928 |
/workspace/coverage/default/28.sram_ctrl_regwen.4245311654 |
|
|
Jul 25 06:09:15 PM PDT 24 |
Jul 25 06:23:52 PM PDT 24 |
10663357607 ps |
| T929 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2821701297 |
|
|
Jul 25 06:10:14 PM PDT 24 |
Jul 25 06:33:28 PM PDT 24 |
53816027163 ps |
| T930 |
/workspace/coverage/default/37.sram_ctrl_regwen.3503067929 |
|
|
Jul 25 06:11:03 PM PDT 24 |
Jul 25 06:36:36 PM PDT 24 |
59640677664 ps |
| T931 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.351750133 |
|
|
Jul 25 06:07:20 PM PDT 24 |
Jul 25 06:13:15 PM PDT 24 |
4095203548 ps |
| T62 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1443030732 |
|
|
Jul 25 06:36:29 PM PDT 24 |
Jul 25 06:36:30 PM PDT 24 |
15509441 ps |
| T932 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1748120626 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:05 PM PDT 24 |
154235947 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2312210713 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
684007674 ps |
| T933 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.192149574 |
|
|
Jul 25 06:35:59 PM PDT 24 |
Jul 25 06:36:01 PM PDT 24 |
255381500 ps |
| T63 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1616082194 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:02 PM PDT 24 |
441202138 ps |
| T934 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4067110898 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:04 PM PDT 24 |
76196057 ps |
| T57 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1638739565 |
|
|
Jul 25 06:36:24 PM PDT 24 |
Jul 25 06:36:26 PM PDT 24 |
266512591 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3217829599 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:01 PM PDT 24 |
67147799 ps |
| T935 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4163971915 |
|
|
Jul 25 06:36:12 PM PDT 24 |
Jul 25 06:36:16 PM PDT 24 |
137764377 ps |
| T101 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2357590543 |
|
|
Jul 25 06:36:09 PM PDT 24 |
Jul 25 06:36:10 PM PDT 24 |
16455626 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.620059619 |
|
|
Jul 25 06:36:02 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
16630582 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2487087991 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:04 PM PDT 24 |
100637861 ps |
| T58 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2653634900 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:06 PM PDT 24 |
193781219 ps |
| T102 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1115914697 |
|
|
Jul 25 06:36:27 PM PDT 24 |
Jul 25 06:36:28 PM PDT 24 |
50928242 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.933650163 |
|
|
Jul 25 06:36:09 PM PDT 24 |
Jul 25 06:36:10 PM PDT 24 |
12174845 ps |
| T936 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1167684754 |
|
|
Jul 25 06:35:59 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
44202855 ps |
| T937 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.896201538 |
|
|
Jul 25 06:36:12 PM PDT 24 |
Jul 25 06:36:16 PM PDT 24 |
111837283 ps |
| T125 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.965255379 |
|
|
Jul 25 06:36:26 PM PDT 24 |
Jul 25 06:36:28 PM PDT 24 |
80256632 ps |
| T938 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3241870992 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:02 PM PDT 24 |
41707524 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4022539865 |
|
|
Jul 25 06:36:25 PM PDT 24 |
Jul 25 06:36:29 PM PDT 24 |
2725155620 ps |
| T939 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1910642084 |
|
|
Jul 25 06:36:02 PM PDT 24 |
Jul 25 06:36:06 PM PDT 24 |
194053954 ps |
| T123 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3431591015 |
|
|
Jul 25 06:36:25 PM PDT 24 |
Jul 25 06:36:28 PM PDT 24 |
222389937 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2912735586 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:20 PM PDT 24 |
21243425 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3694421805 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
67797993 ps |
| T127 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1447583765 |
|
|
Jul 25 06:36:09 PM PDT 24 |
Jul 25 06:36:11 PM PDT 24 |
583121734 ps |
| T74 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3898094992 |
|
|
Jul 25 06:36:18 PM PDT 24 |
Jul 25 06:36:18 PM PDT 24 |
18913534 ps |
| T75 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1020166350 |
|
|
Jul 25 06:36:21 PM PDT 24 |
Jul 25 06:36:22 PM PDT 24 |
62776658 ps |
| T941 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.329149820 |
|
|
Jul 25 06:36:27 PM PDT 24 |
Jul 25 06:36:31 PM PDT 24 |
209559085 ps |
| T942 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.185561447 |
|
|
Jul 25 06:36:23 PM PDT 24 |
Jul 25 06:36:27 PM PDT 24 |
133732337 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3450029188 |
|
|
Jul 25 06:36:09 PM PDT 24 |
Jul 25 06:36:13 PM PDT 24 |
1687224059 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.96618022 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:20 PM PDT 24 |
77274019 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2188765465 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:02 PM PDT 24 |
43798603 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.386852011 |
|
|
Jul 25 06:36:25 PM PDT 24 |
Jul 25 06:36:28 PM PDT 24 |
64857861 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3203836786 |
|
|
Jul 25 06:36:16 PM PDT 24 |
Jul 25 06:36:18 PM PDT 24 |
131511435 ps |
| T947 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1437580590 |
|
|
Jul 25 06:36:07 PM PDT 24 |
Jul 25 06:36:10 PM PDT 24 |
283341543 ps |
| T124 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1919140575 |
|
|
Jul 25 06:36:27 PM PDT 24 |
Jul 25 06:36:29 PM PDT 24 |
150939015 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2279913652 |
|
|
Jul 25 06:36:04 PM PDT 24 |
Jul 25 06:36:05 PM PDT 24 |
88968299 ps |
| T77 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3557385073 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:02 PM PDT 24 |
209667893 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2351543436 |
|
|
Jul 25 06:36:30 PM PDT 24 |
Jul 25 06:36:31 PM PDT 24 |
23577502 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.123398395 |
|
|
Jul 25 06:36:20 PM PDT 24 |
Jul 25 06:36:24 PM PDT 24 |
2543328160 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1716114494 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:04 PM PDT 24 |
16010426 ps |
| T128 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2169272312 |
|
|
Jul 25 06:36:27 PM PDT 24 |
Jul 25 06:36:29 PM PDT 24 |
265546505 ps |
| T79 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1562937890 |
|
|
Jul 25 06:36:28 PM PDT 24 |
Jul 25 06:36:30 PM PDT 24 |
1626968370 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.767242665 |
|
|
Jul 25 06:36:13 PM PDT 24 |
Jul 25 06:36:14 PM PDT 24 |
15454533 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3650590245 |
|
|
Jul 25 06:36:22 PM PDT 24 |
Jul 25 06:36:23 PM PDT 24 |
17544041 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.656152618 |
|
|
Jul 25 06:36:07 PM PDT 24 |
Jul 25 06:36:08 PM PDT 24 |
18284304 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1320403467 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:05 PM PDT 24 |
51522219 ps |
| T954 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2939189109 |
|
|
Jul 25 06:36:31 PM PDT 24 |
Jul 25 06:36:33 PM PDT 24 |
305112353 ps |
| T91 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4291901820 |
|
|
Jul 25 06:36:11 PM PDT 24 |
Jul 25 06:36:13 PM PDT 24 |
879102817 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4257077245 |
|
|
Jul 25 06:36:10 PM PDT 24 |
Jul 25 06:36:11 PM PDT 24 |
24879255 ps |
| T956 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3941945967 |
|
|
Jul 25 06:36:28 PM PDT 24 |
Jul 25 06:36:31 PM PDT 24 |
269402552 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2168317659 |
|
|
Jul 25 06:36:18 PM PDT 24 |
Jul 25 06:36:19 PM PDT 24 |
93240081 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1659616093 |
|
|
Jul 25 06:36:31 PM PDT 24 |
Jul 25 06:36:34 PM PDT 24 |
165885910 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3193825182 |
|
|
Jul 25 06:36:29 PM PDT 24 |
Jul 25 06:36:33 PM PDT 24 |
1517061402 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4138558176 |
|
|
Jul 25 06:36:12 PM PDT 24 |
Jul 25 06:36:14 PM PDT 24 |
68743462 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.500358902 |
|
|
Jul 25 06:36:05 PM PDT 24 |
Jul 25 06:36:07 PM PDT 24 |
82900775 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1186851483 |
|
|
Jul 25 06:35:59 PM PDT 24 |
Jul 25 06:36:00 PM PDT 24 |
374451812 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1382073002 |
|
|
Jul 25 06:36:23 PM PDT 24 |
Jul 25 06:36:26 PM PDT 24 |
400214513 ps |
| T960 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1388097214 |
|
|
Jul 25 06:36:26 PM PDT 24 |
Jul 25 06:36:27 PM PDT 24 |
103693384 ps |
| T132 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3802517930 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:21 PM PDT 24 |
221885558 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1785514512 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:05 PM PDT 24 |
137283523 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1957334622 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:01 PM PDT 24 |
24043400 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2206100621 |
|
|
Jul 25 06:36:11 PM PDT 24 |
Jul 25 06:36:12 PM PDT 24 |
29721227 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2135365640 |
|
|
Jul 25 06:36:32 PM PDT 24 |
Jul 25 06:36:34 PM PDT 24 |
134868927 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2238963069 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:20 PM PDT 24 |
38776446 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.637912455 |
|
|
Jul 25 06:36:16 PM PDT 24 |
Jul 25 06:36:17 PM PDT 24 |
16062167 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1013391910 |
|
|
Jul 25 06:36:10 PM PDT 24 |
Jul 25 06:36:12 PM PDT 24 |
59820630 ps |
| T130 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3945678399 |
|
|
Jul 25 06:36:13 PM PDT 24 |
Jul 25 06:36:15 PM PDT 24 |
414268083 ps |
| T968 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3981207213 |
|
|
Jul 25 06:36:15 PM PDT 24 |
Jul 25 06:36:17 PM PDT 24 |
59669135 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3436623529 |
|
|
Jul 25 06:36:02 PM PDT 24 |
Jul 25 06:36:05 PM PDT 24 |
397452356 ps |
| T131 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4267771034 |
|
|
Jul 25 06:36:22 PM PDT 24 |
Jul 25 06:36:23 PM PDT 24 |
91661342 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1973795352 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:21 PM PDT 24 |
117244684 ps |
| T92 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1310951104 |
|
|
Jul 25 06:36:09 PM PDT 24 |
Jul 25 06:36:12 PM PDT 24 |
235843755 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1766044782 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:22 PM PDT 24 |
262800167 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2765446193 |
|
|
Jul 25 06:36:02 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
24111205 ps |
| T93 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2657091042 |
|
|
Jul 25 06:36:21 PM PDT 24 |
Jul 25 06:36:25 PM PDT 24 |
388247345 ps |
| T972 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3005142053 |
|
|
Jul 25 06:36:12 PM PDT 24 |
Jul 25 06:36:13 PM PDT 24 |
156541635 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3461371650 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
46967269 ps |
| T134 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4167065257 |
|
|
Jul 25 06:36:21 PM PDT 24 |
Jul 25 06:36:24 PM PDT 24 |
1380238060 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.949281474 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:04 PM PDT 24 |
1452556225 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2306675298 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:01 PM PDT 24 |
36599941 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3961742168 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:02 PM PDT 24 |
35576568 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4109847584 |
|
|
Jul 25 06:36:04 PM PDT 24 |
Jul 25 06:36:05 PM PDT 24 |
22337102 ps |
| T978 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1964423142 |
|
|
Jul 25 06:36:14 PM PDT 24 |
Jul 25 06:36:14 PM PDT 24 |
45413467 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.25027654 |
|
|
Jul 25 06:36:00 PM PDT 24 |
Jul 25 06:36:01 PM PDT 24 |
46781013 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1876480229 |
|
|
Jul 25 06:36:02 PM PDT 24 |
Jul 25 06:36:03 PM PDT 24 |
57239792 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2306173548 |
|
|
Jul 25 06:36:26 PM PDT 24 |
Jul 25 06:36:31 PM PDT 24 |
411893215 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.56247724 |
|
|
Jul 25 06:35:59 PM PDT 24 |
Jul 25 06:36:01 PM PDT 24 |
86101440 ps |
| T983 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.809244572 |
|
|
Jul 25 06:35:59 PM PDT 24 |
Jul 25 06:35:59 PM PDT 24 |
18142649 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2379683903 |
|
|
Jul 25 06:36:02 PM PDT 24 |
Jul 25 06:36:07 PM PDT 24 |
280067870 ps |
| T129 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4215995903 |
|
|
Jul 25 06:36:01 PM PDT 24 |
Jul 25 06:36:04 PM PDT 24 |
336455240 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1791136812 |
|
|
Jul 25 06:36:11 PM PDT 24 |
Jul 25 06:36:12 PM PDT 24 |
16139705 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2854063510 |
|
|
Jul 25 06:36:16 PM PDT 24 |
Jul 25 06:36:17 PM PDT 24 |
20764080 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.354029466 |
|
|
Jul 25 06:36:32 PM PDT 24 |
Jul 25 06:36:34 PM PDT 24 |
79902229 ps |
| T94 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3747515649 |
|
|
Jul 25 06:36:18 PM PDT 24 |
Jul 25 06:36:19 PM PDT 24 |
68820905 ps |
| T988 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1266675424 |
|
|
Jul 25 06:36:25 PM PDT 24 |
Jul 25 06:36:27 PM PDT 24 |
63995936 ps |
| T989 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3808452795 |
|
|
Jul 25 06:36:19 PM PDT 24 |
Jul 25 06:36:20 PM PDT 24 |
38490784 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4075583704 |
|
|
Jul 25 06:36:25 PM PDT 24 |
Jul 25 06:36:26 PM PDT 24 |
28970410 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3753129816 |
|
|
Jul 25 06:36:14 PM PDT 24 |
Jul 25 06:36:17 PM PDT 24 |
822994351 ps |
| T992 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2141603663 |
|
|
Jul 25 06:36:24 PM PDT 24 |
Jul 25 06:36:25 PM PDT 24 |
14996915 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4132582575 |
|
|
Jul 25 06:36:09 PM PDT 24 |
Jul 25 06:36:11 PM PDT 24 |
33301642 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2598505799 |
|
|
Jul 25 06:36:29 PM PDT 24 |
Jul 25 06:36:30 PM PDT 24 |
81072580 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3502619956 |
|
|
Jul 25 06:36:03 PM PDT 24 |
Jul 25 06:36:04 PM PDT 24 |
27857351 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1431795501 |
|
|
Jul 25 06:36:11 PM PDT 24 |
Jul 25 06:36:15 PM PDT 24 |
627529135 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.800824249 |
|
|
Jul 25 06:36:21 PM PDT 24 |
Jul 25 06:36:24 PM PDT 24 |
287618080 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4063957456 |
|
|
Jul 25 06:36:26 PM PDT 24 |
Jul 25 06:36:30 PM PDT 24 |
87661635 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1979322162 |
|
|
Jul 25 06:36:28 PM PDT 24 |
Jul 25 06:36:31 PM PDT 24 |
492447169 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3654768867 |
|
|
Jul 25 06:36:27 PM PDT 24 |
Jul 25 06:36:28 PM PDT 24 |
19310890 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3655769569 |
|
|
Jul 25 06:36:26 PM PDT 24 |
Jul 25 06:36:29 PM PDT 24 |
409300651 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3161587674 |
|
|
Jul 25 06:36:14 PM PDT 24 |
Jul 25 06:36:16 PM PDT 24 |
143447269 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2835461175 |
|
|
Jul 25 06:36:31 PM PDT 24 |
Jul 25 06:36:36 PM PDT 24 |
1044176257 ps |