Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149537362	1			T1	303266		T2	15376		T3	8590
instr_valid_dis	115076002	1			T1	303266		T2	15376		T3	8590
instr_en	22195551	1			T4	155244		T11	105640		T43	255208

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11225208	1			T4	39814		T11	104164		T43	18056
sram_ifetch_valid_disable	116804848	1			T1	303266		T2	15376		T3	8590
sram_ifetch_enable	21507306	1			T4	231994		T11	167128		T18	33748

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149537362	1			T1	303266		T2	15376		T3	8590
hw_debug_en_valid_off	115627143	1			T1	303266		T2	15376		T3	8590
hw_debug_en_on	22690827	1			T4	175366		T11	199554		T43	154816

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116804848	1			T1	303266		T2	15376		T3	8590
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102517516	1			T1	303266		T2	15376		T3	8590
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9125527	1			T4	64394		T11	32428		T43	194804
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4548756	1			T11	72508		T57	61438		T61	75516
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1725888	1			T11	58882		T57	61438		T61	13926
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1748784	1			T85	20574		T30	134956		T151	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4679188	1			T57	18332		T146	29612		T69	31532
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1771342	1			T146	29612		T69	31532		T30	46104
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1724716	1			T152	3044		T143	17132		T20	30172
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8853343	1			T4	97400		T11	102262		T43	56986
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3840698	1			T4	45764		T11	70884		T43	14818
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3538447	1			T4	51566		T11	21170		T43	42168

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8660638	1			T4	70850		T11	73212		T43	42348
lc_exec_en	9158296	1			T4	77966		T11	97292		T43	97830
valid_exec_dis	110782687	1			T1	303266		T2	15376		T3	8590
invalid_exec_dis	32732514	1			T4	271808		T11	271292		T18	33748