Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total tests in report: 1031

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
72.11	72.11	91.36	91.36	73.93	73.93	92.16	92.16	23.81	23.81	80.92	80.92	93.22	93.22	49.36	49.36	/workspace/coverage/default/4.sram_ctrl_executable.3013188231
88.95	16.84	97.12	5.76	80.92	6.99	92.79	0.62	90.48	66.67	88.89	7.97	95.13	1.92	77.33	27.97	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1857974137
92.48	3.53	98.31	1.19	85.07	4.15	95.25	2.46	100.00	9.52	92.51	3.62	95.43	0.29	80.80	3.47	/workspace/coverage/default/1.sram_ctrl_lc_escalation.4143888055
94.27	1.79	98.73	0.42	87.91	2.84	97.71	2.46	100.00	0.00	94.20	1.69	95.43	0.00	85.92	5.12	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1516293640
95.25	0.98	98.90	0.17	88.74	0.83	97.92	0.21	100.00	0.00	94.93	0.72	95.43	0.00	90.86	4.94	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3760644186
95.96	0.71	99.07	0.17	90.52	1.78	98.68	0.76	100.00	0.00	95.65	0.72	96.02	0.59	91.77	0.91	/workspace/coverage/default/4.sram_ctrl_sec_cm.2451173319
96.24	0.28	99.07	0.00	90.52	0.00	98.68	0.00	100.00	0.00	95.65	0.00	96.17	0.15	93.60	1.83	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2836097693
96.43	0.19	99.07	0.00	90.64	0.12	98.68	0.00	100.00	0.00	96.14	0.48	96.90	0.74	93.60	0.00	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2963946859
96.62	0.19	99.07	0.00	90.64	0.00	98.68	0.00	100.00	0.00	96.14	0.00	98.23	1.33	93.60	0.00	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.399794584
96.79	0.17	99.07	0.00	90.64	0.00	98.75	0.07	100.00	0.00	96.14	0.00	98.23	0.00	94.70	1.10	/workspace/coverage/default/0.sram_ctrl_stress_all.979311745
96.94	0.15	99.07	0.00	90.64	0.00	98.75	0.00	100.00	0.00	96.14	0.00	99.12	0.88	94.88	0.18	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1648961236
97.07	0.13	99.15	0.08	90.64	0.00	99.58	0.83	100.00	0.00	96.14	0.00	99.12	0.00	94.88	0.00	/workspace/coverage/default/20.sram_ctrl_ram_cfg.1845404010
97.16	0.09	99.15	0.00	91.00	0.36	99.65	0.07	100.00	0.00	96.14	0.00	99.12	0.00	95.06	0.18	/workspace/coverage/default/27.sram_ctrl_alert_test.2298534613
97.24	0.08	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	95.61	0.55	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1351101623
97.32	0.08	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	96.16	0.55	/workspace/coverage/default/19.sram_ctrl_executable.2289596707
97.37	0.05	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	96.53	0.37	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3083919685
97.39	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	96.71	0.18	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3133804454
97.42	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	96.89	0.18	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.893615654
97.45	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.07	0.18	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1458377069
97.47	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.26	0.18	/workspace/coverage/default/0.sram_ctrl_executable.1233014153
97.50	0.03	99.15	0.00	91.00	0.00	99.65	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.44	0.18	/workspace/coverage/default/16.sram_ctrl_regwen.4240163505
97.51	0.01	99.15	0.00	91.00	0.00	99.72	0.07	100.00	0.00	96.14	0.00	99.12	0.00	97.44	0.00	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.584555831

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1930653062
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1908322113
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2470963217
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3749241884
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2375854839
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1604343609
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3349394738
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3184906001
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2345892595
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2405315577
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.458006904
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1390872437
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1832342064
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.813090157
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3827622920
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2221121073
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2010994307
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2019500914
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2351387082
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3356305395
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1609946952
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2772099345
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1820225115
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.804310788
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4059321726
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1144054325
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3126576799
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.112642795
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4213017745
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4092195425
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3449168553
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3527580293
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1440587500
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1759204229
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1858817497
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1552174635
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2902898539
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1567666534
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.76827375
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1649173552
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3505634100
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1234557994
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3771018787
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.44248725
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.299046684
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.553136338
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2288176191
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2740420603
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1440776745
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4120908580
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2467169272
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1841256728
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3466540248
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1635722405
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2484684085
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.993666499
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3940767466
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3740948823
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.837580948
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1903922501
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.568167084
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3219956500
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.88566739
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3588259710
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.874407835
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.256131889
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2871955879
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1254067441
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1727245677
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4096212110
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.843294572
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4211752607
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1140957437
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3682315355
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1656195848
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4083603602
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2052622389
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2628930521
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.435819044
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1055796573
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2871619546
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1950587012
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.781751994
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3133055807
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.173654263
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3057088290
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.787727900
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.356121524
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.143601987
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3388806007
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1957754854
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.158351721
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.483647946
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3002684601
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.866827959
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1718895940
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.449269419
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3507512649
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.718488368
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3825843448
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1842841470
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3138815589
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3436111933
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1476968890
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4173299407
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3039358435
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3266865057
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2318387232
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1064534468
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.920357450
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2557785114
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3178187392
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3199196796
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.730946368
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2797630225
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2000430326
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2178760970
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2741976264
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2726127254
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1389484237
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2924231502
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3432808006
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3928549897
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.81465331
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2127656300
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1343109081
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1045100839
/workspace/coverage/default/0.sram_ctrl_alert_test.1227234190
/workspace/coverage/default/0.sram_ctrl_bijection.1141640962
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3537427081
/workspace/coverage/default/0.sram_ctrl_max_throughput.437329026
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3029008529
/workspace/coverage/default/0.sram_ctrl_mem_walk.2227957673
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3929912246
/workspace/coverage/default/0.sram_ctrl_partial_access.2161578693
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2658322695
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3449705783
/workspace/coverage/default/0.sram_ctrl_regwen.3019330086
/workspace/coverage/default/0.sram_ctrl_sec_cm.3970540084
/workspace/coverage/default/0.sram_ctrl_smoke.1035493212
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1783291309
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1780524316
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1427100232
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2937333087
/workspace/coverage/default/1.sram_ctrl_alert_test.2934904723
/workspace/coverage/default/1.sram_ctrl_bijection.970851198
/workspace/coverage/default/1.sram_ctrl_executable.2833230464
/workspace/coverage/default/1.sram_ctrl_max_throughput.4024472683
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.51759798
/workspace/coverage/default/1.sram_ctrl_mem_walk.1344406186
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2812317525
/workspace/coverage/default/1.sram_ctrl_partial_access.3128616874
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3089649635
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4098921190
/workspace/coverage/default/1.sram_ctrl_regwen.1978334279
/workspace/coverage/default/1.sram_ctrl_sec_cm.3380479497
/workspace/coverage/default/1.sram_ctrl_smoke.384367273
/workspace/coverage/default/1.sram_ctrl_stress_all.1181212482
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2884046549
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3050877045
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2688495727
/workspace/coverage/default/10.sram_ctrl_alert_test.2860465647
/workspace/coverage/default/10.sram_ctrl_bijection.762347556
/workspace/coverage/default/10.sram_ctrl_executable.1524101279
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1815066021
/workspace/coverage/default/10.sram_ctrl_max_throughput.4077112454
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2618540449
/workspace/coverage/default/10.sram_ctrl_mem_walk.622764062
/workspace/coverage/default/10.sram_ctrl_multiple_keys.167736507
/workspace/coverage/default/10.sram_ctrl_partial_access.3310011213
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3246258963
/workspace/coverage/default/10.sram_ctrl_ram_cfg.119542965
/workspace/coverage/default/10.sram_ctrl_regwen.611662093
/workspace/coverage/default/10.sram_ctrl_smoke.1189118913
/workspace/coverage/default/10.sram_ctrl_stress_all.1562652291
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1937360652
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.201084121
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3994450738
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.411243989
/workspace/coverage/default/11.sram_ctrl_alert_test.869362023
/workspace/coverage/default/11.sram_ctrl_bijection.1494456380
/workspace/coverage/default/11.sram_ctrl_executable.1786756690
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3823931352
/workspace/coverage/default/11.sram_ctrl_max_throughput.1336402553
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/workspace/coverage/default/42.sram_ctrl_alert_test.942884766
/workspace/coverage/default/42.sram_ctrl_bijection.1170753418
/workspace/coverage/default/42.sram_ctrl_executable.3962545419
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1885967602
/workspace/coverage/default/42.sram_ctrl_max_throughput.2431065050
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1455873950
/workspace/coverage/default/42.sram_ctrl_mem_walk.933689853
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2500460786
/workspace/coverage/default/42.sram_ctrl_partial_access.580003936
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.57187028
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1507649858
/workspace/coverage/default/42.sram_ctrl_regwen.3398750985
/workspace/coverage/default/42.sram_ctrl_smoke.1669563105
/workspace/coverage/default/42.sram_ctrl_stress_all.2365100084
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.830879709
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2998843800
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1093888229
/workspace/coverage/default/43.sram_ctrl_alert_test.4242355897
/workspace/coverage/default/43.sram_ctrl_bijection.863576517
/workspace/coverage/default/43.sram_ctrl_executable.1070581188
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1077673067
/workspace/coverage/default/43.sram_ctrl_max_throughput.3492211993
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2221041873
/workspace/coverage/default/43.sram_ctrl_mem_walk.4111567472
/workspace/coverage/default/43.sram_ctrl_multiple_keys.857684240
/workspace/coverage/default/43.sram_ctrl_partial_access.784935492
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1090884116
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2444657950
/workspace/coverage/default/43.sram_ctrl_regwen.722302951
/workspace/coverage/default/43.sram_ctrl_smoke.1161832805
/workspace/coverage/default/43.sram_ctrl_stress_all.4133043353
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2055305273
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3729288745
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3148840480
/workspace/coverage/default/44.sram_ctrl_alert_test.946330392
/workspace/coverage/default/44.sram_ctrl_bijection.2794556180
/workspace/coverage/default/44.sram_ctrl_executable.442419375
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1237079378
/workspace/coverage/default/44.sram_ctrl_max_throughput.115820664
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4272172592
/workspace/coverage/default/44.sram_ctrl_mem_walk.795127672
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3660737560
/workspace/coverage/default/44.sram_ctrl_partial_access.3285434834
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3923643736
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2133037490
/workspace/coverage/default/44.sram_ctrl_regwen.1154930473
/workspace/coverage/default/44.sram_ctrl_smoke.2600483690
/workspace/coverage/default/44.sram_ctrl_stress_all.3044119378
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1693129151
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1977214064
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3640067225
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.731617665
/workspace/coverage/default/45.sram_ctrl_alert_test.41321879
/workspace/coverage/default/45.sram_ctrl_bijection.3536765793
/workspace/coverage/default/45.sram_ctrl_executable.1196514920
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2597648051
/workspace/coverage/default/45.sram_ctrl_max_throughput.4087485038
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1188961631
/workspace/coverage/default/45.sram_ctrl_mem_walk.3492488896
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3070496241
/workspace/coverage/default/45.sram_ctrl_partial_access.590526371
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.771614465
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2212916605
/workspace/coverage/default/45.sram_ctrl_regwen.3419790540
/workspace/coverage/default/45.sram_ctrl_smoke.3529539554
/workspace/coverage/default/45.sram_ctrl_stress_all.224125803
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.396278329
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2721160694
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3780165909
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.823502463
/workspace/coverage/default/46.sram_ctrl_alert_test.1251618097
/workspace/coverage/default/46.sram_ctrl_bijection.2362101869
/workspace/coverage/default/46.sram_ctrl_executable.2767571569
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1844260292
/workspace/coverage/default/46.sram_ctrl_max_throughput.2364124114
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3157074391
/workspace/coverage/default/46.sram_ctrl_mem_walk.2893845940
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3244454855
/workspace/coverage/default/46.sram_ctrl_partial_access.1112759673
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1301938365
/workspace/coverage/default/46.sram_ctrl_ram_cfg.47103744
/workspace/coverage/default/46.sram_ctrl_regwen.1779085140
/workspace/coverage/default/46.sram_ctrl_smoke.703576305
/workspace/coverage/default/46.sram_ctrl_stress_all.794680224
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.319825550
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1449365904
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2636086223
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3121104987
/workspace/coverage/default/47.sram_ctrl_alert_test.2800114238
/workspace/coverage/default/47.sram_ctrl_bijection.2645166363
/workspace/coverage/default/47.sram_ctrl_executable.4115688460
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2644544436
/workspace/coverage/default/47.sram_ctrl_max_throughput.1667086084
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3240634233
/workspace/coverage/default/47.sram_ctrl_mem_walk.1676171841
/workspace/coverage/default/47.sram_ctrl_multiple_keys.450376706
/workspace/coverage/default/47.sram_ctrl_partial_access.3890292520
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1562311604
/workspace/coverage/default/47.sram_ctrl_ram_cfg.4113436596
/workspace/coverage/default/47.sram_ctrl_regwen.1023352251
/workspace/coverage/default/47.sram_ctrl_smoke.3668616182
/workspace/coverage/default/47.sram_ctrl_stress_all.912587580
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2561125416
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.776064622
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4067734406
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3889072150
/workspace/coverage/default/48.sram_ctrl_alert_test.3924747909
/workspace/coverage/default/48.sram_ctrl_bijection.3344747118
/workspace/coverage/default/48.sram_ctrl_executable.4117890814
/workspace/coverage/default/48.sram_ctrl_lc_escalation.757732446
/workspace/coverage/default/48.sram_ctrl_max_throughput.2469930123
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1288532121
/workspace/coverage/default/48.sram_ctrl_mem_walk.1124520418
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1392817318
/workspace/coverage/default/48.sram_ctrl_partial_access.4096818756
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1908989028
/workspace/coverage/default/48.sram_ctrl_ram_cfg.486479233
/workspace/coverage/default/48.sram_ctrl_regwen.1244417658
/workspace/coverage/default/48.sram_ctrl_smoke.872624090
/workspace/coverage/default/48.sram_ctrl_stress_all.928094553
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1744217644
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3712177250
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1400726040
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2132475039
/workspace/coverage/default/49.sram_ctrl_alert_test.175943802
/workspace/coverage/default/49.sram_ctrl_bijection.361844131
/workspace/coverage/default/49.sram_ctrl_executable.3633358946
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2890294140
/workspace/coverage/default/49.sram_ctrl_max_throughput.2809495175
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3106785748
/workspace/coverage/default/49.sram_ctrl_mem_walk.864895826
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1022650097
/workspace/coverage/default/49.sram_ctrl_partial_access.842147198
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2598312082
/workspace/coverage/default/49.sram_ctrl_regwen.102316033
/workspace/coverage/default/49.sram_ctrl_smoke.1415426919
/workspace/coverage/default/49.sram_ctrl_stress_all.465716188
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2336039570
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2936363722
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.917648687
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.533105718
/workspace/coverage/default/5.sram_ctrl_alert_test.650778039
/workspace/coverage/default/5.sram_ctrl_bijection.1542892863
/workspace/coverage/default/5.sram_ctrl_executable.1192730495
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2716123669
/workspace/coverage/default/5.sram_ctrl_max_throughput.3827407611
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.597836389
/workspace/coverage/default/5.sram_ctrl_mem_walk.3918760911
/workspace/coverage/default/5.sram_ctrl_multiple_keys.84679942
/workspace/coverage/default/5.sram_ctrl_partial_access.3101784497
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1271153183
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3170351492
/workspace/coverage/default/5.sram_ctrl_regwen.3716088354
/workspace/coverage/default/5.sram_ctrl_smoke.3940387895
/workspace/coverage/default/5.sram_ctrl_stress_all.2874607617
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1993259554
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2740352994
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.272961765
/workspace/coverage/default/6.sram_ctrl_alert_test.1418595217
/workspace/coverage/default/6.sram_ctrl_bijection.1811254704
/workspace/coverage/default/6.sram_ctrl_executable.2321327583
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2354859927
/workspace/coverage/default/6.sram_ctrl_max_throughput.3668848002
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1318488652
/workspace/coverage/default/6.sram_ctrl_mem_walk.734174335
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3884263451
/workspace/coverage/default/6.sram_ctrl_partial_access.4231269373
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1018449081
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3648314109
/workspace/coverage/default/6.sram_ctrl_regwen.2874825584
/workspace/coverage/default/6.sram_ctrl_smoke.1573044386
/workspace/coverage/default/6.sram_ctrl_stress_all.4274811123
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3697037789
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1074531632
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4190386293
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3514082620
/workspace/coverage/default/7.sram_ctrl_alert_test.413101538
/workspace/coverage/default/7.sram_ctrl_bijection.938141761
/workspace/coverage/default/7.sram_ctrl_executable.1151037509
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3145147173
/workspace/coverage/default/7.sram_ctrl_max_throughput.2896791918
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3838063487
/workspace/coverage/default/7.sram_ctrl_mem_walk.2339529717
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1090722477
/workspace/coverage/default/7.sram_ctrl_partial_access.3038881267
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3061426478
/workspace/coverage/default/7.sram_ctrl_ram_cfg.973282825
/workspace/coverage/default/7.sram_ctrl_regwen.2977829256
/workspace/coverage/default/7.sram_ctrl_smoke.2450247106
/workspace/coverage/default/7.sram_ctrl_stress_all.264016332
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2759636508
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3450121145
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.66685328
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3924680729
/workspace/coverage/default/8.sram_ctrl_alert_test.1403140517
/workspace/coverage/default/8.sram_ctrl_bijection.3681749657
/workspace/coverage/default/8.sram_ctrl_executable.3305893061
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3679006961
/workspace/coverage/default/8.sram_ctrl_max_throughput.2938784260
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2741047498
/workspace/coverage/default/8.sram_ctrl_mem_walk.3690838116
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3084795870
/workspace/coverage/default/8.sram_ctrl_partial_access.2107072851
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2012080658
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2002502268
/workspace/coverage/default/8.sram_ctrl_regwen.1884913559
/workspace/coverage/default/8.sram_ctrl_smoke.4196453632
/workspace/coverage/default/8.sram_ctrl_stress_all.3026387440
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.534510353
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3496641644
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2928424323
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1576803508
/workspace/coverage/default/9.sram_ctrl_alert_test.2645000276
/workspace/coverage/default/9.sram_ctrl_bijection.917550045
/workspace/coverage/default/9.sram_ctrl_executable.78292265
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3278910304
/workspace/coverage/default/9.sram_ctrl_max_throughput.3542418844
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.620719785
/workspace/coverage/default/9.sram_ctrl_mem_walk.655669028
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3287985711
/workspace/coverage/default/9.sram_ctrl_partial_access.730735695
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3703712251
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1600973695
/workspace/coverage/default/9.sram_ctrl_regwen.1362249767
/workspace/coverage/default/9.sram_ctrl_smoke.494944499
/workspace/coverage/default/9.sram_ctrl_stress_all.2660917584
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.622716721
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2618907577
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.244981606

Total test records in report: 1031

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2223794794	Jul 26 07:16:29 PM PDT 24	Jul 26 07:19:27 PM PDT 24	3636777901 ps
T2	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1884891936	Jul 26 07:11:35 PM PDT 24	Jul 26 07:12:32 PM PDT 24	247350602 ps
T3	/workspace/coverage/default/10.sram_ctrl_max_throughput.4077112454	Jul 26 07:11:22 PM PDT 24	Jul 26 07:11:44 PM PDT 24	166246209 ps
T10	/workspace/coverage/default/49.sram_ctrl_ram_cfg.2598312082	Jul 26 07:18:17 PM PDT 24	Jul 26 07:18:18 PM PDT 24	84123385 ps
T4	/workspace/coverage/default/3.sram_ctrl_executable.558581471	Jul 26 07:11:04 PM PDT 24	Jul 26 07:33:23 PM PDT 24	175194811631 ps
T5	/workspace/coverage/default/42.sram_ctrl_max_throughput.2431065050	Jul 26 07:16:52 PM PDT 24	Jul 26 07:17:15 PM PDT 24	401238586 ps
T7	/workspace/coverage/default/33.sram_ctrl_lc_escalation.3044575712	Jul 26 07:14:57 PM PDT 24	Jul 26 07:15:03 PM PDT 24	495817157 ps
T6	/workspace/coverage/default/23.sram_ctrl_smoke.2887685215	Jul 26 07:13:11 PM PDT 24	Jul 26 07:13:25 PM PDT 24	5645149404 ps
T11	/workspace/coverage/default/4.sram_ctrl_executable.3013188231	Jul 26 07:11:03 PM PDT 24	Jul 26 07:39:31 PM PDT 24	68219081498 ps
T12	/workspace/coverage/default/29.sram_ctrl_alert_test.605665713	Jul 26 07:14:25 PM PDT 24	Jul 26 07:14:26 PM PDT 24	60568330 ps
T8	/workspace/coverage/default/32.sram_ctrl_lc_escalation.798654551	Jul 26 07:14:56 PM PDT 24	Jul 26 07:15:00 PM PDT 24	455886400 ps
T38	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2998843800	Jul 26 07:16:52 PM PDT 24	Jul 26 07:16:57 PM PDT 24	217726044 ps
T9	/workspace/coverage/default/1.sram_ctrl_lc_escalation.4143888055	Jul 26 07:10:36 PM PDT 24	Jul 26 07:10:46 PM PDT 24	1126690692 ps
T39	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2430558304	Jul 26 07:11:21 PM PDT 24	Jul 26 07:15:08 PM PDT 24	2466456826 ps
T40	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1648961236	Jul 26 07:12:12 PM PDT 24	Jul 26 07:34:04 PM PDT 24	4033483778 ps
T22	/workspace/coverage/default/21.sram_ctrl_bijection.2827909950	Jul 26 07:12:51 PM PDT 24	Jul 26 07:13:11 PM PDT 24	897891482 ps
T70	/workspace/coverage/default/31.sram_ctrl_bijection.1367007219	Jul 26 07:14:41 PM PDT 24	Jul 26 07:15:58 PM PDT 24	3592174293 ps
T18	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1516293640	Jul 26 07:12:59 PM PDT 24	Jul 26 07:23:42 PM PDT 24	1106715744 ps
T43	/workspace/coverage/default/18.sram_ctrl_executable.1396017946	Jul 26 07:12:29 PM PDT 24	Jul 26 07:38:14 PM PDT 24	31696030087 ps
T78	/workspace/coverage/default/3.sram_ctrl_bijection.3693466151	Jul 26 07:10:44 PM PDT 24	Jul 26 07:11:55 PM PDT 24	15694435571 ps
T25	/workspace/coverage/default/43.sram_ctrl_ram_cfg.2444657950	Jul 26 07:17:00 PM PDT 24	Jul 26 07:17:01 PM PDT 24	86062873 ps
T79	/workspace/coverage/default/47.sram_ctrl_bijection.2645166363	Jul 26 07:17:59 PM PDT 24	Jul 26 07:18:25 PM PDT 24	415742147 ps
T80	/workspace/coverage/default/49.sram_ctrl_partial_access.842147198	Jul 26 07:18:16 PM PDT 24	Jul 26 07:18:18 PM PDT 24	48895080 ps
T81	/workspace/coverage/default/5.sram_ctrl_multiple_keys.84679942	Jul 26 07:10:56 PM PDT 24	Jul 26 07:19:11 PM PDT 24	2678261037 ps
T82	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.776064622	Jul 26 07:18:00 PM PDT 24	Jul 26 07:20:12 PM PDT 24	4237827228 ps
T83	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.79355360	Jul 26 07:10:57 PM PDT 24	Jul 26 07:12:02 PM PDT 24	149216893 ps
T84	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2884046549	Jul 26 07:10:31 PM PDT 24	Jul 26 07:14:39 PM PDT 24	2687977309 ps
T71	/workspace/coverage/default/8.sram_ctrl_partial_access.2107072851	Jul 26 07:11:09 PM PDT 24	Jul 26 07:11:19 PM PDT 24	729871675 ps
T96	/workspace/coverage/default/38.sram_ctrl_multiple_keys.1127041351	Jul 26 07:15:59 PM PDT 24	Jul 26 07:32:42 PM PDT 24	105840140338 ps
T158	/workspace/coverage/default/26.sram_ctrl_partial_access.4210537711	Jul 26 07:13:48 PM PDT 24	Jul 26 07:14:08 PM PDT 24	3891937629 ps
T21	/workspace/coverage/default/45.sram_ctrl_lc_escalation.2597648051	Jul 26 07:17:31 PM PDT 24	Jul 26 07:17:38 PM PDT 24	2539866867 ps
T150	/workspace/coverage/default/33.sram_ctrl_multiple_keys.3389372301	Jul 26 07:15:00 PM PDT 24	Jul 26 07:31:56 PM PDT 24	42008055043 ps
T149	/workspace/coverage/default/4.sram_ctrl_partial_access.1230175657	Jul 26 07:10:56 PM PDT 24	Jul 26 07:11:15 PM PDT 24	306437283 ps
T156	/workspace/coverage/default/11.sram_ctrl_smoke.1491890219	Jul 26 07:11:21 PM PDT 24	Jul 26 07:11:32 PM PDT 24	173732222 ps
T44	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2549743611	Jul 26 07:16:14 PM PDT 24	Jul 26 07:16:18 PM PDT 24	553252302 ps
T26	/workspace/coverage/default/9.sram_ctrl_ram_cfg.1600973695	Jul 26 07:11:28 PM PDT 24	Jul 26 07:11:29 PM PDT 24	69874234 ps
T55	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2836097693	Jul 26 07:18:17 PM PDT 24	Jul 26 07:23:26 PM PDT 24	25672791314 ps
T56	/workspace/coverage/default/42.sram_ctrl_lc_escalation.1885967602	Jul 26 07:16:53 PM PDT 24	Jul 26 07:17:00 PM PDT 24	477759678 ps
T57	/workspace/coverage/default/31.sram_ctrl_executable.1541503676	Jul 26 07:14:34 PM PDT 24	Jul 26 07:21:38 PM PDT 24	28235053381 ps
T58	/workspace/coverage/default/36.sram_ctrl_smoke.587472110	Jul 26 07:15:40 PM PDT 24	Jul 26 07:15:53 PM PDT 24	404849081 ps
T59	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3645912362	Jul 26 07:15:57 PM PDT 24	Jul 26 07:23:25 PM PDT 24	6156365820 ps
T41	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1364536069	Jul 26 07:15:07 PM PDT 24	Jul 26 07:16:07 PM PDT 24	4504967985 ps
T60	/workspace/coverage/default/38.sram_ctrl_lc_escalation.3248276353	Jul 26 07:15:59 PM PDT 24	Jul 26 07:16:10 PM PDT 24	912484231 ps
T61	/workspace/coverage/default/34.sram_ctrl_executable.19792751	Jul 26 07:15:20 PM PDT 24	Jul 26 07:35:29 PM PDT 24	20594188793 ps
T159	/workspace/coverage/default/16.sram_ctrl_max_throughput.3036311580	Jul 26 07:12:09 PM PDT 24	Jul 26 07:14:12 PM PDT 24	138580133 ps
T42	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3514082620	Jul 26 07:11:10 PM PDT 24	Jul 26 07:19:00 PM PDT 24	1576939938 ps
T113	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3246258963	Jul 26 07:11:29 PM PDT 24	Jul 26 07:19:09 PM PDT 24	68612047346 ps
T114	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.433962722	Jul 26 07:15:39 PM PDT 24	Jul 26 07:17:36 PM PDT 24	1284802825 ps
T23	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2319722314	Jul 26 07:10:58 PM PDT 24	Jul 26 07:11:27 PM PDT 24	948277474 ps
T74	/workspace/coverage/default/39.sram_ctrl_lc_escalation.3116277665	Jul 26 07:16:18 PM PDT 24	Jul 26 07:16:21 PM PDT 24	575812777 ps
T146	/workspace/coverage/default/47.sram_ctrl_executable.4115688460	Jul 26 07:18:02 PM PDT 24	Jul 26 07:26:53 PM PDT 24	13648604620 ps
T13	/workspace/coverage/default/27.sram_ctrl_alert_test.2298534613	Jul 26 07:14:01 PM PDT 24	Jul 26 07:14:02 PM PDT 24	111921191 ps
T14	/workspace/coverage/default/6.sram_ctrl_alert_test.1418595217	Jul 26 07:11:10 PM PDT 24	Jul 26 07:11:11 PM PDT 24	15995562 ps
T69	/workspace/coverage/default/40.sram_ctrl_regwen.3463772085	Jul 26 07:16:35 PM PDT 24	Jul 26 07:30:31 PM PDT 24	9184347297 ps
T45	/workspace/coverage/default/44.sram_ctrl_mem_walk.795127672	Jul 26 07:17:23 PM PDT 24	Jul 26 07:17:33 PM PDT 24	176339895 ps
T85	/workspace/coverage/default/37.sram_ctrl_stress_all.2611378709	Jul 26 07:15:49 PM PDT 24	Jul 26 07:33:53 PM PDT 24	83360817881 ps
T86	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2354859927	Jul 26 07:11:10 PM PDT 24	Jul 26 07:11:15 PM PDT 24	1776736696 ps
T129	/workspace/coverage/default/49.sram_ctrl_lc_escalation.2890294140	Jul 26 07:18:16 PM PDT 24	Jul 26 07:18:20 PM PDT 24	719056584 ps
T115	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.4136817857	Jul 26 07:12:51 PM PDT 24	Jul 26 07:18:51 PM PDT 24	13335510398 ps
T160	/workspace/coverage/default/35.sram_ctrl_ram_cfg.978150751	Jul 26 07:15:25 PM PDT 24	Jul 26 07:15:26 PM PDT 24	38833817 ps
T52	/workspace/coverage/default/30.sram_ctrl_mem_walk.1898997423	Jul 26 07:14:34 PM PDT 24	Jul 26 07:14:44 PM PDT 24	713118896 ps
T161	/workspace/coverage/default/15.sram_ctrl_lc_escalation.1242254542	Jul 26 07:12:00 PM PDT 24	Jul 26 07:12:08 PM PDT 24	2231178522 ps
T162	/workspace/coverage/default/49.sram_ctrl_bijection.361844131	Jul 26 07:18:14 PM PDT 24	Jul 26 07:19:12 PM PDT 24	1504225631 ps
T154	/workspace/coverage/default/22.sram_ctrl_lc_escalation.3630606540	Jul 26 07:13:02 PM PDT 24	Jul 26 07:13:10 PM PDT 24	1337076064 ps
T100	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2892219035	Jul 26 07:10:58 PM PDT 24	Jul 26 07:11:57 PM PDT 24	1706241928 ps
T116	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1449365904	Jul 26 07:17:37 PM PDT 24	Jul 26 07:22:06 PM PDT 24	6037656764 ps
T153	/workspace/coverage/default/2.sram_ctrl_lc_escalation.833244048	Jul 26 07:10:43 PM PDT 24	Jul 26 07:10:50 PM PDT 24	2102448137 ps
T163	/workspace/coverage/default/31.sram_ctrl_max_throughput.1354912977	Jul 26 07:14:41 PM PDT 24	Jul 26 07:17:06 PM PDT 24	547058463 ps
T101	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2378480531	Jul 26 07:15:21 PM PDT 24	Jul 26 07:21:53 PM PDT 24	2437523421 ps
T164	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3076834570	Jul 26 07:15:16 PM PDT 24	Jul 26 07:15:18 PM PDT 24	192951299 ps
T165	/workspace/coverage/default/33.sram_ctrl_smoke.857905804	Jul 26 07:14:58 PM PDT 24	Jul 26 07:15:00 PM PDT 24	107593676 ps
T166	/workspace/coverage/default/14.sram_ctrl_executable.2364056824	Jul 26 07:12:00 PM PDT 24	Jul 26 07:13:52 PM PDT 24	345379050 ps
T102	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.968277356	Jul 26 07:16:41 PM PDT 24	Jul 26 07:16:44 PM PDT 24	169165233 ps
T155	/workspace/coverage/default/38.sram_ctrl_bijection.2094253397	Jul 26 07:15:59 PM PDT 24	Jul 26 07:16:49 PM PDT 24	766320177 ps
T152	/workspace/coverage/default/8.sram_ctrl_executable.3305893061	Jul 26 07:11:13 PM PDT 24	Jul 26 07:11:20 PM PDT 24	152775371 ps
T167	/workspace/coverage/default/47.sram_ctrl_smoke.3668616182	Jul 26 07:17:48 PM PDT 24	Jul 26 07:17:54 PM PDT 24	88357222 ps
T157	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1977214064	Jul 26 07:17:19 PM PDT 24	Jul 26 07:20:50 PM PDT 24	4310633461 ps
T143	/workspace/coverage/default/19.sram_ctrl_executable.2289596707	Jul 26 07:12:38 PM PDT 24	Jul 26 07:25:39 PM PDT 24	8442906852 ps
T148	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.537129060	Jul 26 07:14:37 PM PDT 24	Jul 26 07:22:28 PM PDT 24	71763335125 ps
T168	/workspace/coverage/default/24.sram_ctrl_ram_cfg.3795451893	Jul 26 07:13:35 PM PDT 24	Jul 26 07:13:36 PM PDT 24	29245701 ps
T103	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1817214776	Jul 26 07:15:40 PM PDT 24	Jul 26 07:15:44 PM PDT 24	62451131 ps
T169	/workspace/coverage/default/47.sram_ctrl_multiple_keys.450376706	Jul 26 07:17:49 PM PDT 24	Jul 26 07:44:31 PM PDT 24	14407969208 ps
T170	/workspace/coverage/default/4.sram_ctrl_alert_test.1526067670	Jul 26 07:10:55 PM PDT 24	Jul 26 07:10:56 PM PDT 24	55902337 ps
T171	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.102054689	Jul 26 07:13:49 PM PDT 24	Jul 26 07:14:21 PM PDT 24	108276726 ps
T24	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.966534775	Jul 26 07:14:47 PM PDT 24	Jul 26 07:14:54 PM PDT 24	843411207 ps
T19	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1540556852	Jul 26 07:16:22 PM PDT 24	Jul 26 07:24:54 PM PDT 24	2447857988 ps
T123	/workspace/coverage/default/12.sram_ctrl_lc_escalation.3117691881	Jul 26 07:11:37 PM PDT 24	Jul 26 07:11:38 PM PDT 24	148211630 ps
T124	/workspace/coverage/default/43.sram_ctrl_smoke.1161832805	Jul 26 07:17:03 PM PDT 24	Jul 26 07:17:16 PM PDT 24	2767159601 ps
T125	/workspace/coverage/default/37.sram_ctrl_bijection.1643518597	Jul 26 07:15:52 PM PDT 24	Jul 26 07:17:01 PM PDT 24	13490329800 ps
T53	/workspace/coverage/default/8.sram_ctrl_mem_walk.3690838116	Jul 26 07:11:14 PM PDT 24	Jul 26 07:11:24 PM PDT 24	181304620 ps
T126	/workspace/coverage/default/46.sram_ctrl_multiple_keys.3244454855	Jul 26 07:17:40 PM PDT 24	Jul 26 07:18:36 PM PDT 24	2204565215 ps
T127	/workspace/coverage/default/20.sram_ctrl_max_throughput.3884552158	Jul 26 07:12:51 PM PDT 24	Jul 26 07:13:00 PM PDT 24	310422639 ps
T128	/workspace/coverage/default/45.sram_ctrl_executable.1196514920	Jul 26 07:17:29 PM PDT 24	Jul 26 07:32:52 PM PDT 24	34389555210 ps
T20	/workspace/coverage/default/8.sram_ctrl_stress_all.3026387440	Jul 26 07:11:28 PM PDT 24	Jul 26 08:16:48 PM PDT 24	7736875558 ps
T172	/workspace/coverage/default/31.sram_ctrl_alert_test.687863954	Jul 26 07:14:46 PM PDT 24	Jul 26 07:14:47 PM PDT 24	15373709 ps
T173	/workspace/coverage/default/28.sram_ctrl_smoke.3442667944	Jul 26 07:14:00 PM PDT 24	Jul 26 07:14:05 PM PDT 24	141648426 ps
T54	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1387258158	Jul 26 07:16:35 PM PDT 24	Jul 26 07:20:25 PM PDT 24	3673390339 ps
T174	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2868784289	Jul 26 07:10:58 PM PDT 24	Jul 26 07:19:55 PM PDT 24	20692619734 ps
T144	/workspace/coverage/default/28.sram_ctrl_executable.3019291186	Jul 26 07:14:13 PM PDT 24	Jul 26 07:27:17 PM PDT 24	2304934953 ps
T175	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2618907577	Jul 26 07:11:34 PM PDT 24	Jul 26 07:15:51 PM PDT 24	2715801092 ps
T50	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1857974137	Jul 26 07:16:52 PM PDT 24	Jul 26 07:17:06 PM PDT 24	901069088 ps
T15	/workspace/coverage/default/4.sram_ctrl_sec_cm.2451173319	Jul 26 07:10:58 PM PDT 24	Jul 26 07:11:01 PM PDT 24	721286138 ps
T29	/workspace/coverage/default/27.sram_ctrl_lc_escalation.2019887126	Jul 26 07:14:02 PM PDT 24	Jul 26 07:14:04 PM PDT 24	165884928 ps
T30	/workspace/coverage/default/45.sram_ctrl_stress_all.224125803	Jul 26 07:17:32 PM PDT 24	Jul 26 07:50:54 PM PDT 24	6821652423 ps
T31	/workspace/coverage/default/46.sram_ctrl_max_throughput.2364124114	Jul 26 07:17:36 PM PDT 24	Jul 26 07:19:38 PM PDT 24	124529188 ps
T32	/workspace/coverage/default/33.sram_ctrl_stress_all.1649803824	Jul 26 07:15:07 PM PDT 24	Jul 26 07:55:17 PM PDT 24	8748652984 ps
T33	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3780165909	Jul 26 07:17:29 PM PDT 24	Jul 26 07:17:31 PM PDT 24	57489489 ps
T34	/workspace/coverage/default/38.sram_ctrl_alert_test.3820980123	Jul 26 07:16:08 PM PDT 24	Jul 26 07:16:09 PM PDT 24	10335634 ps
T35	/workspace/coverage/default/37.sram_ctrl_ram_cfg.1764472086	Jul 26 07:15:49 PM PDT 24	Jul 26 07:15:50 PM PDT 24	29022053 ps
T36	/workspace/coverage/default/18.sram_ctrl_mem_walk.2906728438	Jul 26 07:12:29 PM PDT 24	Jul 26 07:12:39 PM PDT 24	778227286 ps
T37	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.188834651	Jul 26 07:16:18 PM PDT 24	Jul 26 07:25:36 PM PDT 24	1401938935 ps
T176	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.548697990	Jul 26 07:10:41 PM PDT 24	Jul 26 07:15:39 PM PDT 24	4910555241 ps
T177	/workspace/coverage/default/5.sram_ctrl_mem_walk.3918760911	Jul 26 07:11:11 PM PDT 24	Jul 26 07:11:21 PM PDT 24	360479218 ps
T178	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2550096622	Jul 26 07:11:48 PM PDT 24	Jul 26 07:12:20 PM PDT 24	93886335 ps
T179	/workspace/coverage/default/31.sram_ctrl_ram_cfg.1829413520	Jul 26 07:14:48 PM PDT 24	Jul 26 07:14:49 PM PDT 24	27177385 ps
T180	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2247548557	Jul 26 07:12:01 PM PDT 24	Jul 26 07:12:16 PM PDT 24	75634484 ps
T181	/workspace/coverage/default/6.sram_ctrl_stress_all.4274811123	Jul 26 07:11:11 PM PDT 24	Jul 26 07:16:16 PM PDT 24	37792817093 ps
T182	/workspace/coverage/default/0.sram_ctrl_max_throughput.437329026	Jul 26 07:10:31 PM PDT 24	Jul 26 07:10:32 PM PDT 24	56289257 ps
T104	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1201369945	Jul 26 07:11:48 PM PDT 24	Jul 26 07:11:51 PM PDT 24	104781181 ps
T183	/workspace/coverage/default/20.sram_ctrl_ram_cfg.1845404010	Jul 26 07:12:51 PM PDT 24	Jul 26 07:12:52 PM PDT 24	29972350 ps
T184	/workspace/coverage/default/43.sram_ctrl_multiple_keys.857684240	Jul 26 07:17:02 PM PDT 24	Jul 26 07:27:30 PM PDT 24	46208686437 ps
T185	/workspace/coverage/default/29.sram_ctrl_bijection.3396986236	Jul 26 07:14:13 PM PDT 24	Jul 26 07:14:41 PM PDT 24	5302249011 ps
T186	/workspace/coverage/default/8.sram_ctrl_bijection.3681749657	Jul 26 07:11:11 PM PDT 24	Jul 26 07:12:31 PM PDT 24	15268601981 ps
T187	/workspace/coverage/default/9.sram_ctrl_mem_walk.655669028	Jul 26 07:11:22 PM PDT 24	Jul 26 07:11:28 PM PDT 24	223784991 ps
T151	/workspace/coverage/default/0.sram_ctrl_stress_all.979311745	Jul 26 07:10:31 PM PDT 24	Jul 26 07:58:12 PM PDT 24	25264696549 ps
T188	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3030632879	Jul 26 07:16:35 PM PDT 24	Jul 26 07:16:43 PM PDT 24	239613041 ps
T189	/workspace/coverage/default/21.sram_ctrl_ram_cfg.1475607188	Jul 26 07:13:04 PM PDT 24	Jul 26 07:13:04 PM PDT 24	32603449 ps
T51	/workspace/coverage/default/24.sram_ctrl_mem_walk.2306626194	Jul 26 07:13:36 PM PDT 24	Jul 26 07:13:48 PM PDT 24	4315362664 ps
T190	/workspace/coverage/default/13.sram_ctrl_executable.1756483923	Jul 26 07:11:56 PM PDT 24	Jul 26 07:25:28 PM PDT 24	5169487609 ps
T191	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.361620576	Jul 26 07:13:22 PM PDT 24	Jul 26 07:17:21 PM PDT 24	2554517364 ps
T192	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.88948623	Jul 26 07:14:37 PM PDT 24	Jul 26 07:21:27 PM PDT 24	67368512535 ps
T193	/workspace/coverage/default/12.sram_ctrl_partial_access.3926286038	Jul 26 07:11:36 PM PDT 24	Jul 26 07:13:00 PM PDT 24	1414459398 ps
T194	/workspace/coverage/default/45.sram_ctrl_ram_cfg.2212916605	Jul 26 07:17:28 PM PDT 24	Jul 26 07:17:29 PM PDT 24	249001427 ps
T195	/workspace/coverage/default/7.sram_ctrl_lc_escalation.3145147173	Jul 26 07:11:10 PM PDT 24	Jul 26 07:11:14 PM PDT 24	319744436 ps
T196	/workspace/coverage/default/9.sram_ctrl_lc_escalation.3278910304	Jul 26 07:11:25 PM PDT 24	Jul 26 07:11:29 PM PDT 24	382370849 ps
T197	/workspace/coverage/default/44.sram_ctrl_multiple_keys.3660737560	Jul 26 07:17:10 PM PDT 24	Jul 26 07:30:43 PM PDT 24	27353070981 ps
T198	/workspace/coverage/default/19.sram_ctrl_alert_test.933395967	Jul 26 07:12:39 PM PDT 24	Jul 26 07:12:40 PM PDT 24	11274682 ps
T199	/workspace/coverage/default/37.sram_ctrl_mem_walk.1075175081	Jul 26 07:15:48 PM PDT 24	Jul 26 07:15:59 PM PDT 24	443740861 ps
T200	/workspace/coverage/default/8.sram_ctrl_max_throughput.2938784260	Jul 26 07:11:09 PM PDT 24	Jul 26 07:12:19 PM PDT 24	105774237 ps
T201	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2722611467	Jul 26 07:10:56 PM PDT 24	Jul 26 07:13:16 PM PDT 24	4321428359 ps
T202	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.994481114	Jul 26 07:15:39 PM PDT 24	Jul 26 07:21:37 PM PDT 24	9653578806 ps
T203	/workspace/coverage/default/11.sram_ctrl_multiple_keys.3129977543	Jul 26 07:11:29 PM PDT 24	Jul 26 07:30:00 PM PDT 24	5881202438 ps
T204	/workspace/coverage/default/34.sram_ctrl_alert_test.613736481	Jul 26 07:15:16 PM PDT 24	Jul 26 07:15:17 PM PDT 24	16254986 ps
T205	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1719576657	Jul 26 07:10:57 PM PDT 24	Jul 26 07:12:40 PM PDT 24	196505774 ps
T147	/workspace/coverage/default/23.sram_ctrl_stress_all.574543978	Jul 26 07:13:22 PM PDT 24	Jul 26 08:11:43 PM PDT 24	41454391229 ps
T206	/workspace/coverage/default/34.sram_ctrl_smoke.1239191216	Jul 26 07:15:06 PM PDT 24	Jul 26 07:15:08 PM PDT 24	254741321 ps
T207	/workspace/coverage/default/32.sram_ctrl_alert_test.2481329033	Jul 26 07:15:00 PM PDT 24	Jul 26 07:15:01 PM PDT 24	30297115 ps
T208	/workspace/coverage/default/49.sram_ctrl_alert_test.175943802	Jul 26 07:18:26 PM PDT 24	Jul 26 07:18:26 PM PDT 24	38536807 ps
T209	/workspace/coverage/default/37.sram_ctrl_max_throughput.2629101063	Jul 26 07:15:51 PM PDT 24	Jul 26 07:17:48 PM PDT 24	476722726 ps
T62	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3106785748	Jul 26 07:18:25 PM PDT 24	Jul 26 07:18:30 PM PDT 24	188793158 ps
T210	/workspace/coverage/default/45.sram_ctrl_smoke.3529539554	Jul 26 07:17:18 PM PDT 24	Jul 26 07:17:27 PM PDT 24	2005646256 ps
T211	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.242712736	Jul 26 07:16:29 PM PDT 24	Jul 26 07:16:35 PM PDT 24	108926615 ps
T212	/workspace/coverage/default/9.sram_ctrl_regwen.1362249767	Jul 26 07:11:26 PM PDT 24	Jul 26 07:13:23 PM PDT 24	2718874473 ps
T213	/workspace/coverage/default/41.sram_ctrl_smoke.1966412212	Jul 26 07:16:35 PM PDT 24	Jul 26 07:16:38 PM PDT 24	139001500 ps
T214	/workspace/coverage/default/6.sram_ctrl_regwen.2874825584	Jul 26 07:11:10 PM PDT 24	Jul 26 07:14:28 PM PDT 24	24780731664 ps
T215	/workspace/coverage/default/13.sram_ctrl_max_throughput.3782104056	Jul 26 07:11:53 PM PDT 24	Jul 26 07:13:09 PM PDT 24	487819702 ps
T216	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2636086223	Jul 26 07:17:37 PM PDT 24	Jul 26 07:18:08 PM PDT 24	106041288 ps
T217	/workspace/coverage/default/15.sram_ctrl_mem_walk.2454437566	Jul 26 07:12:01 PM PDT 24	Jul 26 07:12:07 PM PDT 24	973234364 ps
T218	/workspace/coverage/default/39.sram_ctrl_max_throughput.1785267860	Jul 26 07:16:07 PM PDT 24	Jul 26 07:16:09 PM PDT 24	74563064 ps
T219	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2691691190	Jul 26 07:11:48 PM PDT 24	Jul 26 07:15:43 PM PDT 24	2566261819 ps
T220	/workspace/coverage/default/12.sram_ctrl_regwen.257366385	Jul 26 07:11:37 PM PDT 24	Jul 26 07:17:37 PM PDT 24	1676318319 ps
T145	/workspace/coverage/default/47.sram_ctrl_stress_all.912587580	Jul 26 07:18:09 PM PDT 24	Jul 26 08:31:14 PM PDT 24	79374285444 ps
T221	/workspace/coverage/default/46.sram_ctrl_alert_test.1251618097	Jul 26 07:17:48 PM PDT 24	Jul 26 07:17:48 PM PDT 24	19963244 ps
T222	/workspace/coverage/default/7.sram_ctrl_max_throughput.2896791918	Jul 26 07:11:10 PM PDT 24	Jul 26 07:11:28 PM PDT 24	162294851 ps
T223	/workspace/coverage/default/10.sram_ctrl_multiple_keys.167736507	Jul 26 07:11:27 PM PDT 24	Jul 26 07:11:50 PM PDT 24	733795983 ps
T224	/workspace/coverage/default/29.sram_ctrl_smoke.4277735625	Jul 26 07:14:13 PM PDT 24	Jul 26 07:14:19 PM PDT 24	486169811 ps
T225	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1173324003	Jul 26 07:16:40 PM PDT 24	Jul 26 07:23:39 PM PDT 24	72690892320 ps
T226	/workspace/coverage/default/47.sram_ctrl_regwen.1023352251	Jul 26 07:17:59 PM PDT 24	Jul 26 07:36:01 PM PDT 24	20275746801 ps
T227	/workspace/coverage/default/42.sram_ctrl_regwen.3398750985	Jul 26 07:16:57 PM PDT 24	Jul 26 07:29:10 PM PDT 24	3741008941 ps
T228	/workspace/coverage/default/27.sram_ctrl_mem_walk.3962321016	Jul 26 07:14:03 PM PDT 24	Jul 26 07:14:13 PM PDT 24	1827240284 ps
T229	/workspace/coverage/default/36.sram_ctrl_lc_escalation.2150226696	Jul 26 07:15:41 PM PDT 24	Jul 26 07:15:45 PM PDT 24	435740661 ps
T230	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1803493038	Jul 26 07:12:51 PM PDT 24	Jul 26 07:21:49 PM PDT 24	44565142490 ps
T231	/workspace/coverage/default/1.sram_ctrl_alert_test.2934904723	Jul 26 07:10:42 PM PDT 24	Jul 26 07:10:43 PM PDT 24	29002032 ps
T232	/workspace/coverage/default/21.sram_ctrl_alert_test.2070759139	Jul 26 07:13:01 PM PDT 24	Jul 26 07:13:01 PM PDT 24	14202902 ps
T233	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3215050433	Jul 26 07:11:47 PM PDT 24	Jul 26 07:16:33 PM PDT 24	7297691331 ps
T234	/workspace/coverage/default/1.sram_ctrl_mem_walk.1344406186	Jul 26 07:10:43 PM PDT 24	Jul 26 07:10:54 PM PDT 24	441934774 ps
T235	/workspace/coverage/default/40.sram_ctrl_ram_cfg.2658806678	Jul 26 07:16:38 PM PDT 24	Jul 26 07:16:39 PM PDT 24	87404055 ps
T236	/workspace/coverage/default/30.sram_ctrl_executable.4037639492	Jul 26 07:14:33 PM PDT 24	Jul 26 07:32:03 PM PDT 24	15434171820 ps
T237	/workspace/coverage/default/27.sram_ctrl_executable.3447296546	Jul 26 07:14:02 PM PDT 24	Jul 26 07:27:18 PM PDT 24	5211985288 ps
T238	/workspace/coverage/default/21.sram_ctrl_stress_all.2302870051	Jul 26 07:13:03 PM PDT 24	Jul 26 08:08:20 PM PDT 24	40673207077 ps
T239	/workspace/coverage/default/14.sram_ctrl_ram_cfg.1482475202	Jul 26 07:12:00 PM PDT 24	Jul 26 07:12:01 PM PDT 24	98309564 ps
T63	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2797549223	Jul 26 07:11:49 PM PDT 24	Jul 26 07:19:31 PM PDT 24	2318907040 ps
T240	/workspace/coverage/default/25.sram_ctrl_lc_escalation.1180529031	Jul 26 07:13:36 PM PDT 24	Jul 26 07:13:44 PM PDT 24	597137695 ps
T241	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1272652508	Jul 26 07:11:35 PM PDT 24	Jul 26 07:13:03 PM PDT 24	260063578 ps
T242	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2928424323	Jul 26 07:11:13 PM PDT 24	Jul 26 07:11:19 PM PDT 24	211520942 ps
T243	/workspace/coverage/default/5.sram_ctrl_regwen.3716088354	Jul 26 07:10:57 PM PDT 24	Jul 26 07:48:41 PM PDT 24	3280786010 ps
T244	/workspace/coverage/default/7.sram_ctrl_smoke.2450247106	Jul 26 07:11:09 PM PDT 24	Jul 26 07:11:24 PM PDT 24	232710418 ps
T245	/workspace/coverage/default/44.sram_ctrl_smoke.2600483690	Jul 26 07:17:10 PM PDT 24	Jul 26 07:17:15 PM PDT 24	227749170 ps
T246	/workspace/coverage/default/34.sram_ctrl_bijection.2808157877	Jul 26 07:15:16 PM PDT 24	Jul 26 07:16:32 PM PDT 24	4364812507 ps
T247	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2937333087	Jul 26 07:10:32 PM PDT 24	Jul 26 07:35:20 PM PDT 24	8245837861 ps
T248	/workspace/coverage/default/17.sram_ctrl_smoke.3118132667	Jul 26 07:12:11 PM PDT 24	Jul 26 07:13:02 PM PDT 24	104597156 ps
T249	/workspace/coverage/default/21.sram_ctrl_max_throughput.632879445	Jul 26 07:12:53 PM PDT 24	Jul 26 07:13:37 PM PDT 24	357303209 ps
T250	/workspace/coverage/default/29.sram_ctrl_regwen.1956972891	Jul 26 07:14:23 PM PDT 24	Jul 26 07:29:37 PM PDT 24	13233464318 ps
T251	/workspace/coverage/default/32.sram_ctrl_executable.2672406537	Jul 26 07:14:58 PM PDT 24	Jul 26 07:22:02 PM PDT 24	1561847763 ps
T252	/workspace/coverage/default/11.sram_ctrl_regwen.2024819303	Jul 26 07:11:36 PM PDT 24	Jul 26 07:32:00 PM PDT 24	24226531965 ps
T253	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.460649665	Jul 26 07:15:58 PM PDT 24	Jul 26 07:16:01 PM PDT 24	55389687 ps
T254	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2936363722	Jul 26 07:18:15 PM PDT 24	Jul 26 07:21:04 PM PDT 24	1965104089 ps
T64	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3051123910	Jul 26 07:12:30 PM PDT 24	Jul 26 07:12:33 PM PDT 24	102746796 ps
T255	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.201084121	Jul 26 07:11:20 PM PDT 24	Jul 26 07:15:04 PM PDT 24	5880099096 ps
T256	/workspace/coverage/default/17.sram_ctrl_regwen.748063038	Jul 26 07:12:20 PM PDT 24	Jul 26 07:31:28 PM PDT 24	13540912281 ps
T257	/workspace/coverage/default/16.sram_ctrl_regwen.4240163505	Jul 26 07:12:11 PM PDT 24	Jul 26 07:26:43 PM PDT 24	16910038138 ps
T258	/workspace/coverage/default/18.sram_ctrl_bijection.2569171480	Jul 26 07:12:18 PM PDT 24	Jul 26 07:12:50 PM PDT 24	2964606532 ps
T259	/workspace/coverage/default/14.sram_ctrl_lc_escalation.150052942	Jul 26 07:11:57 PM PDT 24	Jul 26 07:12:09 PM PDT 24	5763991243 ps
T260	/workspace/coverage/default/22.sram_ctrl_ram_cfg.709421189	Jul 26 07:13:00 PM PDT 24	Jul 26 07:13:01 PM PDT 24	25896324 ps
T261	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3343897458	Jul 26 07:14:45 PM PDT 24	Jul 26 07:21:00 PM PDT 24	6462879357 ps
T262	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3712177250	Jul 26 07:18:12 PM PDT 24	Jul 26 07:21:19 PM PDT 24	38775528661 ps
T263	/workspace/coverage/default/14.sram_ctrl_alert_test.2218608576	Jul 26 07:12:01 PM PDT 24	Jul 26 07:12:02 PM PDT 24	86809926 ps
T264	/workspace/coverage/default/48.sram_ctrl_ram_cfg.486479233	Jul 26 07:18:18 PM PDT 24	Jul 26 07:18:19 PM PDT 24	31554742 ps
T265	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1195873588	Jul 26 07:10:58 PM PDT 24	Jul 26 07:25:50 PM PDT 24	7446850750 ps
T266	/workspace/coverage/default/26.sram_ctrl_bijection.660191303	Jul 26 07:13:50 PM PDT 24	Jul 26 07:14:53 PM PDT 24	16911703462 ps
T267	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1420636021	Jul 26 07:13:48 PM PDT 24	Jul 26 07:23:39 PM PDT 24	166507966326 ps
T268	/workspace/coverage/default/25.sram_ctrl_mem_walk.23526211	Jul 26 07:13:48 PM PDT 24	Jul 26 07:13:53 PM PDT 24	98478148 ps
T269	/workspace/coverage/default/13.sram_ctrl_alert_test.1059265217	Jul 26 07:11:48 PM PDT 24	Jul 26 07:11:49 PM PDT 24	26979145 ps
T270	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3061426478	Jul 26 07:11:11 PM PDT 24	Jul 26 07:17:46 PM PDT 24	65133290104 ps
T271	/workspace/coverage/default/21.sram_ctrl_regwen.1651724882	Jul 26 07:13:01 PM PDT 24	Jul 26 07:16:19 PM PDT 24	1324450291 ps
T272	/workspace/coverage/default/22.sram_ctrl_multiple_keys.3984122285	Jul 26 07:12:59 PM PDT 24	Jul 26 07:50:19 PM PDT 24	6842945655 ps
T273	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3882807921	Jul 26 07:14:57 PM PDT 24	Jul 26 07:17:11 PM PDT 24	534663507 ps
T274	/workspace/coverage/default/18.sram_ctrl_regwen.2200904558	Jul 26 07:12:32 PM PDT 24	Jul 26 07:27:13 PM PDT 24	22089991334 ps
T275	/workspace/coverage/default/29.sram_ctrl_lc_escalation.4188561553	Jul 26 07:14:13 PM PDT 24	Jul 26 07:14:19 PM PDT 24	467765054 ps
T276	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1282559555	Jul 26 07:13:35 PM PDT 24	Jul 26 07:17:39 PM PDT 24	2636014054 ps
T277	/workspace/coverage/default/33.sram_ctrl_regwen.893646573	Jul 26 07:15:07 PM PDT 24	Jul 26 07:44:48 PM PDT 24	15312734434 ps
T278	/workspace/coverage/default/14.sram_ctrl_multiple_keys.2151475876	Jul 26 07:11:49 PM PDT 24	Jul 26 07:20:43 PM PDT 24	7864130479 ps
T65	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2243847778	Jul 26 07:12:19 PM PDT 24	Jul 26 07:12:25 PM PDT 24	686099062 ps
T75	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.708671090	Jul 26 07:13:48 PM PDT 24	Jul 26 07:14:03 PM PDT 24	436375521 ps
T279	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.66685328	Jul 26 07:11:20 PM PDT 24	Jul 26 07:11:46 PM PDT 24	400078725 ps
T280	/workspace/coverage/default/38.sram_ctrl_stress_all.3073165377	Jul 26 07:16:09 PM PDT 24	Jul 26 08:02:48 PM PDT 24	15268521978 ps
T281	/workspace/coverage/default/43.sram_ctrl_lc_escalation.1077673067	Jul 26 07:17:04 PM PDT 24	Jul 26 07:17:11 PM PDT 24	2566545454 ps
T282	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2531882065	Jul 26 07:13:37 PM PDT 24	Jul 26 07:13:48 PM PDT 24	255763622 ps
T283	/workspace/coverage/default/15.sram_ctrl_stress_all.2288246890	Jul 26 07:11:59 PM PDT 24	Jul 26 09:00:46 PM PDT 24	257856593589 ps
T284	/workspace/coverage/default/12.sram_ctrl_ram_cfg.1259567774	Jul 26 07:11:35 PM PDT 24	Jul 26 07:11:36 PM PDT 24	89329965 ps
T285	/workspace/coverage/default/21.sram_ctrl_lc_escalation.2437589092	Jul 26 07:12:54 PM PDT 24	Jul 26 07:13:01 PM PDT 24	1238530108 ps
T286	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3547365150	Jul 26 07:15:40 PM PDT 24	Jul 26 07:16:18 PM PDT 24	112020989 ps
T287	/workspace/coverage/default/8.sram_ctrl_lc_escalation.3679006961	Jul 26 07:11:11 PM PDT 24	Jul 26 07:11:18 PM PDT 24	703867528 ps
T76	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.492808913	Jul 26 07:14:01 PM PDT 24	Jul 26 07:14:32 PM PDT 24	1132951913 ps
T288	/workspace/coverage/default/27.sram_ctrl_bijection.1244303613	Jul 26 07:14:01 PM PDT 24	Jul 26 07:15:24 PM PDT 24	10612859850 ps
T289	/workspace/coverage/default/8.sram_ctrl_alert_test.1403140517	Jul 26 07:11:22 PM PDT 24	Jul 26 07:11:23 PM PDT 24	11264761 ps
T290	/workspace/coverage/default/15.sram_ctrl_bijection.2158021531	Jul 26 07:12:00 PM PDT 24	Jul 26 07:13:01 PM PDT 24	5732565689 ps
T291	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.186085709	Jul 26 07:10:54 PM PDT 24	Jul 26 07:16:04 PM PDT 24	108199736760 ps
T292	/workspace/coverage/default/5.sram_ctrl_ram_cfg.3170351492	Jul 26 07:11:10 PM PDT 24	Jul 26 07:11:11 PM PDT 24	72624306 ps
T293	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1301938365	Jul 26 07:17:40 PM PDT 24	Jul 26 07:22:34 PM PDT 24	11608284653 ps
T294	/workspace/coverage/default/40.sram_ctrl_partial_access.564044030	Jul 26 07:16:28 PM PDT 24	Jul 26 07:16:39 PM PDT 24	605510058 ps
T295	/workspace/coverage/default/10.sram_ctrl_ram_cfg.119542965	Jul 26 07:11:34 PM PDT 24	Jul 26 07:11:35 PM PDT 24	29890326 ps
T296	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.497296005	Jul 26 07:14:57 PM PDT 24	Jul 26 07:20:51 PM PDT 24	6845268005 ps
T297	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2364443954	Jul 26 07:13:48 PM PDT 24	Jul 26 07:13:53 PM PDT 24	68049025 ps
T298	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3635765663	Jul 26 07:10:56 PM PDT 24	Jul 26 07:11:02 PM PDT 24	966574742 ps
T299	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1326653954	Jul 26 07:12:10 PM PDT 24	Jul 26 07:15:58 PM PDT 24	8256999762 ps
T300	/workspace/coverage/default/36.sram_ctrl_executable.3859931415	Jul 26 07:15:38 PM PDT 24	Jul 26 07:16:04 PM PDT 24	1769622924 ps
T77	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3520911894	Jul 26 07:13:48 PM PDT 24	Jul 26 07:14:41 PM PDT 24	1102951332 ps
T301	/workspace/coverage/default/43.sram_ctrl_bijection.863576517	Jul 26 07:17:00 PM PDT 24	Jul 26 07:17:18 PM PDT 24	5331668147 ps
T302	/workspace/coverage/default/18.sram_ctrl_stress_all.2324643127	Jul 26 07:12:31 PM PDT 24	Jul 26 07:30:16 PM PDT 24	8751379889 ps