Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44820209	1			T1	137901		T2	6262		T3	4295
triple_byte_access	2643828	1			T1	2682		T2	299		T4	1453
halfword_access	3966142	1			T1	4055		T2	400		T4	2146
byte_access	5297670	1			T1	5613		T2	570		T4	2936
zero_access	1333012	1			T1	1382		T2	157		T4	731

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28973964

1

T1

76010

T2

3843

T3

2117

auto[1]

29086897

1

T1

75623

T2

3845

T3

2178

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22357053	1			T1	69097		T2	3146		T3	2117
auto[0]	triple_byte_access	1319363	1			T1	1384		T2	136		T4	745
auto[0]	halfword_access	1979101	1			T1	2013		T2	197		T4	1052
auto[0]	byte_access	2647608	1			T1	2809		T2	289		T4	1442
auto[0]	zero_access	670839	1			T1	707		T2	75		T4	379
auto[1]	word_access	22463156	1			T1	68804		T2	3116		T3	2178
auto[1]	triple_byte_access	1324465	1			T1	1298		T2	163		T4	708
auto[1]	halfword_access	1987041	1			T1	2042		T2	203		T4	1094
auto[1]	byte_access	2650062	1			T1	2804		T2	281		T4	1494
auto[1]	zero_access	662173	1			T1	675		T2	82		T4	352