Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	141717518	1			T1	102990		T2	12284		T3	164258
instr_valid_dis	115878466	1			T1	58576		T2	12284		T3	10376
instr_en	18404189	1			T1	44414		T3	153882		T4	177872

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9892614	1			T3	27894		T4	57478		T13	95172
sram_ifetch_valid_disable	109654617	1			T1	71454		T2	12284		T3	10376
sram_ifetch_enable	22170287	1			T1	31536		T3	125988		T4	84428

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	141717518	1			T1	102990		T2	12284		T3	164258
hw_debug_en_valid_off	111966336	1			T1	63228		T2	12284		T3	95584
hw_debug_en_on	19404078	1			T1	39762		T3	64478		T4	144358

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	109654617	1			T1	71454		T2	12284		T3	10376
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	100213006	1			T1	58576		T2	12284		T3	10376
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	6820692	1			T1	12878		T4	93730		T13	170128
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3434526	1			T13	14962		T14	16532		T20	13858
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1751910	1			T14	16532		T108	9374		T124	35334
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1257098	1			T13	14962		T20	13858		T21	24624
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4287452	1			T3	27894		T4	40026		T13	16494
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2029192	1			T108	20106		T46	4024		T126	7684
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1563974	1			T3	27894		T4	40026		T13	16494
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6737084	1			T1	12878		T3	10376		T4	47028
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3106534	1			T3	10376		T14	13658		T123	36620
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2554568	1			T1	12878		T4	44828		T13	123362

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8116203	1			T1	31536		T3	125988		T4	26664
lc_exec_en	8379542	1			T1	26884		T3	26208		T4	57304
valid_exec_dis	109604928	1			T1	58576		T2	12284		T5	3958
invalid_exec_dis	32062901	1			T1	31536		T3	153882		T4	141906