Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Total tests in report: 1023

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
79.59	79.59	95.85	95.85	81.99	81.99	93.52	93.52	61.90	61.90	86.71	86.71	94.40	94.40	42.78	42.78	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2258863708
85.57	5.98	97.03	1.19	84.83	2.84	94.80	1.28	71.43	9.52	89.37	2.66	94.99	0.59	66.54	23.77	/workspace/coverage/default/39.sram_ctrl_lc_escalation.668435116
90.99	5.42	98.73	1.69	86.49	1.66	95.56	0.76	100.00	28.57	93.24	3.86	96.02	1.03	66.91	0.37	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.941152104
92.90	1.91	98.73	0.00	86.49	0.00	95.56	0.00	100.00	0.00	93.24	0.00	96.02	0.00	80.26	13.35	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.449186651
94.18	1.28	98.73	0.00	87.56	1.07	97.16	1.60	100.00	0.00	93.96	0.72	96.46	0.44	85.37	5.12	/workspace/coverage/default/33.sram_ctrl_executable.324073075
95.13	0.95	98.90	0.17	88.39	0.83	97.36	0.21	100.00	0.00	94.69	0.72	96.46	0.00	90.13	4.75	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.135976311
95.89	0.75	99.07	0.17	90.17	1.78	98.47	1.11	100.00	0.00	95.41	0.72	97.05	0.59	91.04	0.91	/workspace/coverage/default/4.sram_ctrl_sec_cm.194262010
96.28	0.39	99.07	0.00	90.17	0.00	98.47	0.00	100.00	0.00	95.41	0.00	97.05	0.00	93.78	2.74	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1146020273
96.53	0.25	99.07	0.00	90.28	0.12	98.47	0.00	100.00	0.00	95.41	0.00	97.05	0.00	95.43	1.65	/workspace/coverage/default/17.sram_ctrl_stress_all.2767706309
96.71	0.18	99.07	0.00	90.28	0.00	98.75	0.28	100.00	0.00	95.65	0.24	97.79	0.74	95.43	0.00	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1071799989
96.86	0.15	99.07	0.00	90.28	0.00	98.75	0.00	100.00	0.00	95.65	0.00	98.82	1.03	95.43	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.972079990
96.99	0.13	99.15	0.08	90.28	0.00	99.58	0.83	100.00	0.00	95.65	0.00	98.82	0.00	95.43	0.00	/workspace/coverage/default/0.sram_ctrl_ram_cfg.650783660
97.12	0.13	99.15	0.00	90.28	0.00	99.58	0.00	100.00	0.00	95.65	0.00	98.82	0.00	96.34	0.91	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1429079045
97.21	0.09	99.15	0.00	90.40	0.12	99.58	0.00	100.00	0.00	96.14	0.48	98.82	0.00	96.34	0.00	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1265255251
97.28	0.08	99.15	0.00	90.40	0.00	99.58	0.00	100.00	0.00	96.14	0.00	98.82	0.00	96.89	0.55	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.152906886
97.34	0.06	99.15	0.00	90.76	0.36	99.65	0.07	100.00	0.00	96.14	0.00	98.82	0.00	96.89	0.00	/workspace/coverage/default/11.sram_ctrl_alert_test.497656164
97.40	0.06	99.15	0.00	91.00	0.24	99.65	0.00	100.00	0.00	96.14	0.00	98.82	0.00	97.07	0.18	/workspace/coverage/default/18.sram_ctrl_lc_escalation.1240821856
97.46	0.05	99.15	0.00	91.00	0.00	99.72	0.07	100.00	0.00	96.14	0.00	99.12	0.29	97.07	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1986520769
97.48	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.26	0.18	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.403840726
97.51	0.03	99.15	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.14	0.00	99.12	0.00	97.44	0.18	/workspace/coverage/default/11.sram_ctrl_executable.1529251522

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2414913849
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2471829881
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.427173002
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3923631648
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3310955576
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.289369119
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.635235755
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.664526571
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3290863577
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2707165170
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3965765742
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1151799704
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4142259794
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3643438641
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.26423399
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3769719049
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3214716559
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1618969139
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.996795767
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3166179774
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.418835010
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3918776771
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3508844561
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.15382156
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2237044132
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2852337054
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.822030842
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2296237619
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3487999018
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4251694405
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2747669278
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.356541206
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.376103675
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.456314202
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.351530648
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2130094988
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1325916479
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3539804499
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3267385690
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.673345956
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.199853381
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4150699952
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.592664941
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.819460799
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1624350145
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.122013663
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2940234513
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3722010056
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.697057388
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2485861812
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.363967860
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2300942048
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1227583100
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.436642998
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2776416744
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2575656554
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2279192237
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3075530704
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3642559209
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2136206454
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.784410383
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3924385835
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.919595204
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1444080352
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2167026916
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2766662222
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2019884452
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2182801991
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1050248410
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3321436590
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2841468529
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2740601291
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2791880176
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1958970466
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.283661147
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2985412313
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3533625457
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3452294173
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1043845497
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2791797413
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2591958807
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.506069604
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1749031227
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3955857835
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2936704034
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4013741969
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1064206345
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.510398885
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1854220563
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2547710832
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3245724227
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1976951934
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.918909970
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3561082027
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1847201364
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3724916504
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3561592701
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2606596765
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3471920651
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2790362649
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2540565138
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3131937316
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.863528265
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3011090369
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3873600436
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1625238312
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2218659238
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4076369983
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3331605473
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1325813006
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3085720807
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3588683333
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3625661307
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1946125176
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3142863055
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.239701886
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2724509297
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2162351558
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1334627695
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1118993306
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2926971515
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4033602262
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.30560526
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3766814154
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3217707936
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.397561149
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2957738779
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1450654637
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.4256894381
/workspace/coverage/default/0.sram_ctrl_alert_test.1987713705
/workspace/coverage/default/0.sram_ctrl_bijection.2536269448
/workspace/coverage/default/0.sram_ctrl_executable.517944627
/workspace/coverage/default/0.sram_ctrl_lc_escalation.603794640
/workspace/coverage/default/0.sram_ctrl_max_throughput.99731008
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1295027759
/workspace/coverage/default/0.sram_ctrl_mem_walk.3703608677
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3352668389
/workspace/coverage/default/0.sram_ctrl_partial_access.2702699133
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2996957259
/workspace/coverage/default/0.sram_ctrl_regwen.2385079767
/workspace/coverage/default/0.sram_ctrl_sec_cm.1834919438
/workspace/coverage/default/0.sram_ctrl_smoke.3219066420
/workspace/coverage/default/0.sram_ctrl_stress_all.102652476
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.353274392
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1607806849
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2429725588
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1988331270
/workspace/coverage/default/1.sram_ctrl_alert_test.2403271675
/workspace/coverage/default/1.sram_ctrl_bijection.816353364
/workspace/coverage/default/1.sram_ctrl_executable.1471242669
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2284056100
/workspace/coverage/default/1.sram_ctrl_max_throughput.2835167024
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3434744780
/workspace/coverage/default/1.sram_ctrl_mem_walk.4089296579
/workspace/coverage/default/1.sram_ctrl_multiple_keys.311875054
/workspace/coverage/default/1.sram_ctrl_partial_access.4062318615
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1997491698
/workspace/coverage/default/1.sram_ctrl_ram_cfg.377902050
/workspace/coverage/default/1.sram_ctrl_regwen.1785971340
/workspace/coverage/default/1.sram_ctrl_sec_cm.4065580393
/workspace/coverage/default/1.sram_ctrl_smoke.3081668436
/workspace/coverage/default/1.sram_ctrl_stress_all.1880556135
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2762931893
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.159777122
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3956865269
/workspace/coverage/default/10.sram_ctrl_alert_test.588855932
/workspace/coverage/default/10.sram_ctrl_bijection.3746967657
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1660323131
/workspace/coverage/default/10.sram_ctrl_max_throughput.3712260792
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.182803474
/workspace/coverage/default/10.sram_ctrl_mem_walk.2509405634
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1818217893
/workspace/coverage/default/10.sram_ctrl_partial_access.3018445065
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3054593151
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1051627172
/workspace/coverage/default/10.sram_ctrl_regwen.237009757
/workspace/coverage/default/10.sram_ctrl_smoke.1289577037
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.612236926
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3383486947
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.762109833
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2505829410
/workspace/coverage/default/11.sram_ctrl_bijection.3720510115
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2472628421
/workspace/coverage/default/11.sram_ctrl_max_throughput.2317689190
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1159002161
/workspace/coverage/default/11.sram_ctrl_mem_walk.3475718952
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2616150121
/workspace/coverage/default/11.sram_ctrl_partial_access.4148536128
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2216848255
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3145393630
/workspace/coverage/default/11.sram_ctrl_regwen.2138619514
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/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3910140158
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2493381632
/workspace/coverage/default/43.sram_ctrl_alert_test.1652512341
/workspace/coverage/default/43.sram_ctrl_bijection.944581614
/workspace/coverage/default/43.sram_ctrl_executable.3296775292
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1126402754
/workspace/coverage/default/43.sram_ctrl_max_throughput.3919714658
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2486903008
/workspace/coverage/default/43.sram_ctrl_mem_walk.1233617614
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1650234656
/workspace/coverage/default/43.sram_ctrl_partial_access.2758154075
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1395494006
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2962336428
/workspace/coverage/default/43.sram_ctrl_regwen.827341133
/workspace/coverage/default/43.sram_ctrl_smoke.1763035496
/workspace/coverage/default/43.sram_ctrl_stress_all.2485834968
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1718018802
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3931522514
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3892569347
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.635702802
/workspace/coverage/default/44.sram_ctrl_alert_test.2013606465
/workspace/coverage/default/44.sram_ctrl_bijection.378308275
/workspace/coverage/default/44.sram_ctrl_executable.2818308413
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1027523371
/workspace/coverage/default/44.sram_ctrl_max_throughput.135232141
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4036490792
/workspace/coverage/default/44.sram_ctrl_mem_walk.1934459449
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4285505896
/workspace/coverage/default/44.sram_ctrl_partial_access.2997390019
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1542470961
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2046104804
/workspace/coverage/default/44.sram_ctrl_regwen.1014846608
/workspace/coverage/default/44.sram_ctrl_smoke.985106694
/workspace/coverage/default/44.sram_ctrl_stress_all.881039501
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.625460668
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1760102307
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.317925711
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2191141832
/workspace/coverage/default/45.sram_ctrl_alert_test.137088360
/workspace/coverage/default/45.sram_ctrl_bijection.850349340
/workspace/coverage/default/45.sram_ctrl_executable.3190234289
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3826021114
/workspace/coverage/default/45.sram_ctrl_max_throughput.1187161222
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4086168945
/workspace/coverage/default/45.sram_ctrl_mem_walk.421070884
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3024650256
/workspace/coverage/default/45.sram_ctrl_partial_access.345858782
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1439090143
/workspace/coverage/default/45.sram_ctrl_ram_cfg.4259404058
/workspace/coverage/default/45.sram_ctrl_regwen.342926470
/workspace/coverage/default/45.sram_ctrl_smoke.209744373
/workspace/coverage/default/45.sram_ctrl_stress_all.371467706
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3577559253
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2418055434
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.879988962
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3923613647
/workspace/coverage/default/46.sram_ctrl_alert_test.3983987600
/workspace/coverage/default/46.sram_ctrl_bijection.3649658715
/workspace/coverage/default/46.sram_ctrl_executable.2975105105
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3640879024
/workspace/coverage/default/46.sram_ctrl_max_throughput.1831599966
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1249811188
/workspace/coverage/default/46.sram_ctrl_mem_walk.2362051939
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4288541179
/workspace/coverage/default/46.sram_ctrl_partial_access.4056272461
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.604432120
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2664892647
/workspace/coverage/default/46.sram_ctrl_regwen.3637763086
/workspace/coverage/default/46.sram_ctrl_smoke.2149224954
/workspace/coverage/default/46.sram_ctrl_stress_all.2490057468
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3195089547
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3768826132
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3537539213
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3495994577
/workspace/coverage/default/47.sram_ctrl_alert_test.916802347
/workspace/coverage/default/47.sram_ctrl_bijection.384875923
/workspace/coverage/default/47.sram_ctrl_executable.846990903
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1101838890
/workspace/coverage/default/47.sram_ctrl_max_throughput.4181455247
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.372090555
/workspace/coverage/default/47.sram_ctrl_mem_walk.3644916228
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1341409653
/workspace/coverage/default/47.sram_ctrl_partial_access.3407703613
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3457362173
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3284194136
/workspace/coverage/default/47.sram_ctrl_regwen.3438255298
/workspace/coverage/default/47.sram_ctrl_smoke.1910375898
/workspace/coverage/default/47.sram_ctrl_stress_all.3145527483
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.26706855
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1873631947
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.133633582
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3361362017
/workspace/coverage/default/48.sram_ctrl_alert_test.2086180700
/workspace/coverage/default/48.sram_ctrl_bijection.4279600983
/workspace/coverage/default/48.sram_ctrl_executable.894984438
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1027725849
/workspace/coverage/default/48.sram_ctrl_max_throughput.131159355
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3002638689
/workspace/coverage/default/48.sram_ctrl_mem_walk.1786119543
/workspace/coverage/default/48.sram_ctrl_multiple_keys.874727632
/workspace/coverage/default/48.sram_ctrl_partial_access.2888667664
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2367286187
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3407796261
/workspace/coverage/default/48.sram_ctrl_regwen.3907124199
/workspace/coverage/default/48.sram_ctrl_smoke.3154843047
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4253691015
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3317023058
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3640116455
/workspace/coverage/default/49.sram_ctrl_alert_test.2883299130
/workspace/coverage/default/49.sram_ctrl_bijection.3919257854
/workspace/coverage/default/49.sram_ctrl_executable.1903364324
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3385486922
/workspace/coverage/default/49.sram_ctrl_max_throughput.1907698294
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1386740000
/workspace/coverage/default/49.sram_ctrl_mem_walk.4085392646
/workspace/coverage/default/49.sram_ctrl_multiple_keys.693719977
/workspace/coverage/default/49.sram_ctrl_partial_access.2184139515
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3184667311
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2375453398
/workspace/coverage/default/49.sram_ctrl_regwen.1514333142
/workspace/coverage/default/49.sram_ctrl_smoke.2524213642
/workspace/coverage/default/49.sram_ctrl_stress_all.3054440247
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.35416298
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1453508139
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3630267338
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3727280783
/workspace/coverage/default/5.sram_ctrl_alert_test.2478058897
/workspace/coverage/default/5.sram_ctrl_bijection.1951436199
/workspace/coverage/default/5.sram_ctrl_executable.2874396011
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2005015968
/workspace/coverage/default/5.sram_ctrl_max_throughput.2951453671
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2687677170
/workspace/coverage/default/5.sram_ctrl_mem_walk.4245984318
/workspace/coverage/default/5.sram_ctrl_multiple_keys.205402016
/workspace/coverage/default/5.sram_ctrl_partial_access.1526716112
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.217065642
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2585770501
/workspace/coverage/default/5.sram_ctrl_regwen.785220726
/workspace/coverage/default/5.sram_ctrl_smoke.1042305351
/workspace/coverage/default/5.sram_ctrl_stress_all.3774627686
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2438464560
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3805306999
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.531471459
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2978090632
/workspace/coverage/default/6.sram_ctrl_alert_test.3397469865
/workspace/coverage/default/6.sram_ctrl_bijection.4087471425
/workspace/coverage/default/6.sram_ctrl_executable.1985918347
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4150138456
/workspace/coverage/default/6.sram_ctrl_max_throughput.2954550053
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2113191831
/workspace/coverage/default/6.sram_ctrl_mem_walk.3217009610
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2698988320
/workspace/coverage/default/6.sram_ctrl_partial_access.1361607469
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1874527330
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3478593890
/workspace/coverage/default/6.sram_ctrl_regwen.701952502
/workspace/coverage/default/6.sram_ctrl_smoke.1237213242
/workspace/coverage/default/6.sram_ctrl_stress_all.1572368684
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1472366094
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.122312051
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2970870524
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1603127661
/workspace/coverage/default/7.sram_ctrl_alert_test.3147778857
/workspace/coverage/default/7.sram_ctrl_bijection.600798474
/workspace/coverage/default/7.sram_ctrl_executable.1901417001
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1851592602
/workspace/coverage/default/7.sram_ctrl_max_throughput.2000866713
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2666218828
/workspace/coverage/default/7.sram_ctrl_mem_walk.2563328764
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1229300977
/workspace/coverage/default/7.sram_ctrl_partial_access.1404428194
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1775356639
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3432930843
/workspace/coverage/default/7.sram_ctrl_regwen.2263706609
/workspace/coverage/default/7.sram_ctrl_smoke.2937884615
/workspace/coverage/default/7.sram_ctrl_stress_all.3370454882
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1024947999
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4083102910
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.850523849
/workspace/coverage/default/8.sram_ctrl_alert_test.1317603516
/workspace/coverage/default/8.sram_ctrl_bijection.3792884034
/workspace/coverage/default/8.sram_ctrl_executable.1225604141
/workspace/coverage/default/8.sram_ctrl_lc_escalation.912532764
/workspace/coverage/default/8.sram_ctrl_max_throughput.1316986351
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2507454117
/workspace/coverage/default/8.sram_ctrl_mem_walk.4251249529
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3707291015
/workspace/coverage/default/8.sram_ctrl_partial_access.1622674624
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1995440523
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2068398127
/workspace/coverage/default/8.sram_ctrl_regwen.2565502543
/workspace/coverage/default/8.sram_ctrl_smoke.1231480825
/workspace/coverage/default/8.sram_ctrl_stress_all.3791432896
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2952211494
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2583192547
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1871884207
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3421443229
/workspace/coverage/default/9.sram_ctrl_alert_test.3230037924
/workspace/coverage/default/9.sram_ctrl_bijection.2962874834
/workspace/coverage/default/9.sram_ctrl_executable.349368284
/workspace/coverage/default/9.sram_ctrl_lc_escalation.927366257
/workspace/coverage/default/9.sram_ctrl_max_throughput.1919739144
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2182792474
/workspace/coverage/default/9.sram_ctrl_mem_walk.1241803270
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3171388852
/workspace/coverage/default/9.sram_ctrl_partial_access.1122829635
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.414371621
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3869631223
/workspace/coverage/default/9.sram_ctrl_regwen.3032666842
/workspace/coverage/default/9.sram_ctrl_smoke.1076462544
/workspace/coverage/default/9.sram_ctrl_stress_all.2619047510
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3433330390
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1133058361
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.788320352

Total test records in report: 1023

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2258863708	Jul 27 04:59:47 PM PDT 24	Jul 27 05:02:40 PM PDT 24	1976602758 ps
T2	/workspace/coverage/default/1.sram_ctrl_mem_walk.4089296579	Jul 27 04:59:42 PM PDT 24	Jul 27 04:59:53 PM PDT 24	1837385852 ps
T3	/workspace/coverage/default/46.sram_ctrl_executable.2975105105	Jul 27 05:01:40 PM PDT 24	Jul 27 05:11:31 PM PDT 24	5391094904 ps
T5	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2545483432	Jul 27 05:00:31 PM PDT 24	Jul 27 05:00:36 PM PDT 24	70093103 ps
T10	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1307100088	Jul 27 04:59:46 PM PDT 24	Jul 27 04:59:49 PM PDT 24	788477595 ps
T4	/workspace/coverage/default/33.sram_ctrl_executable.324073075	Jul 27 05:00:58 PM PDT 24	Jul 27 05:13:48 PM PDT 24	19285066001 ps
T11	/workspace/coverage/default/7.sram_ctrl_ram_cfg.3432930843	Jul 27 04:59:51 PM PDT 24	Jul 27 04:59:52 PM PDT 24	31320833 ps
T12	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2637704683	Jul 27 05:00:29 PM PDT 24	Jul 27 05:06:24 PM PDT 24	9413799622 ps
T13	/workspace/coverage/default/11.sram_ctrl_regwen.2138619514	Jul 27 05:00:22 PM PDT 24	Jul 27 05:33:08 PM PDT 24	16226091384 ps
T14	/workspace/coverage/default/13.sram_ctrl_executable.2848257382	Jul 27 05:00:10 PM PDT 24	Jul 27 05:16:19 PM PDT 24	101828612814 ps
T37	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.850523849	Jul 27 04:59:54 PM PDT 24	Jul 27 05:08:37 PM PDT 24	1852883208 ps
T27	/workspace/coverage/default/0.sram_ctrl_ram_cfg.650783660	Jul 27 04:59:35 PM PDT 24	Jul 27 04:59:36 PM PDT 24	31156784 ps
T38	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2486903008	Jul 27 05:01:29 PM PDT 24	Jul 27 05:01:35 PM PDT 24	678935425 ps
T15	/workspace/coverage/default/26.sram_ctrl_alert_test.1001996846	Jul 27 05:00:32 PM PDT 24	Jul 27 05:00:33 PM PDT 24	13431051 ps
T6	/workspace/coverage/default/39.sram_ctrl_lc_escalation.668435116	Jul 27 05:01:07 PM PDT 24	Jul 27 05:01:12 PM PDT 24	5722027864 ps
T9	/workspace/coverage/default/4.sram_ctrl_sec_cm.194262010	Jul 27 04:59:34 PM PDT 24	Jul 27 04:59:37 PM PDT 24	777720247 ps
T7	/workspace/coverage/default/32.sram_ctrl_lc_escalation.3824684101	Jul 27 05:00:44 PM PDT 24	Jul 27 05:00:46 PM PDT 24	131694464 ps
T31	/workspace/coverage/default/4.sram_ctrl_mem_walk.3450354906	Jul 27 04:59:52 PM PDT 24	Jul 27 04:59:59 PM PDT 24	348114462 ps
T32	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.941152104	Jul 27 05:00:11 PM PDT 24	Jul 27 05:00:17 PM PDT 24	191395383 ps
T33	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3281193925	Jul 27 05:00:06 PM PDT 24	Jul 27 05:01:59 PM PDT 24	1180261837 ps
T34	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2182677372	Jul 27 05:00:26 PM PDT 24	Jul 27 05:00:29 PM PDT 24	170062936 ps
T28	/workspace/coverage/default/33.sram_ctrl_ram_cfg.2212601492	Jul 27 05:00:53 PM PDT 24	Jul 27 05:00:54 PM PDT 24	49316388 ps
T20	/workspace/coverage/default/3.sram_ctrl_regwen.3175304997	Jul 27 04:59:43 PM PDT 24	Jul 27 05:07:11 PM PDT 24	7540238553 ps
T35	/workspace/coverage/default/7.sram_ctrl_smoke.2937884615	Jul 27 04:59:55 PM PDT 24	Jul 27 05:00:01 PM PDT 24	176586624 ps
T36	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2420410386	Jul 27 05:00:25 PM PDT 24	Jul 27 05:05:36 PM PDT 24	12195788590 ps
T135	/workspace/coverage/default/38.sram_ctrl_ram_cfg.1170520003	Jul 27 05:01:11 PM PDT 24	Jul 27 05:01:12 PM PDT 24	26890831 ps
T129	/workspace/coverage/default/28.sram_ctrl_bijection.3552817796	Jul 27 05:00:32 PM PDT 24	Jul 27 05:01:38 PM PDT 24	3874538878 ps
T130	/workspace/coverage/default/26.sram_ctrl_bijection.713123160	Jul 27 05:00:31 PM PDT 24	Jul 27 05:01:32 PM PDT 24	8490173467 ps
T8	/workspace/coverage/default/30.sram_ctrl_lc_escalation.4240903617	Jul 27 05:00:40 PM PDT 24	Jul 27 05:00:46 PM PDT 24	1833470047 ps
T136	/workspace/coverage/default/16.sram_ctrl_max_throughput.2282978935	Jul 27 04:59:53 PM PDT 24	Jul 27 05:01:31 PM PDT 24	1329556664 ps
T25	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1071799989	Jul 27 05:00:30 PM PDT 24	Jul 27 05:00:59 PM PDT 24	4438629324 ps
T105	/workspace/coverage/default/15.sram_ctrl_mem_walk.2474308203	Jul 27 05:00:12 PM PDT 24	Jul 27 05:00:20 PM PDT 24	135054338 ps
T94	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3759612305	Jul 27 05:00:00 PM PDT 24	Jul 27 05:07:09 PM PDT 24	16673560185 ps
T78	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1159002161	Jul 27 04:59:51 PM PDT 24	Jul 27 04:59:54 PM PDT 24	45743528 ps
T95	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2006833164	Jul 27 05:01:18 PM PDT 24	Jul 27 05:04:26 PM PDT 24	11599518882 ps
T106	/workspace/coverage/default/40.sram_ctrl_partial_access.2539412873	Jul 27 05:01:22 PM PDT 24	Jul 27 05:01:23 PM PDT 24	77485962 ps
T47	/workspace/coverage/default/38.sram_ctrl_mem_walk.793295088	Jul 27 05:01:10 PM PDT 24	Jul 27 05:01:21 PM PDT 24	453274938 ps
T107	/workspace/coverage/default/4.sram_ctrl_partial_access.3847696837	Jul 27 04:59:42 PM PDT 24	Jul 27 04:59:59 PM PDT 24	4257916635 ps
T108	/workspace/coverage/default/48.sram_ctrl_executable.894984438	Jul 27 05:01:57 PM PDT 24	Jul 27 05:23:54 PM PDT 24	202967477588 ps
T48	/workspace/coverage/default/17.sram_ctrl_mem_walk.2098450222	Jul 27 05:00:17 PM PDT 24	Jul 27 05:00:22 PM PDT 24	92782022 ps
T127	/workspace/coverage/default/48.sram_ctrl_partial_access.2888667664	Jul 27 05:01:47 PM PDT 24	Jul 27 05:01:58 PM PDT 24	2167358779 ps
T132	/workspace/coverage/default/0.sram_ctrl_bijection.2536269448	Jul 27 04:59:22 PM PDT 24	Jul 27 04:59:50 PM PDT 24	3621382724 ps
T131	/workspace/coverage/default/30.sram_ctrl_smoke.2061507626	Jul 27 05:00:44 PM PDT 24	Jul 27 05:00:51 PM PDT 24	121362655 ps
T43	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.956738432	Jul 27 05:00:23 PM PDT 24	Jul 27 05:00:28 PM PDT 24	97934997 ps
T96	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1146020273	Jul 27 05:00:25 PM PDT 24	Jul 27 05:03:32 PM PDT 24	25922440166 ps
T16	/workspace/coverage/default/20.sram_ctrl_alert_test.2552791509	Jul 27 05:00:02 PM PDT 24	Jul 27 05:00:02 PM PDT 24	54621201 ps
T21	/workspace/coverage/default/14.sram_ctrl_stress_all.1890736004	Jul 27 05:00:26 PM PDT 24	Jul 27 05:41:14 PM PDT 24	120089617085 ps
T26	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1718018802	Jul 27 05:01:32 PM PDT 24	Jul 27 05:02:12 PM PDT 24	537994351 ps
T79	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1777620534	Jul 27 05:00:53 PM PDT 24	Jul 27 05:00:56 PM PDT 24	542294252 ps
T49	/workspace/coverage/default/30.sram_ctrl_mem_walk.2217474971	Jul 27 05:00:52 PM PDT 24	Jul 27 05:01:03 PM PDT 24	1163312965 ps
T123	/workspace/coverage/default/24.sram_ctrl_executable.911537964	Jul 27 05:00:28 PM PDT 24	Jul 27 05:12:52 PM PDT 24	4071608389 ps
T17	/workspace/coverage/default/28.sram_ctrl_alert_test.961569696	Jul 27 05:00:31 PM PDT 24	Jul 27 05:00:32 PM PDT 24	17818639 ps
T80	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1008120170	Jul 27 04:59:51 PM PDT 24	Jul 27 04:59:56 PM PDT 24	168364283 ps
T125	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2360050896	Jul 27 05:01:05 PM PDT 24	Jul 27 05:06:49 PM PDT 24	59650304392 ps
T137	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.198086394	Jul 27 05:01:22 PM PDT 24	Jul 27 05:06:09 PM PDT 24	12392636603 ps
T124	/workspace/coverage/default/11.sram_ctrl_executable.1529251522	Jul 27 04:59:52 PM PDT 24	Jul 27 05:16:17 PM PDT 24	16445734144 ps
T133	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3846789588	Jul 27 05:00:29 PM PDT 24	Jul 27 05:04:03 PM PDT 24	31912077252 ps
T138	/workspace/coverage/default/15.sram_ctrl_ram_cfg.3905663499	Jul 27 05:00:24 PM PDT 24	Jul 27 05:00:25 PM PDT 24	28716574 ps
T44	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1249811188	Jul 27 05:01:45 PM PDT 24	Jul 27 05:01:49 PM PDT 24	1136299908 ps
T50	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2628397078	Jul 27 04:59:52 PM PDT 24	Jul 27 05:04:54 PM PDT 24	11467851606 ps
T46	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.4019771875	Jul 27 04:59:57 PM PDT 24	Jul 27 05:08:12 PM PDT 24	13846712483 ps
T139	/workspace/coverage/default/6.sram_ctrl_ram_cfg.3478593890	Jul 27 04:59:45 PM PDT 24	Jul 27 04:59:45 PM PDT 24	42186819 ps
T140	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3550321938	Jul 27 05:00:28 PM PDT 24	Jul 27 05:02:29 PM PDT 24	309208684 ps
T18	/workspace/coverage/default/1.sram_ctrl_sec_cm.4065580393	Jul 27 04:59:50 PM PDT 24	Jul 27 04:59:53 PM PDT 24	439535016 ps
T141	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1873631947	Jul 27 05:01:47 PM PDT 24	Jul 27 05:04:30 PM PDT 24	14343459916 ps
T142	/workspace/coverage/default/43.sram_ctrl_alert_test.1652512341	Jul 27 05:01:28 PM PDT 24	Jul 27 05:01:28 PM PDT 24	12505959 ps
T143	/workspace/coverage/default/13.sram_ctrl_alert_test.2319456423	Jul 27 05:00:12 PM PDT 24	Jul 27 05:00:13 PM PDT 24	21730800 ps
T126	/workspace/coverage/default/23.sram_ctrl_executable.2915807303	Jul 27 05:00:33 PM PDT 24	Jul 27 05:18:45 PM PDT 24	51430260995 ps
T39	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3873257587	Jul 27 05:01:16 PM PDT 24	Jul 27 05:09:58 PM PDT 24	13845325057 ps
T144	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2378210066	Jul 27 05:01:01 PM PDT 24	Jul 27 05:01:59 PM PDT 24	115655739 ps
T145	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3400229172	Jul 27 05:00:01 PM PDT 24	Jul 27 05:06:18 PM PDT 24	7923841427 ps
T128	/workspace/coverage/default/4.sram_ctrl_max_throughput.2177318024	Jul 27 04:59:42 PM PDT 24	Jul 27 05:01:44 PM PDT 24	245269429 ps
T146	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2583192547	Jul 27 04:59:55 PM PDT 24	Jul 27 05:05:06 PM PDT 24	13099120048 ps
T51	/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3195089547	Jul 27 05:01:45 PM PDT 24	Jul 27 05:09:31 PM PDT 24	1399541513 ps
T147	/workspace/coverage/default/49.sram_ctrl_multiple_keys.693719977	Jul 27 05:01:57 PM PDT 24	Jul 27 05:11:38 PM PDT 24	8226301502 ps
T148	/workspace/coverage/default/39.sram_ctrl_max_throughput.2024977743	Jul 27 05:01:07 PM PDT 24	Jul 27 05:01:25 PM PDT 24	275823090 ps
T149	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.414371621	Jul 27 05:00:02 PM PDT 24	Jul 27 05:04:24 PM PDT 24	51428232221 ps
T40	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3296621550	Jul 27 05:01:20 PM PDT 24	Jul 27 05:18:31 PM PDT 24	3476929846 ps
T134	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3056445740	Jul 27 05:01:19 PM PDT 24	Jul 27 05:07:20 PM PDT 24	15040741770 ps
T150	/workspace/coverage/default/14.sram_ctrl_mem_walk.4265222633	Jul 27 05:00:05 PM PDT 24	Jul 27 05:00:15 PM PDT 24	158252292 ps
T45	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3111626267	Jul 27 05:00:43 PM PDT 24	Jul 27 05:00:47 PM PDT 24	375140885 ps
T151	/workspace/coverage/default/1.sram_ctrl_max_throughput.2835167024	Jul 27 04:59:50 PM PDT 24	Jul 27 05:02:05 PM PDT 24	762555977 ps
T59	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3529446446	Jul 27 05:00:54 PM PDT 24	Jul 27 05:06:26 PM PDT 24	1209433160 ps
T152	/workspace/coverage/default/5.sram_ctrl_alert_test.2478058897	Jul 27 04:59:46 PM PDT 24	Jul 27 04:59:47 PM PDT 24	48059861 ps
T22	/workspace/coverage/default/17.sram_ctrl_stress_all.2767706309	Jul 27 05:00:13 PM PDT 24	Jul 27 06:18:46 PM PDT 24	21490804601 ps
T52	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.449186651	Jul 27 05:00:12 PM PDT 24	Jul 27 05:06:09 PM PDT 24	4908346881 ps
T153	/workspace/coverage/default/33.sram_ctrl_alert_test.3007588081	Jul 27 05:00:56 PM PDT 24	Jul 27 05:00:57 PM PDT 24	18299667 ps
T154	/workspace/coverage/default/22.sram_ctrl_max_throughput.294716353	Jul 27 05:00:36 PM PDT 24	Jul 27 05:01:25 PM PDT 24	1295665161 ps
T23	/workspace/coverage/default/18.sram_ctrl_lc_escalation.1240821856	Jul 27 05:00:15 PM PDT 24	Jul 27 05:00:21 PM PDT 24	720367331 ps
T155	/workspace/coverage/default/37.sram_ctrl_stress_all.1735005843	Jul 27 05:01:07 PM PDT 24	Jul 27 06:26:59 PM PDT 24	15087069137 ps
T109	/workspace/coverage/default/48.sram_ctrl_lc_escalation.1027725849	Jul 27 05:01:46 PM PDT 24	Jul 27 05:01:48 PM PDT 24	63370265 ps
T156	/workspace/coverage/default/45.sram_ctrl_mem_walk.421070884	Jul 27 05:01:39 PM PDT 24	Jul 27 05:01:50 PM PDT 24	468855403 ps
T157	/workspace/coverage/default/11.sram_ctrl_mem_walk.3475718952	Jul 27 04:59:58 PM PDT 24	Jul 27 05:00:05 PM PDT 24	1370909974 ps
T158	/workspace/coverage/default/30.sram_ctrl_alert_test.1487294978	Jul 27 05:00:58 PM PDT 24	Jul 27 05:00:58 PM PDT 24	13920505 ps
T159	/workspace/coverage/default/14.sram_ctrl_smoke.2380504916	Jul 27 05:00:19 PM PDT 24	Jul 27 05:00:32 PM PDT 24	400296427 ps
T160	/workspace/coverage/default/7.sram_ctrl_regwen.2263706609	Jul 27 04:59:51 PM PDT 24	Jul 27 05:29:02 PM PDT 24	11844123947 ps
T161	/workspace/coverage/default/13.sram_ctrl_mem_walk.3875733582	Jul 27 04:59:58 PM PDT 24	Jul 27 05:00:10 PM PDT 24	2742722097 ps
T162	/workspace/coverage/default/5.sram_ctrl_stress_all.3774627686	Jul 27 04:59:43 PM PDT 24	Jul 27 05:12:51 PM PDT 24	50176463923 ps
T163	/workspace/coverage/default/42.sram_ctrl_lc_escalation.4283434545	Jul 27 05:01:24 PM PDT 24	Jul 27 05:01:33 PM PDT 24	932909477 ps
T164	/workspace/coverage/default/45.sram_ctrl_executable.3190234289	Jul 27 05:01:37 PM PDT 24	Jul 27 05:11:30 PM PDT 24	6955404948 ps
T19	/workspace/coverage/default/3.sram_ctrl_sec_cm.89665282	Jul 27 04:59:50 PM PDT 24	Jul 27 04:59:52 PM PDT 24	356557168 ps
T165	/workspace/coverage/default/33.sram_ctrl_mem_walk.886782406	Jul 27 05:00:51 PM PDT 24	Jul 27 05:01:03 PM PDT 24	2487821734 ps
T166	/workspace/coverage/default/4.sram_ctrl_multiple_keys.3435239376	Jul 27 04:59:36 PM PDT 24	Jul 27 05:03:11 PM PDT 24	20280558180 ps
T167	/workspace/coverage/default/34.sram_ctrl_ram_cfg.1007625990	Jul 27 05:00:58 PM PDT 24	Jul 27 05:00:59 PM PDT 24	52540846 ps
T168	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1871884207	Jul 27 04:59:59 PM PDT 24	Jul 27 05:00:00 PM PDT 24	77101358 ps
T169	/workspace/coverage/default/22.sram_ctrl_alert_test.2427872605	Jul 27 05:00:22 PM PDT 24	Jul 27 05:00:27 PM PDT 24	20398867 ps
T170	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2429725588	Jul 27 04:59:32 PM PDT 24	Jul 27 05:00:26 PM PDT 24	808773445 ps
T171	/workspace/coverage/default/3.sram_ctrl_mem_walk.1681942368	Jul 27 04:59:49 PM PDT 24	Jul 27 05:00:00 PM PDT 24	456075035 ps
T172	/workspace/coverage/default/44.sram_ctrl_executable.2818308413	Jul 27 05:01:39 PM PDT 24	Jul 27 05:11:48 PM PDT 24	2831083683 ps
T173	/workspace/coverage/default/22.sram_ctrl_mem_walk.2479168305	Jul 27 05:00:29 PM PDT 24	Jul 27 05:00:35 PM PDT 24	181388599 ps
T174	/workspace/coverage/default/25.sram_ctrl_max_throughput.1530243449	Jul 27 05:00:25 PM PDT 24	Jul 27 05:00:34 PM PDT 24	229226662 ps
T175	/workspace/coverage/default/0.sram_ctrl_partial_access.2702699133	Jul 27 04:59:35 PM PDT 24	Jul 27 04:59:53 PM PDT 24	140514849 ps
T176	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4040773476	Jul 27 04:59:57 PM PDT 24	Jul 27 05:00:05 PM PDT 24	249571353 ps
T177	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1316840444	Jul 27 04:59:49 PM PDT 24	Jul 27 05:03:41 PM PDT 24	3259291842 ps
T178	/workspace/coverage/default/42.sram_ctrl_smoke.144021869	Jul 27 05:01:20 PM PDT 24	Jul 27 05:01:35 PM PDT 24	387479974 ps
T179	/workspace/coverage/default/22.sram_ctrl_partial_access.2180465250	Jul 27 05:00:07 PM PDT 24	Jul 27 05:00:27 PM PDT 24	2004512350 ps
T180	/workspace/coverage/default/8.sram_ctrl_smoke.1231480825	Jul 27 04:59:37 PM PDT 24	Jul 27 04:59:47 PM PDT 24	197994288 ps
T181	/workspace/coverage/default/23.sram_ctrl_max_throughput.2792144641	Jul 27 05:00:29 PM PDT 24	Jul 27 05:02:14 PM PDT 24	504935876 ps
T182	/workspace/coverage/default/19.sram_ctrl_max_throughput.2301843785	Jul 27 05:00:24 PM PDT 24	Jul 27 05:00:56 PM PDT 24	176151269 ps
T60	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.52124858	Jul 27 05:01:19 PM PDT 24	Jul 27 05:01:30 PM PDT 24	359832532 ps
T183	/workspace/coverage/default/48.sram_ctrl_ram_cfg.3407796261	Jul 27 05:01:56 PM PDT 24	Jul 27 05:01:57 PM PDT 24	123173556 ps
T184	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1760102307	Jul 27 05:01:31 PM PDT 24	Jul 27 05:05:18 PM PDT 24	2384731301 ps
T185	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1603127661	Jul 27 04:59:50 PM PDT 24	Jul 27 05:09:28 PM PDT 24	1655948461 ps
T186	/workspace/coverage/default/11.sram_ctrl_alert_test.497656164	Jul 27 05:00:05 PM PDT 24	Jul 27 05:00:07 PM PDT 24	32763595 ps
T187	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3028474664	Jul 27 05:00:41 PM PDT 24	Jul 27 05:07:11 PM PDT 24	14789715928 ps
T24	/workspace/coverage/default/45.sram_ctrl_lc_escalation.3826021114	Jul 27 05:01:39 PM PDT 24	Jul 27 05:01:45 PM PDT 24	427106934 ps
T188	/workspace/coverage/default/18.sram_ctrl_partial_access.1346970928	Jul 27 05:00:25 PM PDT 24	Jul 27 05:00:42 PM PDT 24	601651506 ps
T189	/workspace/coverage/default/49.sram_ctrl_ram_cfg.2375453398	Jul 27 05:01:57 PM PDT 24	Jul 27 05:01:58 PM PDT 24	77947091 ps
T190	/workspace/coverage/default/31.sram_ctrl_alert_test.3453900439	Jul 27 05:00:47 PM PDT 24	Jul 27 05:00:48 PM PDT 24	34765137 ps
T191	/workspace/coverage/default/45.sram_ctrl_alert_test.137088360	Jul 27 05:01:39 PM PDT 24	Jul 27 05:01:40 PM PDT 24	21462952 ps
T192	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.3093801432	Jul 27 05:00:16 PM PDT 24	Jul 27 05:16:27 PM PDT 24	5978720309 ps
T193	/workspace/coverage/default/28.sram_ctrl_regwen.2018248109	Jul 27 05:00:37 PM PDT 24	Jul 27 05:13:47 PM PDT 24	30045102154 ps
T194	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3434744780	Jul 27 04:59:38 PM PDT 24	Jul 27 04:59:42 PM PDT 24	129096438 ps
T195	/workspace/coverage/default/38.sram_ctrl_partial_access.194678667	Jul 27 05:01:15 PM PDT 24	Jul 27 05:01:17 PM PDT 24	112543552 ps
T196	/workspace/coverage/default/44.sram_ctrl_ram_cfg.2046104804	Jul 27 05:01:35 PM PDT 24	Jul 27 05:01:36 PM PDT 24	87637843 ps
T197	/workspace/coverage/default/9.sram_ctrl_multiple_keys.3171388852	Jul 27 04:59:48 PM PDT 24	Jul 27 05:06:14 PM PDT 24	2318951101 ps
T198	/workspace/coverage/default/22.sram_ctrl_multiple_keys.1665337129	Jul 27 05:00:19 PM PDT 24	Jul 27 05:11:45 PM PDT 24	6602000191 ps
T199	/workspace/coverage/default/11.sram_ctrl_ram_cfg.3145393630	Jul 27 04:59:56 PM PDT 24	Jul 27 04:59:57 PM PDT 24	85376100 ps
T61	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.910013055	Jul 27 05:00:16 PM PDT 24	Jul 27 05:08:14 PM PDT 24	3523928393 ps
T200	/workspace/coverage/default/0.sram_ctrl_alert_test.1987713705	Jul 27 04:59:36 PM PDT 24	Jul 27 04:59:36 PM PDT 24	30326535 ps
T201	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1386740000	Jul 27 05:01:58 PM PDT 24	Jul 27 05:02:04 PM PDT 24	321413982 ps
T202	/workspace/coverage/default/38.sram_ctrl_regwen.3118497960	Jul 27 05:01:13 PM PDT 24	Jul 27 05:16:35 PM PDT 24	18176506976 ps
T203	/workspace/coverage/default/40.sram_ctrl_multiple_keys.745207744	Jul 27 05:01:17 PM PDT 24	Jul 27 05:09:26 PM PDT 24	2471011153 ps
T204	/workspace/coverage/default/39.sram_ctrl_stress_all.2519339981	Jul 27 05:01:17 PM PDT 24	Jul 27 05:12:09 PM PDT 24	8796043058 ps
T205	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.122312051	Jul 27 05:00:02 PM PDT 24	Jul 27 05:04:54 PM PDT 24	5444388055 ps
T206	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2505829410	Jul 27 04:59:57 PM PDT 24	Jul 27 05:19:18 PM PDT 24	2901191918 ps
T207	/workspace/coverage/default/36.sram_ctrl_executable.3606160736	Jul 27 05:01:05 PM PDT 24	Jul 27 05:06:04 PM PDT 24	7634492845 ps
T208	/workspace/coverage/default/44.sram_ctrl_stress_all.881039501	Jul 27 05:01:38 PM PDT 24	Jul 27 05:50:26 PM PDT 24	639059348754 ps
T209	/workspace/coverage/default/41.sram_ctrl_max_throughput.2736346780	Jul 27 05:01:16 PM PDT 24	Jul 27 05:01:18 PM PDT 24	123243179 ps
T210	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2348024258	Jul 27 05:00:32 PM PDT 24	Jul 27 05:02:42 PM PDT 24	664505650 ps
T211	/workspace/coverage/default/16.sram_ctrl_regwen.3271787433	Jul 27 05:00:09 PM PDT 24	Jul 27 05:04:31 PM PDT 24	12396330922 ps
T212	/workspace/coverage/default/41.sram_ctrl_ram_cfg.3524743173	Jul 27 05:01:20 PM PDT 24	Jul 27 05:01:21 PM PDT 24	87656477 ps
T213	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1312179921	Jul 27 05:00:34 PM PDT 24	Jul 27 05:05:07 PM PDT 24	14777762331 ps
T214	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3768826132	Jul 27 05:01:36 PM PDT 24	Jul 27 05:04:32 PM PDT 24	3807586456 ps
T215	/workspace/coverage/default/30.sram_ctrl_partial_access.1748001643	Jul 27 05:00:32 PM PDT 24	Jul 27 05:01:48 PM PDT 24	561760397 ps
T216	/workspace/coverage/default/20.sram_ctrl_max_throughput.2949634585	Jul 27 05:00:21 PM PDT 24	Jul 27 05:01:38 PM PDT 24	165687773 ps
T217	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3100873467	Jul 27 05:00:30 PM PDT 24	Jul 27 05:18:09 PM PDT 24	18819198307 ps
T218	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.1072749133	Jul 27 05:01:00 PM PDT 24	Jul 27 05:01:05 PM PDT 24	177927070 ps
T219	/workspace/coverage/default/36.sram_ctrl_alert_test.377440885	Jul 27 05:00:59 PM PDT 24	Jul 27 05:01:00 PM PDT 24	17435773 ps
T220	/workspace/coverage/default/13.sram_ctrl_smoke.2692133812	Jul 27 04:59:56 PM PDT 24	Jul 27 05:00:06 PM PDT 24	666189835 ps
T221	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3142149775	Jul 27 05:00:54 PM PDT 24	Jul 27 05:05:24 PM PDT 24	2797403766 ps
T222	/workspace/coverage/default/32.sram_ctrl_ram_cfg.1145388729	Jul 27 05:00:53 PM PDT 24	Jul 27 05:00:54 PM PDT 24	38405080 ps
T223	/workspace/coverage/default/15.sram_ctrl_executable.1586161243	Jul 27 05:00:08 PM PDT 24	Jul 27 05:09:03 PM PDT 24	15851196241 ps
T224	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2216848255	Jul 27 05:00:08 PM PDT 24	Jul 27 05:06:00 PM PDT 24	20244386712 ps
T225	/workspace/coverage/default/26.sram_ctrl_lc_escalation.1870570383	Jul 27 05:00:29 PM PDT 24	Jul 27 05:00:36 PM PDT 24	1970919863 ps
T226	/workspace/coverage/default/32.sram_ctrl_max_throughput.1729909132	Jul 27 05:00:53 PM PDT 24	Jul 27 05:00:55 PM PDT 24	77028430 ps
T227	/workspace/coverage/default/2.sram_ctrl_ram_cfg.3995861974	Jul 27 04:59:52 PM PDT 24	Jul 27 04:59:53 PM PDT 24	34953607 ps
T228	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1997491698	Jul 27 05:00:04 PM PDT 24	Jul 27 05:04:38 PM PDT 24	3851473052 ps
T229	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.408259348	Jul 27 05:00:31 PM PDT 24	Jul 27 05:15:48 PM PDT 24	3771754010 ps
T230	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1165351324	Jul 27 04:59:56 PM PDT 24	Jul 27 05:01:28 PM PDT 24	1909818841 ps
T231	/workspace/coverage/default/7.sram_ctrl_alert_test.3147778857	Jul 27 04:59:47 PM PDT 24	Jul 27 04:59:48 PM PDT 24	147546686 ps
T232	/workspace/coverage/default/9.sram_ctrl_alert_test.3230037924	Jul 27 05:00:03 PM PDT 24	Jul 27 05:00:07 PM PDT 24	45509218 ps
T233	/workspace/coverage/default/23.sram_ctrl_lc_escalation.624202227	Jul 27 05:00:31 PM PDT 24	Jul 27 05:00:36 PM PDT 24	395279423 ps
T234	/workspace/coverage/default/7.sram_ctrl_lc_escalation.1851592602	Jul 27 05:00:09 PM PDT 24	Jul 27 05:00:15 PM PDT 24	596082081 ps
T235	/workspace/coverage/default/17.sram_ctrl_ram_cfg.1567290845	Jul 27 05:00:28 PM PDT 24	Jul 27 05:00:29 PM PDT 24	115889069 ps
T236	/workspace/coverage/default/30.sram_ctrl_regwen.1908074646	Jul 27 05:00:35 PM PDT 24	Jul 27 05:25:42 PM PDT 24	63221971038 ps
T237	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2996957259	Jul 27 04:59:48 PM PDT 24	Jul 27 05:07:36 PM PDT 24	24824092829 ps
T238	/workspace/coverage/default/4.sram_ctrl_smoke.841425255	Jul 27 04:59:35 PM PDT 24	Jul 27 04:59:37 PM PDT 24	89538750 ps
T239	/workspace/coverage/default/43.sram_ctrl_mem_walk.1233617614	Jul 27 05:01:28 PM PDT 24	Jul 27 05:01:33 PM PDT 24	75045033 ps
T240	/workspace/coverage/default/46.sram_ctrl_ram_cfg.2664892647	Jul 27 05:01:44 PM PDT 24	Jul 27 05:01:45 PM PDT 24	48231109 ps
T241	/workspace/coverage/default/41.sram_ctrl_executable.916299708	Jul 27 05:01:22 PM PDT 24	Jul 27 05:13:11 PM PDT 24	1734673974 ps
T242	/workspace/coverage/default/24.sram_ctrl_mem_walk.346107075	Jul 27 05:00:27 PM PDT 24	Jul 27 05:00:36 PM PDT 24	465151662 ps
T243	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2270168076	Jul 27 05:00:16 PM PDT 24	Jul 27 05:04:39 PM PDT 24	141744422275 ps
T244	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2210265574	Jul 27 05:00:29 PM PDT 24	Jul 27 05:07:11 PM PDT 24	38746775265 ps
T245	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1236526801	Jul 27 05:00:27 PM PDT 24	Jul 27 05:01:42 PM PDT 24	140678394 ps
T246	/workspace/coverage/default/23.sram_ctrl_smoke.2964791253	Jul 27 05:00:25 PM PDT 24	Jul 27 05:00:28 PM PDT 24	87627090 ps
T247	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3537539213	Jul 27 05:01:37 PM PDT 24	Jul 27 05:01:40 PM PDT 24	49606257 ps
T248	/workspace/coverage/default/21.sram_ctrl_alert_test.2463235300	Jul 27 05:00:24 PM PDT 24	Jul 27 05:00:25 PM PDT 24	15639693 ps
T249	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.666812457	Jul 27 04:59:33 PM PDT 24	Jul 27 05:03:16 PM PDT 24	2371458946 ps
T250	/workspace/coverage/default/2.sram_ctrl_max_throughput.3360041153	Jul 27 04:59:42 PM PDT 24	Jul 27 05:00:11 PM PDT 24	178491741 ps
T251	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3199236564	Jul 27 05:00:53 PM PDT 24	Jul 27 05:08:38 PM PDT 24	13330617676 ps
T252	/workspace/coverage/default/8.sram_ctrl_ram_cfg.2068398127	Jul 27 04:59:53 PM PDT 24	Jul 27 04:59:54 PM PDT 24	29994043 ps
T253	/workspace/coverage/default/36.sram_ctrl_partial_access.537373152	Jul 27 05:01:01 PM PDT 24	Jul 27 05:02:50 PM PDT 24	659675330 ps
T254	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.4256894381	Jul 27 04:59:15 PM PDT 24	Jul 27 05:13:33 PM PDT 24	27170219349 ps
T255	/workspace/coverage/default/4.sram_ctrl_ram_cfg.205717597	Jul 27 04:59:41 PM PDT 24	Jul 27 04:59:42 PM PDT 24	26456838 ps
T256	/workspace/coverage/default/42.sram_ctrl_max_throughput.264226175	Jul 27 05:01:19 PM PDT 24	Jul 27 05:01:20 PM PDT 24	34273363 ps
T257	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.159777122	Jul 27 04:59:59 PM PDT 24	Jul 27 05:00:30 PM PDT 24	406825808 ps
T258	/workspace/coverage/default/21.sram_ctrl_regwen.2756837943	Jul 27 05:00:20 PM PDT 24	Jul 27 05:14:38 PM PDT 24	11967967625 ps
T259	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2240324846	Jul 27 05:01:18 PM PDT 24	Jul 27 05:01:23 PM PDT 24	275067411 ps
T260	/workspace/coverage/default/10.sram_ctrl_max_throughput.3712260792	Jul 27 05:00:00 PM PDT 24	Jul 27 05:00:35 PM PDT 24	251508973 ps
T261	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3002638689	Jul 27 05:01:56 PM PDT 24	Jul 27 05:02:02 PM PDT 24	187361380 ps
T262	/workspace/coverage/default/45.sram_ctrl_multiple_keys.3024650256	Jul 27 05:01:35 PM PDT 24	Jul 27 05:09:42 PM PDT 24	10365690039 ps
T263	/workspace/coverage/default/34.sram_ctrl_executable.2401518541	Jul 27 05:01:02 PM PDT 24	Jul 27 05:15:40 PM PDT 24	11623034700 ps
T264	/workspace/coverage/default/35.sram_ctrl_multiple_keys.1428786551	Jul 27 05:00:49 PM PDT 24	Jul 27 05:02:37 PM PDT 24	1517335902 ps
T265	/workspace/coverage/default/31.sram_ctrl_mem_walk.1760475470	Jul 27 05:00:53 PM PDT 24	Jul 27 05:01:04 PM PDT 24	922531905 ps
T266	/workspace/coverage/default/6.sram_ctrl_mem_walk.3217009610	Jul 27 04:59:49 PM PDT 24	Jul 27 04:59:58 PM PDT 24	346415036 ps
T267	/workspace/coverage/default/11.sram_ctrl_smoke.361170685	Jul 27 04:59:55 PM PDT 24	Jul 27 04:59:59 PM PDT 24	121285179 ps
T268	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.478626846	Jul 27 04:59:40 PM PDT 24	Jul 27 04:59:45 PM PDT 24	754905226 ps
T269	/workspace/coverage/default/26.sram_ctrl_smoke.2290740768	Jul 27 05:00:28 PM PDT 24	Jul 27 05:01:14 PM PDT 24	444649630 ps
T270	/workspace/coverage/default/44.sram_ctrl_bijection.378308275	Jul 27 05:01:29 PM PDT 24	Jul 27 05:02:11 PM PDT 24	2547502720 ps
T271	/workspace/coverage/default/37.sram_ctrl_multiple_keys.836609678	Jul 27 05:01:03 PM PDT 24	Jul 27 05:19:45 PM PDT 24	17558342054 ps
T272	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4136910324	Jul 27 04:59:46 PM PDT 24	Jul 27 05:03:46 PM PDT 24	17604476417 ps
T273	/workspace/coverage/default/16.sram_ctrl_mem_walk.560119704	Jul 27 05:00:54 PM PDT 24	Jul 27 05:01:03 PM PDT 24	183286528 ps
T274	/workspace/coverage/default/25.sram_ctrl_mem_walk.2761615915	Jul 27 05:00:25 PM PDT 24	Jul 27 05:00:29 PM PDT 24	143964350 ps
T275	/workspace/coverage/default/37.sram_ctrl_mem_walk.3597027431	Jul 27 05:01:05 PM PDT 24	Jul 27 05:01:16 PM PDT 24	287254046 ps
T29	/workspace/coverage/default/0.sram_ctrl_sec_cm.1834919438	Jul 27 04:59:37 PM PDT 24	Jul 27 04:59:39 PM PDT 24	180465706 ps
T276	/workspace/coverage/default/26.sram_ctrl_stress_all.3080790777	Jul 27 05:00:37 PM PDT 24	Jul 27 05:54:08 PM PDT 24	79944874886 ps
T277	/workspace/coverage/default/23.sram_ctrl_stress_all.2067990515	Jul 27 05:00:27 PM PDT 24	Jul 27 05:19:36 PM PDT 24	69368325315 ps
T278	/workspace/coverage/default/41.sram_ctrl_stress_all.1163499197	Jul 27 05:01:18 PM PDT 24	Jul 27 06:30:49 PM PDT 24	197886623167 ps
T279	/workspace/coverage/default/11.sram_ctrl_max_throughput.2317689190	Jul 27 04:59:50 PM PDT 24	Jul 27 05:00:51 PM PDT 24	119758464 ps
T280	/workspace/coverage/default/16.sram_ctrl_ram_cfg.2930792293	Jul 27 05:00:02 PM PDT 24	Jul 27 05:00:07 PM PDT 24	51571720 ps
T281	/workspace/coverage/default/5.sram_ctrl_bijection.1951436199	Jul 27 04:59:46 PM PDT 24	Jul 27 05:00:09 PM PDT 24	3921887045 ps
T282	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2675785766	Jul 27 05:00:55 PM PDT 24	Jul 27 05:02:50 PM PDT 24	1286593109 ps
T283	/workspace/coverage/default/31.sram_ctrl_partial_access.4233209994	Jul 27 05:00:44 PM PDT 24	Jul 27 05:00:54 PM PDT 24	679142934 ps
T284	/workspace/coverage/default/15.sram_ctrl_max_throughput.2602771832	Jul 27 05:00:17 PM PDT 24	Jul 27 05:02:34 PM PDT 24	141379536 ps
T285	/workspace/coverage/default/4.sram_ctrl_stress_all.3692450907	Jul 27 04:59:49 PM PDT 24	Jul 27 05:02:39 PM PDT 24	12148695995 ps
T286	/workspace/coverage/default/15.sram_ctrl_regwen.874993802	Jul 27 04:59:52 PM PDT 24	Jul 27 05:02:09 PM PDT 24	1616085785 ps
T287	/workspace/coverage/default/41.sram_ctrl_multiple_keys.4260163865	Jul 27 05:01:21 PM PDT 24	Jul 27 05:13:43 PM PDT 24	16550176029 ps
T288	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.824125511	Jul 27 05:00:17 PM PDT 24	Jul 27 05:00:22 PM PDT 24	207575026 ps
T289	/workspace/coverage/default/34.sram_ctrl_alert_test.847901325	Jul 27 05:00:54 PM PDT 24	Jul 27 05:00:55 PM PDT 24	39408078 ps
T290	/workspace/coverage/default/17.sram_ctrl_alert_test.3506364378	Jul 27 05:00:17 PM PDT 24	Jul 27 05:00:18 PM PDT 24	47451685 ps
T291	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2794983854	Jul 27 05:00:32 PM PDT 24	Jul 27 05:13:50 PM PDT 24	15007799243 ps
T292	/workspace/coverage/default/18.sram_ctrl_alert_test.2354433679	Jul 27 05:00:36 PM PDT 24	Jul 27 05:00:37 PM PDT 24	15700282 ps
T293	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.744757485	Jul 27 05:00:28 PM PDT 24	Jul 27 05:03:48 PM PDT 24	2652771027 ps
T294	/workspace/coverage/default/5.sram_ctrl_mem_walk.4245984318	Jul 27 04:59:31 PM PDT 24	Jul 27 04:59:39 PM PDT 24	136831232 ps
T295	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1761147815	Jul 27 05:00:32 PM PDT 24	Jul 27 05:05:21 PM PDT 24	19620457267 ps
T296	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.182803474	Jul 27 05:00:21 PM PDT 24	Jul 27 05:00:27 PM PDT 24	1156515658 ps
T297	/workspace/coverage/default/6.sram_ctrl_bijection.4087471425	Jul 27 05:00:03 PM PDT 24	Jul 27 05:00:59 PM PDT 24	10305608402 ps
T298	/workspace/coverage/default/8.sram_ctrl_mem_walk.4251249529	Jul 27 05:00:11 PM PDT 24	Jul 27 05:00:23 PM PDT 24	1313055221 ps
T97	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3606112429	Jul 27 05:00:27 PM PDT 24	Jul 27 05:01:09 PM PDT 24	2038814563 ps
T299	/workspace/coverage/default/36.sram_ctrl_stress_all.1800761329	Jul 27 05:00:57 PM PDT 24	Jul 27 05:16:20 PM PDT 24	11055707225 ps
T300	/workspace/coverage/default/3.sram_ctrl_stress_all.1409189699	Jul 27 04:59:54 PM PDT 24	Jul 27 05:12:35 PM PDT 24	28547931373 ps
T301	/workspace/coverage/default/25.sram_ctrl_smoke.3658785966	Jul 27 05:00:40 PM PDT 24	Jul 27 05:00:52 PM PDT 24	531736930 ps
T302	/workspace/coverage/default/36.sram_ctrl_regwen.1232484528	Jul 27 05:01:04 PM PDT 24	Jul 27 05:23:27 PM PDT 24	3791776454 ps
T303	/workspace/coverage/default/40.sram_ctrl_mem_walk.3902861850	Jul 27 05:01:20 PM PDT 24	Jul 27 05:01:25 PM PDT 24	631774008 ps
T304	/workspace/coverage/default/47.sram_ctrl_alert_test.916802347	Jul 27 05:01:43 PM PDT 24	Jul 27 05:01:44 PM PDT 24	16843651 ps
T305	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3923613647	Jul 27 05:01:37 PM PDT 24	Jul 27 05:17:52 PM PDT 24	3544478151 ps
T306	/workspace/coverage/default/35.sram_ctrl_alert_test.419602909	Jul 27 05:00:58 PM PDT 24	Jul 27 05:00:59 PM PDT 24	15635761 ps
T307	/workspace/coverage/default/19.sram_ctrl_stress_all.820091336	Jul 27 05:00:20 PM PDT 24	Jul 27 05:52:55 PM PDT 24	40933117024 ps
T308	/workspace/coverage/default/14.sram_ctrl_lc_escalation.2886856742	Jul 27 05:00:02 PM PDT 24	Jul 27 05:00:14 PM PDT 24	1002864353 ps