Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	43173903	1			T1	25797		T2	6142		T3	29828
triple_byte_access	2449293	1			T1	436		T3	622		T5	252
halfword_access	3678799	1			T1	706		T3	891		T5	425
byte_access	4913053	1			T1	942		T3	1239		T5	762
zero_access	1237895	1			T1	233		T3	290		T5	422

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27671463

1

T1

13864

T2

2048

T3

16488

auto[1]

27781480

1

T1

14250

T2

4094

T3

16382

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21534627	1			T1	12710		T2	2048		T3	14982
auto[0]	triple_byte_access	1222601	1			T1	213		T3	311		T5	48
auto[0]	halfword_access	1834563	1			T1	352		T3	454		T5	114
auto[0]	byte_access	2456828	1			T1	467		T3	587		T5	375
auto[0]	zero_access	622844	1			T1	122		T3	154		T5	316
auto[1]	word_access	21639276	1			T1	13087		T2	4094		T3	14846
auto[1]	triple_byte_access	1226692	1			T1	223		T3	311		T5	204
auto[1]	halfword_access	1844236	1			T1	354		T3	437		T5	311
auto[1]	byte_access	2456225	1			T1	475		T3	652		T5	387
auto[1]	zero_access	615051	1			T1	111		T3	136		T5	106