Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147904028	1			T1	41000		T2	19284		T3	201898
instr_valid_dis	114828664	1			T1	41000		T2	19284		T3	201898
instr_en	22094290	1			T21	299192		T22	741738		T44	98578

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10250451	1			T25	12824		T21	139018		T22	479268
sram_ifetch_valid_disable	116261833	1			T1	41000		T2	19284		T3	201898
sram_ifetch_enable	21391744	1			T25	446		T21	139824		T22	733940

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147904028	1			T1	41000		T2	19284		T3	201898
hw_debug_en_valid_off	117668987	1			T1	41000		T2	19284		T3	201898
hw_debug_en_on	19485402	1			T25	121848		T21	54952		T22	600410

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	116261833	1			T1	41000		T2	19284		T3	201898
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102438046	1			T1	41000		T2	19284		T3	201898
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9454608	1			T21	20350		T22	123676		T44	63782
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4910681	1			T21	102332		T22	338576		T44	34796
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2064946	1			T23	44162		T151	17310		T152	16438
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1842685	1			T21	102332		T22	3382		T44	34796
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3609400	1			T21	36686		T22	72606		T44	15004
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1146304	1			T44	15004		T23	27214		T135	27636
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1611182	1			T21	36686		T22	52710		T147	46116
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7995737	1			T25	121848		T22	80278		T44	49522
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2844972	1			T25	121848		T22	40544		T44	18278
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3703685	1			T22	3334		T44	31244		T26	21590

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8478051	1			T21	139824		T22	531808		T26	28254
lc_exec_en	7880265	1			T21	18266		T22	447526		T26	15570
valid_exec_dis	111746058	1			T1	41000		T2	19284		T3	201898
invalid_exec_dis	31642195	1			T25	13270		T21	278842		T22	121320