Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total tests in report: 1030
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.68 66.68 91.02 91.02 62.80 62.80 75.76 75.76 23.81 23.81 77.78 77.78 94.10 94.10 41.50 41.50 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2548498540
82.92 16.24 95.85 4.83 79.74 16.94 80.20 4.44 61.90 38.10 86.71 8.94 96.17 2.06 79.89 38.39 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3334204747
88.78 5.85 97.03 1.19 86.26 6.52 97.36 17.16 71.43 9.52 90.58 3.86 96.31 0.15 82.45 2.56 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1454231943
93.64 4.86 98.56 1.53 86.37 0.12 97.36 0.00 100.00 28.57 93.48 2.90 97.05 0.74 82.63 0.18 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1691882152
94.72 1.09 98.73 0.17 87.20 0.83 97.57 0.21 100.00 0.00 94.20 0.72 97.05 0.00 88.30 5.67 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3689500414
95.54 0.82 98.73 0.00 88.03 0.83 97.99 0.42 100.00 0.00 94.69 0.48 97.05 0.00 92.32 4.02 /workspace/coverage/default/24.sram_ctrl_stress_all.3336382407
96.25 0.71 98.90 0.17 89.81 1.78 98.75 0.76 100.00 0.00 95.41 0.72 97.64 0.59 93.24 0.91 /workspace/coverage/default/4.sram_ctrl_sec_cm.873091566
96.70 0.45 98.90 0.00 90.17 0.36 98.75 0.00 100.00 0.00 95.65 0.24 97.79 0.15 95.61 2.38 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3535560192
96.89 0.20 98.90 0.00 90.17 0.00 98.82 0.07 100.00 0.00 95.65 0.00 99.12 1.33 95.61 0.00 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2095719015
97.03 0.14 99.07 0.17 90.28 0.12 98.82 0.00 100.00 0.00 96.14 0.48 99.12 0.00 95.80 0.18 /workspace/coverage/default/30.sram_ctrl_mem_walk.3418320553
97.16 0.13 99.15 0.08 90.28 0.00 99.65 0.83 100.00 0.00 96.14 0.00 99.12 0.00 95.80 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.494498465
97.25 0.09 99.15 0.00 90.52 0.24 99.65 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.16 0.37 /workspace/coverage/default/40.sram_ctrl_stress_all.1273110533
97.31 0.06 99.15 0.00 90.88 0.36 99.72 0.07 100.00 0.00 96.14 0.00 99.12 0.00 96.16 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.3494632307
97.36 0.05 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.53 0.37 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1098514405
97.41 0.05 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 96.89 0.37 /workspace/coverage/default/17.sram_ctrl_executable.2699727519
97.44 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.201106612
97.47 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1847029717
97.49 0.03 99.15 0.00 90.88 0.00 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/default/12.sram_ctrl_regwen.2745334930
97.51 0.02 99.15 0.00 91.00 0.12 99.72 0.00 100.00 0.00 96.14 0.00 99.12 0.00 97.44 0.00 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3664233340

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2207801716
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1794218879
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.464572483
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3419407789
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3453601435
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.867705764
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.375260579
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3614416791
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3955056554
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1339292588
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3624653652
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1569607794
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2847293224
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2294372960
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2024215846
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4106617733
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.715792459
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3947206468
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2494573252
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.874859022
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1127135065
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3255841108
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.973282031
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1418865672
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3607662824
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1920857360
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.836910264
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3882257391
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1686570024
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1446595086
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3869843263
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3640289612
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3863451726
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1078152624
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.903000352
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.395362813
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1372221759
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.648899166
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1710404424
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.244423471
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3949311086
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3674942778
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2834054517
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.803526568
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1357337961
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1012714748
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2649884851
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3773829930
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1419529298
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2980355423
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2633349390
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3618651019
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3104673492
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3774699085
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2840546130
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2238743913
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3646458059
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4078390403
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2348388374
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2766951586
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1279864870
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.46871157
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1407021998
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3083980219
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1766519037
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3470570
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1126727710
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2976719824
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2682386258
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3932561180
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2734015812
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2564053718
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3907869116
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3664913256
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2356963740
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2702021571
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1895925604
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.966830047
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1405776223
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.501457723
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2333685181
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2966426951
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.775622655
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.341996217
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.157096967
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.762365274
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3467310365
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3075048269
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3276796506
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.467272919
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2150030704
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1168688323
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3214676888
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1102755148
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3181258263
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1195903454
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.443773070
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.834715992
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2635470488
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1715175551
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3624532837
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3564387180
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3424090587
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.774895625
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2565778083
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4057690030
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1261905649
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1133104204
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1097891808
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.346911892
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4096164896
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3036519260
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3084910379
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.534080493
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3419644180
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1948710746
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2805837686
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2519723766
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4221786520
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1504248177
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2033556554
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.854106902
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2021000809
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.160345548
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1228687390
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.68344594
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.599861549
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4221725109
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1299022223
/workspace/coverage/default/0.sram_ctrl_bijection.100094211
/workspace/coverage/default/0.sram_ctrl_executable.3176860568
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3629932560
/workspace/coverage/default/0.sram_ctrl_max_throughput.906239498
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1280940304
/workspace/coverage/default/0.sram_ctrl_mem_walk.2344954872
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1652344268
/workspace/coverage/default/0.sram_ctrl_partial_access.1785937173
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.51520415
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3761278328
/workspace/coverage/default/0.sram_ctrl_regwen.157265453
/workspace/coverage/default/0.sram_ctrl_sec_cm.3004737185
/workspace/coverage/default/0.sram_ctrl_smoke.2756970635
/workspace/coverage/default/0.sram_ctrl_stress_all.3863730088
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.695767960
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.4241509727
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1729877999
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2468190124
/workspace/coverage/default/1.sram_ctrl_alert_test.4233369623
/workspace/coverage/default/1.sram_ctrl_bijection.342262531
/workspace/coverage/default/1.sram_ctrl_executable.1098575925
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1854096616
/workspace/coverage/default/1.sram_ctrl_max_throughput.3205623351
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2151575080
/workspace/coverage/default/1.sram_ctrl_mem_walk.2382209903
/workspace/coverage/default/1.sram_ctrl_multiple_keys.4242811625
/workspace/coverage/default/1.sram_ctrl_partial_access.1274758378
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1348298667
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2171189893
/workspace/coverage/default/1.sram_ctrl_regwen.3429563604
/workspace/coverage/default/1.sram_ctrl_sec_cm.2925592694
/workspace/coverage/default/1.sram_ctrl_smoke.67102924
/workspace/coverage/default/1.sram_ctrl_stress_all.291698823
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2788513617
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1228955136
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1382868828
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3690706673
/workspace/coverage/default/10.sram_ctrl_alert_test.456462547
/workspace/coverage/default/10.sram_ctrl_bijection.2636831019
/workspace/coverage/default/10.sram_ctrl_executable.871281704
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3904894032
/workspace/coverage/default/10.sram_ctrl_max_throughput.2271740669
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4069399173
/workspace/coverage/default/10.sram_ctrl_mem_walk.3967738444
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3659016967
/workspace/coverage/default/10.sram_ctrl_partial_access.2086159929
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2027865485
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1289366597
/workspace/coverage/default/10.sram_ctrl_regwen.2969556329
/workspace/coverage/default/10.sram_ctrl_smoke.2007049636
/workspace/coverage/default/10.sram_ctrl_stress_all.3109330575
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2731413893
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3952188509
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3796968477
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.645181759
/workspace/coverage/default/11.sram_ctrl_alert_test.3217835897
/workspace/coverage/default/11.sram_ctrl_bijection.4193962363
/workspace/coverage/default/11.sram_ctrl_executable.771346725
/workspace/coverage/default/11.sram_ctrl_lc_escalation.328727334
/workspace/coverage/default/11.sram_ctrl_max_throughput.3444803565
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.804170261
/workspace/coverage/default/11.sram_ctrl_mem_walk.548061854
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3082354738
/workspace/coverage/default/11.sram_ctrl_partial_access.3337029985
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.305773112
/workspace/coverage/default/11.sram_ctrl_regwen.2375160666
/workspace/coverage/default/11.sram_ctrl_smoke.2452934454
/workspace/coverage/default/11.sram_ctrl_stress_all.3752801730
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1206927189
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2869026381
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3007232086
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3126770263
/workspace/coverage/default/12.sram_ctrl_alert_test.2708422457
/workspace/coverage/default/12.sram_ctrl_bijection.3885744396
/workspace/coverage/default/12.sram_ctrl_executable.1778778204
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1123220322
/workspace/coverage/default/12.sram_ctrl_max_throughput.2137776157
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2304326847
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/workspace/coverage/default/43.sram_ctrl_multiple_keys.2244440673
/workspace/coverage/default/43.sram_ctrl_partial_access.2442173579
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2152082471
/workspace/coverage/default/43.sram_ctrl_ram_cfg.50090347
/workspace/coverage/default/43.sram_ctrl_regwen.2185027198
/workspace/coverage/default/43.sram_ctrl_smoke.672559660
/workspace/coverage/default/43.sram_ctrl_stress_all.3878837688
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3827904783
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.374741461
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4003013187
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.958195791
/workspace/coverage/default/44.sram_ctrl_alert_test.801939672
/workspace/coverage/default/44.sram_ctrl_bijection.1761994641
/workspace/coverage/default/44.sram_ctrl_executable.1984869265
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1075316371
/workspace/coverage/default/44.sram_ctrl_max_throughput.2619231338
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2160930765
/workspace/coverage/default/44.sram_ctrl_mem_walk.1477898625
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4128981582
/workspace/coverage/default/44.sram_ctrl_partial_access.4283155622
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2741886752
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2281080489
/workspace/coverage/default/44.sram_ctrl_regwen.979420532
/workspace/coverage/default/44.sram_ctrl_smoke.2755965461
/workspace/coverage/default/44.sram_ctrl_stress_all.1137417975
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3147924457
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1407998163
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4285575031
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2335307319
/workspace/coverage/default/45.sram_ctrl_alert_test.4117347876
/workspace/coverage/default/45.sram_ctrl_bijection.1698609932
/workspace/coverage/default/45.sram_ctrl_executable.3650090039
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3906771007
/workspace/coverage/default/45.sram_ctrl_max_throughput.2258868576
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3904625029
/workspace/coverage/default/45.sram_ctrl_mem_walk.663422014
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3605393789
/workspace/coverage/default/45.sram_ctrl_partial_access.296277704
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.149506166
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1873893886
/workspace/coverage/default/45.sram_ctrl_regwen.3537010018
/workspace/coverage/default/45.sram_ctrl_smoke.2262772171
/workspace/coverage/default/45.sram_ctrl_stress_all.622819426
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3896714819
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3573977058
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.977200034
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1356333232
/workspace/coverage/default/46.sram_ctrl_alert_test.3890623770
/workspace/coverage/default/46.sram_ctrl_bijection.3643471177
/workspace/coverage/default/46.sram_ctrl_executable.1989248614
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3448646252
/workspace/coverage/default/46.sram_ctrl_max_throughput.3733114511
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2810771952
/workspace/coverage/default/46.sram_ctrl_mem_walk.3159354538
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1954205920
/workspace/coverage/default/46.sram_ctrl_partial_access.1259619274
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4250303075
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1385810907
/workspace/coverage/default/46.sram_ctrl_regwen.2314308958
/workspace/coverage/default/46.sram_ctrl_smoke.4020152449
/workspace/coverage/default/46.sram_ctrl_stress_all.961299024
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2883475291
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.186040584
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2819505476
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.313853557
/workspace/coverage/default/47.sram_ctrl_alert_test.3538119495
/workspace/coverage/default/47.sram_ctrl_bijection.325731040
/workspace/coverage/default/47.sram_ctrl_executable.3835186392
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2474868971
/workspace/coverage/default/47.sram_ctrl_max_throughput.474466594
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.944779365
/workspace/coverage/default/47.sram_ctrl_mem_walk.4022825806
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2587627771
/workspace/coverage/default/47.sram_ctrl_partial_access.3664416954
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2587770988
/workspace/coverage/default/47.sram_ctrl_ram_cfg.465461354
/workspace/coverage/default/47.sram_ctrl_regwen.4267442310
/workspace/coverage/default/47.sram_ctrl_smoke.3922693393
/workspace/coverage/default/47.sram_ctrl_stress_all.3825242847
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3495395228
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3518613449
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3436574511
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1108191615
/workspace/coverage/default/48.sram_ctrl_alert_test.3671198499
/workspace/coverage/default/48.sram_ctrl_bijection.62869577
/workspace/coverage/default/48.sram_ctrl_executable.1036028131
/workspace/coverage/default/48.sram_ctrl_lc_escalation.978339332
/workspace/coverage/default/48.sram_ctrl_max_throughput.529837868
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3206153744
/workspace/coverage/default/48.sram_ctrl_mem_walk.4142787003
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1396992
/workspace/coverage/default/48.sram_ctrl_partial_access.1355893763
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.326603926
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2457107350
/workspace/coverage/default/48.sram_ctrl_regwen.971713729
/workspace/coverage/default/48.sram_ctrl_smoke.2715376308
/workspace/coverage/default/48.sram_ctrl_stress_all.2155607151
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2125906381
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.297129091
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.4294810045
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1302312923
/workspace/coverage/default/49.sram_ctrl_alert_test.1299218035
/workspace/coverage/default/49.sram_ctrl_bijection.3099293112
/workspace/coverage/default/49.sram_ctrl_executable.3237731468
/workspace/coverage/default/49.sram_ctrl_lc_escalation.4266337873
/workspace/coverage/default/49.sram_ctrl_max_throughput.2635162597
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2836018310
/workspace/coverage/default/49.sram_ctrl_mem_walk.1756183113
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3370478414
/workspace/coverage/default/49.sram_ctrl_partial_access.1664867338
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.300584578
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1594290947
/workspace/coverage/default/49.sram_ctrl_regwen.962757999
/workspace/coverage/default/49.sram_ctrl_smoke.2813267912
/workspace/coverage/default/49.sram_ctrl_stress_all.3581209691
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1376236450
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3477628252
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4078836735
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1639772917
/workspace/coverage/default/5.sram_ctrl_alert_test.2988859897
/workspace/coverage/default/5.sram_ctrl_bijection.3040609051
/workspace/coverage/default/5.sram_ctrl_executable.2092029396
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2315866450
/workspace/coverage/default/5.sram_ctrl_max_throughput.514290761
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3481596771
/workspace/coverage/default/5.sram_ctrl_mem_walk.1854603623
/workspace/coverage/default/5.sram_ctrl_multiple_keys.181257148
/workspace/coverage/default/5.sram_ctrl_partial_access.1759870264
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1420259700
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2023863719
/workspace/coverage/default/5.sram_ctrl_regwen.3773955340
/workspace/coverage/default/5.sram_ctrl_smoke.1799984227
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.819418496
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3586037169
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4182374403
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.525809871
/workspace/coverage/default/6.sram_ctrl_alert_test.4231007371
/workspace/coverage/default/6.sram_ctrl_bijection.3514865700
/workspace/coverage/default/6.sram_ctrl_executable.1457246336
/workspace/coverage/default/6.sram_ctrl_lc_escalation.304618382
/workspace/coverage/default/6.sram_ctrl_max_throughput.1492313298
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.391251378
/workspace/coverage/default/6.sram_ctrl_mem_walk.324957690
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1946265137
/workspace/coverage/default/6.sram_ctrl_partial_access.3987601020
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3105205706
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2008267354
/workspace/coverage/default/6.sram_ctrl_regwen.1078564707
/workspace/coverage/default/6.sram_ctrl_smoke.3115189727
/workspace/coverage/default/6.sram_ctrl_stress_all.1385875617
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2963326035
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3905498329
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4279822345
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1785637324
/workspace/coverage/default/7.sram_ctrl_alert_test.1282767028
/workspace/coverage/default/7.sram_ctrl_bijection.1750294
/workspace/coverage/default/7.sram_ctrl_executable.964989054
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3170163418
/workspace/coverage/default/7.sram_ctrl_max_throughput.269484652
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2741683771
/workspace/coverage/default/7.sram_ctrl_mem_walk.328889970
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1216288604
/workspace/coverage/default/7.sram_ctrl_partial_access.3391732607
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1569193716
/workspace/coverage/default/7.sram_ctrl_ram_cfg.685154306
/workspace/coverage/default/7.sram_ctrl_regwen.4173468494
/workspace/coverage/default/7.sram_ctrl_smoke.2197185944
/workspace/coverage/default/7.sram_ctrl_stress_all.3551367214
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1011200887
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3018295953
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3996744287
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.971609989
/workspace/coverage/default/8.sram_ctrl_alert_test.2681580603
/workspace/coverage/default/8.sram_ctrl_bijection.395076009
/workspace/coverage/default/8.sram_ctrl_executable.2440726574
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3557014163
/workspace/coverage/default/8.sram_ctrl_max_throughput.1715117400
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4122535942
/workspace/coverage/default/8.sram_ctrl_mem_walk.3594540177
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1416570356
/workspace/coverage/default/8.sram_ctrl_partial_access.3941610562
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.605852941
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3676446751
/workspace/coverage/default/8.sram_ctrl_regwen.105835150
/workspace/coverage/default/8.sram_ctrl_smoke.1709951479
/workspace/coverage/default/8.sram_ctrl_stress_all.2473753173
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3531952261
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.522286566
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.233046163
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.238366140
/workspace/coverage/default/9.sram_ctrl_alert_test.1324743532
/workspace/coverage/default/9.sram_ctrl_bijection.3035308441
/workspace/coverage/default/9.sram_ctrl_executable.3736738065
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3510593051
/workspace/coverage/default/9.sram_ctrl_max_throughput.1254426870
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3479294713
/workspace/coverage/default/9.sram_ctrl_mem_walk.2367873710
/workspace/coverage/default/9.sram_ctrl_multiple_keys.183281005
/workspace/coverage/default/9.sram_ctrl_partial_access.3416106671
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1754636856
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3115513897
/workspace/coverage/default/9.sram_ctrl_regwen.1397680840
/workspace/coverage/default/9.sram_ctrl_smoke.4244420913
/workspace/coverage/default/9.sram_ctrl_stress_all.228516829
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2658742665
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.818264115
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2878068041



Total test records in report: 1030
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.sram_ctrl_multiple_keys.1652344268 Jul 28 06:24:26 PM PDT 24 Jul 28 06:27:00 PM PDT 24 1494567618 ps
T2 /workspace/coverage/default/21.sram_ctrl_smoke.2587309705 Jul 28 06:30:18 PM PDT 24 Jul 28 06:32:05 PM PDT 24 2886593033 ps
T3 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2548498540 Jul 28 06:32:08 PM PDT 24 Jul 28 06:40:13 PM PDT 24 4018865853 ps
T7 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.935164381 Jul 28 06:35:10 PM PDT 24 Jul 28 06:40:17 PM PDT 24 4132707850 ps
T8 /workspace/coverage/default/4.sram_ctrl_smoke.617879906 Jul 28 06:25:21 PM PDT 24 Jul 28 06:25:36 PM PDT 24 279034026 ps
T9 /workspace/coverage/default/8.sram_ctrl_max_throughput.1715117400 Jul 28 06:26:21 PM PDT 24 Jul 28 06:26:31 PM PDT 24 234309915 ps
T10 /workspace/coverage/default/2.sram_ctrl_bijection.952655507 Jul 28 06:24:52 PM PDT 24 Jul 28 06:25:26 PM PDT 24 7529081747 ps
T11 /workspace/coverage/default/11.sram_ctrl_multiple_keys.3082354738 Jul 28 06:27:09 PM PDT 24 Jul 28 06:44:27 PM PDT 24 78998293603 ps
T12 /workspace/coverage/default/40.sram_ctrl_mem_walk.2204066636 Jul 28 06:36:04 PM PDT 24 Jul 28 06:36:10 PM PDT 24 95391447 ps
T13 /workspace/coverage/default/8.sram_ctrl_mem_walk.3594540177 Jul 28 06:26:26 PM PDT 24 Jul 28 06:26:30 PM PDT 24 78559486 ps
T4 /workspace/coverage/default/2.sram_ctrl_lc_escalation.4029472957 Jul 28 06:24:55 PM PDT 24 Jul 28 06:24:57 PM PDT 24 470910165 ps
T25 /workspace/coverage/default/34.sram_ctrl_regwen.3286775194 Jul 28 06:34:23 PM PDT 24 Jul 28 06:43:35 PM PDT 24 39827094909 ps
T5 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1454231943 Jul 28 06:29:57 PM PDT 24 Jul 28 06:30:03 PM PDT 24 2111143290 ps
T21 /workspace/coverage/default/10.sram_ctrl_stress_all.3109330575 Jul 28 06:27:02 PM PDT 24 Jul 28 07:13:24 PM PDT 24 18145045108 ps
T57 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3477628252 Jul 28 06:38:26 PM PDT 24 Jul 28 06:41:24 PM PDT 24 7222860091 ps
T42 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3174068854 Jul 28 06:36:09 PM PDT 24 Jul 28 06:41:59 PM PDT 24 1198727161 ps
T58 /workspace/coverage/default/15.sram_ctrl_partial_access.321684805 Jul 28 06:28:37 PM PDT 24 Jul 28 06:28:48 PM PDT 24 213791679 ps
T59 /workspace/coverage/default/45.sram_ctrl_multiple_keys.3605393789 Jul 28 06:37:16 PM PDT 24 Jul 28 06:43:50 PM PDT 24 8553078663 ps
T70 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3673482714 Jul 28 06:31:56 PM PDT 24 Jul 28 06:33:00 PM PDT 24 2301354197 ps
T73 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3535560192 Jul 28 06:32:01 PM PDT 24 Jul 28 06:38:24 PM PDT 24 21900836131 ps
T161 /workspace/coverage/default/7.sram_ctrl_smoke.2197185944 Jul 28 06:25:59 PM PDT 24 Jul 28 06:26:16 PM PDT 24 3557199729 ps
T95 /workspace/coverage/default/18.sram_ctrl_multiple_keys.814555832 Jul 28 06:29:29 PM PDT 24 Jul 28 06:43:56 PM PDT 24 12260768828 ps
T6 /workspace/coverage/default/5.sram_ctrl_lc_escalation.2315866450 Jul 28 06:25:34 PM PDT 24 Jul 28 06:25:38 PM PDT 24 850383208 ps
T22 /workspace/coverage/default/24.sram_ctrl_stress_all.3336382407 Jul 28 06:31:26 PM PDT 24 Jul 28 08:19:12 PM PDT 24 64490921616 ps
T156 /workspace/coverage/default/23.sram_ctrl_bijection.2910539923 Jul 28 06:30:53 PM PDT 24 Jul 28 06:31:23 PM PDT 24 15947869445 ps
T29 /workspace/coverage/default/11.sram_ctrl_ram_cfg.494498465 Jul 28 06:27:22 PM PDT 24 Jul 28 06:27:23 PM PDT 24 139075629 ps
T45 /workspace/coverage/default/34.sram_ctrl_mem_walk.3110161737 Jul 28 06:34:22 PM PDT 24 Jul 28 06:34:27 PM PDT 24 481277977 ps
T116 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.706097426 Jul 28 06:29:38 PM PDT 24 Jul 28 06:34:53 PM PDT 24 4247878730 ps
T117 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3135848134 Jul 28 06:28:21 PM PDT 24 Jul 28 06:31:26 PM PDT 24 2570658687 ps
T46 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.682189960 Jul 28 06:30:39 PM PDT 24 Jul 28 06:30:44 PM PDT 24 96000590 ps
T20 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2742145304 Jul 28 06:28:41 PM PDT 24 Jul 28 06:28:46 PM PDT 24 1904727460 ps
T14 /workspace/coverage/default/13.sram_ctrl_alert_test.2125691933 Jul 28 06:28:11 PM PDT 24 Jul 28 06:28:11 PM PDT 24 12991748 ps
T43 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3323062050 Jul 28 06:33:03 PM PDT 24 Jul 28 06:40:35 PM PDT 24 1452118523 ps
T51 /workspace/coverage/default/26.sram_ctrl_mem_walk.3064028870 Jul 28 06:31:57 PM PDT 24 Jul 28 06:32:03 PM PDT 24 917011742 ps
T15 /workspace/coverage/default/12.sram_ctrl_alert_test.2708422457 Jul 28 06:27:43 PM PDT 24 Jul 28 06:27:44 PM PDT 24 14323202 ps
T64 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3589897746 Jul 28 06:29:03 PM PDT 24 Jul 28 06:29:13 PM PDT 24 278817826 ps
T65 /workspace/coverage/default/3.sram_ctrl_multiple_keys.38434056 Jul 28 06:25:03 PM PDT 24 Jul 28 06:48:45 PM PDT 24 33233159172 ps
T30 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3828672273 Jul 28 06:29:09 PM PDT 24 Jul 28 06:29:09 PM PDT 24 89672546 ps
T66 /workspace/coverage/default/10.sram_ctrl_lc_escalation.3904894032 Jul 28 06:27:01 PM PDT 24 Jul 28 06:27:08 PM PDT 24 664993579 ps
T50 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.866670794 Jul 28 06:28:48 PM PDT 24 Jul 28 06:28:51 PM PDT 24 99699053 ps
T44 /workspace/coverage/default/11.sram_ctrl_executable.771346725 Jul 28 06:27:21 PM PDT 24 Jul 28 06:38:14 PM PDT 24 11213804806 ps
T166 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.554161088 Jul 28 06:24:55 PM PDT 24 Jul 28 06:24:59 PM PDT 24 49683300 ps
T26 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3334204747 Jul 28 06:36:33 PM PDT 24 Jul 28 06:49:09 PM PDT 24 5418679090 ps
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T80 /workspace/coverage/default/26.sram_ctrl_bijection.3716268081 Jul 28 06:31:51 PM PDT 24 Jul 28 06:33:18 PM PDT 24 8889593979 ps
T81 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.326873656 Jul 28 06:36:22 PM PDT 24 Jul 28 06:41:15 PM PDT 24 55248656022 ps
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T83 /workspace/coverage/default/48.sram_ctrl_mem_walk.4142787003 Jul 28 06:38:23 PM PDT 24 Jul 28 06:38:28 PM PDT 24 209555896 ps
T84 /workspace/coverage/default/25.sram_ctrl_max_throughput.247303437 Jul 28 06:31:31 PM PDT 24 Jul 28 06:31:53 PM PDT 24 1294533395 ps
T55 /workspace/coverage/default/30.sram_ctrl_mem_walk.3418320553 Jul 28 06:33:07 PM PDT 24 Jul 28 06:33:17 PM PDT 24 886605099 ps
T31 /workspace/coverage/default/48.sram_ctrl_ram_cfg.2457107350 Jul 28 06:38:20 PM PDT 24 Jul 28 06:38:22 PM PDT 24 31814115 ps
T85 /workspace/coverage/default/17.sram_ctrl_executable.2699727519 Jul 28 06:29:25 PM PDT 24 Jul 28 06:40:50 PM PDT 24 13351677247 ps
T162 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3981381270 Jul 28 06:28:36 PM PDT 24 Jul 28 06:28:40 PM PDT 24 308788394 ps
T167 /workspace/coverage/default/17.sram_ctrl_max_throughput.1463253496 Jul 28 06:29:22 PM PDT 24 Jul 28 06:29:24 PM PDT 24 45370674 ps
T147 /workspace/coverage/default/38.sram_ctrl_executable.2544083361 Jul 28 06:35:22 PM PDT 24 Jul 28 06:45:02 PM PDT 24 31670421022 ps
T23 /workspace/coverage/default/3.sram_ctrl_stress_all.180151510 Jul 28 06:25:16 PM PDT 24 Jul 28 06:55:47 PM PDT 24 44080573952 ps
T168 /workspace/coverage/default/38.sram_ctrl_multiple_keys.2724309592 Jul 28 06:35:28 PM PDT 24 Jul 28 06:45:01 PM PDT 24 5714358236 ps
T118 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2667691104 Jul 28 06:28:38 PM PDT 24 Jul 28 06:35:15 PM PDT 24 65243281474 ps
T160 /workspace/coverage/default/15.sram_ctrl_bijection.2001193412 Jul 28 06:28:38 PM PDT 24 Jul 28 06:29:25 PM PDT 24 10448990532 ps
T151 /workspace/coverage/default/44.sram_ctrl_executable.1984869265 Jul 28 06:37:00 PM PDT 24 Jul 28 06:44:29 PM PDT 24 9200268536 ps
T153 /workspace/coverage/default/12.sram_ctrl_bijection.3885744396 Jul 28 06:27:31 PM PDT 24 Jul 28 06:28:47 PM PDT 24 3595318096 ps
T158 /workspace/coverage/default/22.sram_ctrl_ram_cfg.2026577131 Jul 28 06:30:50 PM PDT 24 Jul 28 06:30:51 PM PDT 24 30478221 ps
T169 /workspace/coverage/default/18.sram_ctrl_ram_cfg.3500582728 Jul 28 06:29:40 PM PDT 24 Jul 28 06:29:41 PM PDT 24 76902940 ps
T100 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1339799078 Jul 28 06:36:23 PM PDT 24 Jul 28 06:51:27 PM PDT 24 8734819617 ps
T119 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1128500696 Jul 28 06:30:23 PM PDT 24 Jul 28 06:36:18 PM PDT 24 15979659534 ps
T170 /workspace/coverage/default/8.sram_ctrl_multiple_keys.1416570356 Jul 28 06:26:15 PM PDT 24 Jul 28 06:57:58 PM PDT 24 21480665747 ps
T165 /workspace/coverage/default/24.sram_ctrl_ram_cfg.285984010 Jul 28 06:31:28 PM PDT 24 Jul 28 06:31:29 PM PDT 24 82807704 ps
T86 /workspace/coverage/default/33.sram_ctrl_regwen.1886752084 Jul 28 06:34:00 PM PDT 24 Jul 28 06:40:42 PM PDT 24 13309075150 ps
T164 /workspace/coverage/default/3.sram_ctrl_ram_cfg.3668337174 Jul 28 06:25:13 PM PDT 24 Jul 28 06:25:14 PM PDT 24 31338583 ps
T171 /workspace/coverage/default/12.sram_ctrl_max_throughput.2137776157 Jul 28 06:27:38 PM PDT 24 Jul 28 06:28:16 PM PDT 24 110080173 ps
T135 /workspace/coverage/default/44.sram_ctrl_stress_all.1137417975 Jul 28 06:37:09 PM PDT 24 Jul 28 06:49:35 PM PDT 24 11483715045 ps
T16 /workspace/coverage/default/15.sram_ctrl_alert_test.2164750918 Jul 28 06:28:54 PM PDT 24 Jul 28 06:28:55 PM PDT 24 16396581 ps
T172 /workspace/coverage/default/35.sram_ctrl_partial_access.2492090097 Jul 28 06:34:30 PM PDT 24 Jul 28 06:35:45 PM PDT 24 1201245664 ps
T120 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1098117742 Jul 28 06:27:30 PM PDT 24 Jul 28 06:35:52 PM PDT 24 27987800636 ps
T163 /workspace/coverage/default/25.sram_ctrl_mem_walk.1837600516 Jul 28 06:31:44 PM PDT 24 Jul 28 06:31:48 PM PDT 24 155981016 ps
T17 /workspace/coverage/default/4.sram_ctrl_sec_cm.873091566 Jul 28 06:25:33 PM PDT 24 Jul 28 06:25:35 PM PDT 24 94726355 ps
T34 /workspace/coverage/default/1.sram_ctrl_partial_access.1274758378 Jul 28 06:24:41 PM PDT 24 Jul 28 06:25:08 PM PDT 24 629489567 ps
T35 /workspace/coverage/default/33.sram_ctrl_stress_all.483546026 Jul 28 06:34:07 PM PDT 24 Jul 28 06:58:40 PM PDT 24 43481428951 ps
T36 /workspace/coverage/default/41.sram_ctrl_mem_walk.4268323814 Jul 28 06:36:16 PM PDT 24 Jul 28 06:36:21 PM PDT 24 283102303 ps
T37 /workspace/coverage/default/44.sram_ctrl_bijection.1761994641 Jul 28 06:36:56 PM PDT 24 Jul 28 06:37:44 PM PDT 24 11003949240 ps
T38 /workspace/coverage/default/7.sram_ctrl_max_throughput.269484652 Jul 28 06:26:10 PM PDT 24 Jul 28 06:28:37 PM PDT 24 138705964 ps
T39 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3018295953 Jul 28 06:26:00 PM PDT 24 Jul 28 06:30:44 PM PDT 24 3141631186 ps
T24 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3664233340 Jul 28 06:27:55 PM PDT 24 Jul 28 06:28:00 PM PDT 24 293703421 ps
T40 /workspace/coverage/default/39.sram_ctrl_ram_cfg.99032073 Jul 28 06:35:39 PM PDT 24 Jul 28 06:35:40 PM PDT 24 39574571 ps
T41 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3255479205 Jul 28 06:33:09 PM PDT 24 Jul 28 06:33:14 PM PDT 24 91983789 ps
T173 /workspace/coverage/default/29.sram_ctrl_stress_all.1304281358 Jul 28 06:32:49 PM PDT 24 Jul 28 07:04:00 PM PDT 24 76646378004 ps
T174 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1436695053 Jul 28 06:33:24 PM PDT 24 Jul 28 06:33:25 PM PDT 24 382557792 ps
T159 /workspace/coverage/default/46.sram_ctrl_regwen.2314308958 Jul 28 06:37:45 PM PDT 24 Jul 28 06:47:29 PM PDT 24 7719623655 ps
T175 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1407998163 Jul 28 06:36:57 PM PDT 24 Jul 28 06:42:42 PM PDT 24 3898041590 ps
T152 /workspace/coverage/default/40.sram_ctrl_stress_all.1273110533 Jul 28 06:36:10 PM PDT 24 Jul 28 07:25:24 PM PDT 24 62171452308 ps
T176 /workspace/coverage/default/46.sram_ctrl_smoke.4020152449 Jul 28 06:37:35 PM PDT 24 Jul 28 06:38:12 PM PDT 24 1380868667 ps
T177 /workspace/coverage/default/14.sram_ctrl_max_throughput.3364078047 Jul 28 06:28:21 PM PDT 24 Jul 28 06:28:35 PM PDT 24 79860273 ps
T178 /workspace/coverage/default/43.sram_ctrl_ram_cfg.50090347 Jul 28 06:36:46 PM PDT 24 Jul 28 06:36:47 PM PDT 24 79122783 ps
T154 /workspace/coverage/default/42.sram_ctrl_multiple_keys.3579361678 Jul 28 06:36:20 PM PDT 24 Jul 28 06:50:53 PM PDT 24 17827307671 ps
T101 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.971609989 Jul 28 06:26:20 PM PDT 24 Jul 28 06:41:51 PM PDT 24 6955362790 ps
T179 /workspace/coverage/default/37.sram_ctrl_lc_escalation.1789236065 Jul 28 06:35:17 PM PDT 24 Jul 28 06:35:21 PM PDT 24 644540771 ps
T148 /workspace/coverage/default/7.sram_ctrl_executable.964989054 Jul 28 06:26:06 PM PDT 24 Jul 28 06:42:04 PM PDT 24 10518859476 ps
T180 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4003013187 Jul 28 06:36:45 PM PDT 24 Jul 28 06:38:27 PM PDT 24 1083679421 ps
T181 /workspace/coverage/default/35.sram_ctrl_multiple_keys.549857177 Jul 28 06:34:22 PM PDT 24 Jul 28 06:39:33 PM PDT 24 3408952721 ps
T27 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1695989784 Jul 28 06:32:01 PM PDT 24 Jul 28 06:32:16 PM PDT 24 5363952625 ps
T128 /workspace/coverage/default/36.sram_ctrl_regwen.1550506306 Jul 28 06:34:51 PM PDT 24 Jul 28 06:50:24 PM PDT 24 15643690331 ps
T129 /workspace/coverage/default/48.sram_ctrl_alert_test.3671198499 Jul 28 06:38:21 PM PDT 24 Jul 28 06:38:22 PM PDT 24 48411457 ps
T130 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.4028429356 Jul 28 06:33:40 PM PDT 24 Jul 28 06:34:15 PM PDT 24 202530189 ps
T52 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3206153744 Jul 28 06:38:20 PM PDT 24 Jul 28 06:38:23 PM PDT 24 198126168 ps
T131 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.150008020 Jul 28 06:31:21 PM PDT 24 Jul 28 06:39:41 PM PDT 24 69002759925 ps
T132 /workspace/coverage/default/2.sram_ctrl_alert_test.895565890 Jul 28 06:25:06 PM PDT 24 Jul 28 06:25:07 PM PDT 24 105892177 ps
T133 /workspace/coverage/default/20.sram_ctrl_bijection.3960790274 Jul 28 06:30:07 PM PDT 24 Jul 28 06:30:47 PM PDT 24 9987589164 ps
T56 /workspace/coverage/default/9.sram_ctrl_mem_walk.2367873710 Jul 28 06:26:42 PM PDT 24 Jul 28 06:26:48 PM PDT 24 362898463 ps
T134 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2264790133 Jul 28 06:32:03 PM PDT 24 Jul 28 06:34:31 PM PDT 24 7313459113 ps
T155 /workspace/coverage/default/7.sram_ctrl_bijection.1750294 Jul 28 06:26:01 PM PDT 24 Jul 28 06:27:29 PM PDT 24 35999030129 ps
T182 /workspace/coverage/default/35.sram_ctrl_smoke.1952205452 Jul 28 06:34:23 PM PDT 24 Jul 28 06:34:38 PM PDT 24 1552188083 ps
T183 /workspace/coverage/default/37.sram_ctrl_bijection.3311606726 Jul 28 06:35:03 PM PDT 24 Jul 28 06:36:06 PM PDT 24 1202055126 ps
T184 /workspace/coverage/default/13.sram_ctrl_bijection.4204551662 Jul 28 06:27:48 PM PDT 24 Jul 28 06:29:14 PM PDT 24 5519713385 ps
T185 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4276888681 Jul 28 06:32:20 PM PDT 24 Jul 28 06:32:42 PM PDT 24 88592957 ps
T186 /workspace/coverage/default/23.sram_ctrl_max_throughput.1833382345 Jul 28 06:30:55 PM PDT 24 Jul 28 06:30:57 PM PDT 24 123700730 ps
T157 /workspace/coverage/default/1.sram_ctrl_stress_all.291698823 Jul 28 06:24:46 PM PDT 24 Jul 28 06:51:40 PM PDT 24 23080344827 ps
T187 /workspace/coverage/default/29.sram_ctrl_bijection.509534408 Jul 28 06:32:29 PM PDT 24 Jul 28 06:33:24 PM PDT 24 1360901446 ps
T28 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.446818918 Jul 28 06:31:43 PM PDT 24 Jul 28 06:34:36 PM PDT 24 3180759760 ps
T102 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.313853557 Jul 28 06:37:56 PM PDT 24 Jul 28 06:54:27 PM PDT 24 2355375899 ps
T188 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.968206554 Jul 28 06:25:25 PM PDT 24 Jul 28 06:45:17 PM PDT 24 4433304134 ps
T53 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1409669436 Jul 28 06:30:09 PM PDT 24 Jul 28 06:30:15 PM PDT 24 699027942 ps
T54 /workspace/coverage/default/23.sram_ctrl_mem_walk.3718921594 Jul 28 06:31:08 PM PDT 24 Jul 28 06:31:14 PM PDT 24 2060157655 ps
T189 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4069399173 Jul 28 06:27:01 PM PDT 24 Jul 28 06:27:04 PM PDT 24 162004995 ps
T190 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2917312476 Jul 28 06:31:01 PM PDT 24 Jul 28 06:31:02 PM PDT 24 30730260 ps
T191 /workspace/coverage/default/35.sram_ctrl_executable.3230349801 Jul 28 06:34:40 PM PDT 24 Jul 28 06:42:33 PM PDT 24 1488725247 ps
T192 /workspace/coverage/default/27.sram_ctrl_executable.1730590929 Jul 28 06:32:10 PM PDT 24 Jul 28 06:55:08 PM PDT 24 23308643689 ps
T193 /workspace/coverage/default/38.sram_ctrl_partial_access.3544231587 Jul 28 06:35:23 PM PDT 24 Jul 28 06:35:36 PM PDT 24 1151256951 ps
T194 /workspace/coverage/default/28.sram_ctrl_lc_escalation.1396327865 Jul 28 06:32:20 PM PDT 24 Jul 28 06:32:28 PM PDT 24 6395635724 ps
T60 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.391251378 Jul 28 06:25:54 PM PDT 24 Jul 28 06:25:58 PM PDT 24 238110969 ps
T195 /workspace/coverage/default/42.sram_ctrl_lc_escalation.107816776 Jul 28 06:36:22 PM PDT 24 Jul 28 06:36:27 PM PDT 24 1194520678 ps
T149 /workspace/coverage/default/12.sram_ctrl_regwen.2745334930 Jul 28 06:27:37 PM PDT 24 Jul 28 06:48:59 PM PDT 24 12114633656 ps
T61 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1376236450 Jul 28 06:38:42 PM PDT 24 Jul 28 06:41:36 PM PDT 24 5944594483 ps
T196 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1302312923 Jul 28 06:38:34 PM PDT 24 Jul 28 06:44:41 PM PDT 24 1360473376 ps
T62 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2304326847 Jul 28 06:27:43 PM PDT 24 Jul 28 06:27:46 PM PDT 24 193489646 ps
T197 /workspace/coverage/default/46.sram_ctrl_max_throughput.3733114511 Jul 28 06:37:41 PM PDT 24 Jul 28 06:37:58 PM PDT 24 413867690 ps
T63 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1495981003 Jul 28 06:32:15 PM PDT 24 Jul 28 06:32:18 PM PDT 24 119185069 ps
T198 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2741683771 Jul 28 06:26:11 PM PDT 24 Jul 28 06:26:16 PM PDT 24 65133067 ps
T199 /workspace/coverage/default/5.sram_ctrl_smoke.1799984227 Jul 28 06:25:34 PM PDT 24 Jul 28 06:25:41 PM PDT 24 254444973 ps
T200 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1965663494 Jul 28 06:25:11 PM PDT 24 Jul 28 06:47:08 PM PDT 24 7650088926 ps
T146 /workspace/coverage/default/38.sram_ctrl_regwen.1963628926 Jul 28 06:35:28 PM PDT 24 Jul 28 06:43:47 PM PDT 24 16934305444 ps
T201 /workspace/coverage/default/4.sram_ctrl_executable.906573617 Jul 28 06:25:26 PM PDT 24 Jul 28 06:31:23 PM PDT 24 16419235693 ps
T202 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3363931246 Jul 28 06:34:22 PM PDT 24 Jul 28 06:43:25 PM PDT 24 5865271869 ps
T203 /workspace/coverage/default/5.sram_ctrl_executable.2092029396 Jul 28 06:25:37 PM PDT 24 Jul 28 06:36:29 PM PDT 24 2581282655 ps
T204 /workspace/coverage/default/28.sram_ctrl_ram_cfg.1106559990 Jul 28 06:32:28 PM PDT 24 Jul 28 06:32:29 PM PDT 24 47654776 ps
T205 /workspace/coverage/default/45.sram_ctrl_max_throughput.2258868576 Jul 28 06:37:22 PM PDT 24 Jul 28 06:37:44 PM PDT 24 190745544 ps
T206 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3755155038 Jul 28 06:35:28 PM PDT 24 Jul 28 06:35:35 PM PDT 24 131511138 ps
T207 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.962576394 Jul 28 06:30:54 PM PDT 24 Jul 28 06:30:58 PM PDT 24 65745234 ps
T208 /workspace/coverage/default/22.sram_ctrl_multiple_keys.539032702 Jul 28 06:31:00 PM PDT 24 Jul 28 06:39:26 PM PDT 24 2302684736 ps
T209 /workspace/coverage/default/16.sram_ctrl_bijection.1188261467 Jul 28 06:28:53 PM PDT 24 Jul 28 06:29:29 PM PDT 24 1214949653 ps
T210 /workspace/coverage/default/7.sram_ctrl_lc_escalation.3170163418 Jul 28 06:26:07 PM PDT 24 Jul 28 06:26:16 PM PDT 24 1906817695 ps
T211 /workspace/coverage/default/49.sram_ctrl_smoke.2813267912 Jul 28 06:38:22 PM PDT 24 Jul 28 06:38:24 PM PDT 24 534916522 ps
T212 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2198664818 Jul 28 06:36:15 PM PDT 24 Jul 28 06:36:18 PM PDT 24 555827645 ps
T213 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.208439517 Jul 28 06:33:51 PM PDT 24 Jul 28 06:37:45 PM PDT 24 3069651871 ps
T214 /workspace/coverage/default/13.sram_ctrl_executable.1963870610 Jul 28 06:27:57 PM PDT 24 Jul 28 06:33:58 PM PDT 24 8034747892 ps
T215 /workspace/coverage/default/7.sram_ctrl_mem_walk.328889970 Jul 28 06:26:09 PM PDT 24 Jul 28 06:26:18 PM PDT 24 134836424 ps
T216 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2335307319 Jul 28 06:37:32 PM PDT 24 Jul 28 06:57:57 PM PDT 24 4468612061 ps
T217 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1337100545 Jul 28 06:34:35 PM PDT 24 Jul 28 06:36:24 PM PDT 24 165848102 ps
T218 /workspace/coverage/default/49.sram_ctrl_partial_access.1664867338 Jul 28 06:38:34 PM PDT 24 Jul 28 06:38:38 PM PDT 24 115960110 ps
T219 /workspace/coverage/default/24.sram_ctrl_multiple_keys.2361648829 Jul 28 06:31:22 PM PDT 24 Jul 28 06:46:57 PM PDT 24 3180346857 ps
T220 /workspace/coverage/default/41.sram_ctrl_partial_access.743345393 Jul 28 06:36:09 PM PDT 24 Jul 28 06:38:38 PM PDT 24 3498475719 ps
T221 /workspace/coverage/default/42.sram_ctrl_smoke.763313495 Jul 28 06:36:21 PM PDT 24 Jul 28 06:37:37 PM PDT 24 140369071 ps
T222 /workspace/coverage/default/46.sram_ctrl_mem_walk.3159354538 Jul 28 06:37:45 PM PDT 24 Jul 28 06:37:51 PM PDT 24 303045621 ps
T223 /workspace/coverage/default/21.sram_ctrl_mem_walk.620027002 Jul 28 06:30:31 PM PDT 24 Jul 28 06:30:43 PM PDT 24 2618424221 ps
T224 /workspace/coverage/default/26.sram_ctrl_partial_access.3143902413 Jul 28 06:31:50 PM PDT 24 Jul 28 06:31:55 PM PDT 24 378885355 ps
T225 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3508197211 Jul 28 06:28:24 PM PDT 24 Jul 28 06:28:24 PM PDT 24 26404407 ps
T226 /workspace/coverage/default/1.sram_ctrl_bijection.342262531 Jul 28 06:24:39 PM PDT 24 Jul 28 06:24:56 PM PDT 24 975915224 ps
T227 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1375898400 Jul 28 06:24:56 PM PDT 24 Jul 28 06:29:09 PM PDT 24 4523689978 ps
T228 /workspace/coverage/default/22.sram_ctrl_partial_access.283428933 Jul 28 06:30:43 PM PDT 24 Jul 28 06:30:59 PM PDT 24 5119522786 ps
T150 /workspace/coverage/default/45.sram_ctrl_executable.3650090039 Jul 28 06:37:31 PM PDT 24 Jul 28 06:52:54 PM PDT 24 7011579404 ps
T145 /workspace/coverage/default/32.sram_ctrl_regwen.261433574 Jul 28 06:33:40 PM PDT 24 Jul 28 06:48:32 PM PDT 24 5157452445 ps
T229 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3996744287 Jul 28 06:26:08 PM PDT 24 Jul 28 06:26:09 PM PDT 24 37502377 ps
T230 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.525809871 Jul 28 06:25:56 PM PDT 24 Jul 28 06:36:12 PM PDT 24 3459579974 ps
T231 /workspace/coverage/default/39.sram_ctrl_partial_access.2371993718 Jul 28 06:35:36 PM PDT 24 Jul 28 06:35:46 PM PDT 24 371058034 ps
T232 /workspace/coverage/default/48.sram_ctrl_executable.1036028131 Jul 28 06:38:22 PM PDT 24 Jul 28 06:52:55 PM PDT 24 21827696811 ps
T233 /workspace/coverage/default/33.sram_ctrl_executable.1547412160 Jul 28 06:33:59 PM PDT 24 Jul 28 06:45:22 PM PDT 24 37137661386 ps
T234 /workspace/coverage/default/42.sram_ctrl_regwen.4215312578 Jul 28 06:36:26 PM PDT 24 Jul 28 06:58:49 PM PDT 24 55902827184 ps
T235 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3610622465 Jul 28 06:33:58 PM PDT 24 Jul 28 06:34:04 PM PDT 24 1646018355 ps
T236 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2819505476 Jul 28 06:37:39 PM PDT 24 Jul 28 06:38:04 PM PDT 24 98404371 ps
T237 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1880090330 Jul 28 06:30:10 PM PDT 24 Jul 28 06:31:13 PM PDT 24 137017950 ps
T238 /workspace/coverage/default/32.sram_ctrl_mem_walk.1379640457 Jul 28 06:33:46 PM PDT 24 Jul 28 06:33:53 PM PDT 24 3307632033 ps
T239 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2718221908 Jul 28 06:36:02 PM PDT 24 Jul 28 06:36:08 PM PDT 24 396385771 ps
T240 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2290917900 Jul 28 06:25:00 PM PDT 24 Jul 28 06:25:04 PM PDT 24 177391073 ps
T241 /workspace/coverage/default/22.sram_ctrl_max_throughput.2944543791 Jul 28 06:30:49 PM PDT 24 Jul 28 06:33:03 PM PDT 24 548313256 ps
T242 /workspace/coverage/default/47.sram_ctrl_smoke.3922693393 Jul 28 06:37:46 PM PDT 24 Jul 28 06:39:42 PM PDT 24 1068761000 ps
T243 /workspace/coverage/default/11.sram_ctrl_regwen.2375160666 Jul 28 06:27:20 PM PDT 24 Jul 28 06:33:01 PM PDT 24 37694380471 ps
T74 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1665400047 Jul 28 06:34:06 PM PDT 24 Jul 28 06:36:24 PM PDT 24 7756990284 ps
T244 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.326603926 Jul 28 06:38:09 PM PDT 24 Jul 28 06:43:17 PM PDT 24 22199230104 ps
T245 /workspace/coverage/default/24.sram_ctrl_bijection.979031642 Jul 28 06:31:21 PM PDT 24 Jul 28 06:32:05 PM PDT 24 762384055 ps
T246 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.435133667 Jul 28 06:32:39 PM PDT 24 Jul 28 06:46:14 PM PDT 24 10201706796 ps
T247 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1141791072 Jul 28 06:25:10 PM PDT 24 Jul 28 06:27:05 PM PDT 24 582532295 ps
T248 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.3930078410 Jul 28 06:35:16 PM PDT 24 Jul 28 06:35:22 PM PDT 24 588343029 ps
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T250 /workspace/coverage/default/7.sram_ctrl_alert_test.1282767028 Jul 28 06:26:11 PM PDT 24 Jul 28 06:26:12 PM PDT 24 15051123 ps
T251 /workspace/coverage/default/30.sram_ctrl_alert_test.2987979939 Jul 28 06:33:16 PM PDT 24 Jul 28 06:33:17 PM PDT 24 16749904 ps
T252 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.4149011055 Jul 28 06:31:26 PM PDT 24 Jul 28 06:31:30 PM PDT 24 59752079 ps
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T254 /workspace/coverage/default/1.sram_ctrl_alert_test.4233369623 Jul 28 06:24:50 PM PDT 24 Jul 28 06:24:51 PM PDT 24 42855852 ps
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T256 /workspace/coverage/default/20.sram_ctrl_alert_test.3788672464 Jul 28 06:30:18 PM PDT 24 Jul 28 06:30:19 PM PDT 24 15250030 ps
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T293 /workspace/coverage/default/40.sram_ctrl_partial_access.407120493 Jul 28 06:36:01 PM PDT 24 Jul 28 06:37:14 PM PDT 24 319018210 ps
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T295 /workspace/coverage/default/18.sram_ctrl_executable.4229516071 Jul 28 06:29:42 PM PDT 24 Jul 28 06:35:11 PM PDT 24 79880174366 ps
T296 /workspace/coverage/default/8.sram_ctrl_regwen.105835150 Jul 28 06:26:25 PM PDT 24 Jul 28 06:30:15 PM PDT 24 4272320031 ps
T297 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.490142771 Jul 28 06:33:44 PM PDT 24 Jul 28 06:33:47 PM PDT 24 100650617 ps
T298 /workspace/coverage/default/48.sram_ctrl_max_throughput.529837868 Jul 28 06:38:09 PM PDT 24 Jul 28 06:38:50 PM PDT 24 87310740 ps
T299 /workspace/coverage/default/43.sram_ctrl_bijection.4072883499 Jul 28 06:36:38 PM PDT 24 Jul 28 06:37:03 PM PDT 24 3164064707 ps
T300 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1278025962 Jul 28 06:28:30 PM PDT 24 Jul 28 06:31:01 PM PDT 24 7128701087 ps
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